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Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is
connected to internal data bus & ALU.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be
executed. Microprocessor increments the program whenever an instruction is being executed, so
that the program counter points to the memory address of the next instruction that is going to be
executed.
Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the
result stored in the accumulator.
These are the set of 5 flip-flops
Sign (S)
Zero (Z)
Auxiliary Carry (AC)
Parity (P)
Carry (C)
Its bit position is shown in the following table
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
8085 Architecture
We have tried to depict the architecture of 8085 with this following image
The following image depicts the pin diagram of 8085 Microprocessor
Address bus
A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus
AD7-AD0, it carries the least significant 8-bit address and data bus.
IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0
These signals are used to identify the type of current operation.
Power supply
There are 2 power supply signals VCC & VSS. VCC indicates +5v power supply and VSS
indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
X1, X2 A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
CLK OUT This signal is used as the system clock for devices connected with the
microprocessor.
These are the instructions used to transfer the data from one register to another register, from
the memory to the register, and from the register to the memory without any alteration in the
content. Addressing modes in 8085 is classified into 5 groups
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is
enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to
backup memory. This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this
interrupt is executed, the processor saves the content of the PC register into the stack and
branches to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the
PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by
resetting the microprocessor.
When INTR signal goes high, the following events can occur
The microprocessor checks the status of INTR signal during the execution of each
instruction.
When the INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal.
When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
Instruction sets are instruction codes to perform some task. It is classified into five
categories.
1. Control
2. Logical
3. Branching
4. Arithmetic
5. Data Transfer
Control Instructions
Example: NOP
HLT none Halt and enter The CPU finishes executing the current instruction and halts
wait state any further execution. An interrupt or reset is necessary to
exit from the halt state.
Example: HLT
DI none Disable The interrupt enable flip-flop is reset and all the interrupts
interrupts except the TRAP are disabled. No flags are affected.
Example: DI
EI none Enable The interrupt enable flip-flop is set and all interrupts are
interrupts enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flipflop
is reset, thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI
RIM none Read interrupt This is a multipurpose instruction used to read the status of
mas interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the
following interpretations.
Example: RIM
SIM none Set interrupt This is a multipurpose instruction and used to implement the
mask 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM
LOGICAL INSTRUCTIONS
CMP R Compare register The contents of the operand (register or memory) are M
or memory with compared with the contents of the accumulator. Both
M accumulator contents are preserved . The result of the comparison is
shown by setting the flags of the PSW as follows:
CPI 8-bit Compare The second byte (8-bit data) is compared with the contents
data immediate with of the accumulator. The values being compared remain
accumulator unchanged. The result of the comparison is shown by
setting the flags of the PSW as follows:
ANA R Logical AND The contents of the accumulator are logically ANDed with
register or M the contents of the operand (register or memory), and the
M memory with result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
accumulator
HL registers. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
ANI 8-bit Logical AND The contents of the accumulator are logically ANDed with
data immediate with the
accumulator 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Opcode Operand Explanation of Description
Instruction
XRA R Exclusive OR The contents of the accumulator are Exclusive ORed with
register or M the contents of the operand (register or memory), and the
M memory with result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
accumulator
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive ORed with
data immediate with the 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
ORA R Logical OR The contents of the accumulator are logically ORed with M
register or the contents of the operand (register or memory), and the
M memory with result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
accumulator
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
ORI 8-bit Logical OR The contents of the accumulator are logically ORed with
data immediate with the 8-bit data (operand) and the result is placed in the
accumulator accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
RLC none Rotate Each binary bit of the accumulator is rotated left by one
accumulator left position. Bit D7 is placed in the position of D0 as well as in
the Carry flag. CY is modified according to bit D7. S, Z, P,
AC are not affected.
Example: RLC
RRC none Rotate Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
Opcode Operand Explanation of Description
Instruction
Example: RRC
RAL none Rotate Each binary bit of the accumulator is rotated left by one
accumulator left position through the Carry flag. Bit D7 is placed in the
through carry Carry flag, and the Carry flag is placed in the least
significant position D0. CY is modified according to bit
D7. S, Z, P, AC are not affected.
Example: RAL
RAR none Rotate Each binary bit of the accumulator is rotated right by one
accumulator right position through the Carry flag. Bit D0 is placed in the
through carry Carry flag, and the Carry flag is placed in the most
significant position D7. CY is modified according to bit
D0. S, Z, P, AC are not affected.
Example: RAR
Example: CMA
CMC none Complement The Carry flag is complemented. No other flags are
carry affected.
Example: CMC
Example: STC
BRANCHING INSTRUCTIONS
Opcode Operand Explanation of Description
Instruction
Example: RET
parity even
Return on
RPO P=0
parity odd
Example: PCHL
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
Opcode Operand Explanation of Description
Instruction
RST 5 0028H
RST 6 0030H
RST 7 0038H
Restart
Interrupt
Address
TRAP 0024H
Arithmetic Instructions
ADD R Add register or The contents of the operand (register or memory) are
memory, to added to the contents of the accumulator and the result is
M accumulator stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the
HL registers. All flags are modified to reflect the result of
Opcode Operand Explanation of Description
Instruction
the addition.
ADC R Add register to The contents of the operand (register or memory) and M
accumulator with the Carry flag are added to the contents of the
M carry accumulator and the result is stored in the accumulator. If
the operand is a memory location, its location is specified
by the contents of the HL registers. All flags are modified
to reflect the result of the addition.
ADI 8-bit data Add immediate to The 8-bit data (operand) is added to the contents of the
accumulator accumulator and the result is stored in the accumulator.
All flags are modified to reflect the result of the addition.
ACI 8-bit data Add immediate to The 8-bit data (operand) and the Carry flag are added to
accumulator with the contents of the accumulator and the result is stored in
carry the accumulator. All flags are modified to reflect the
result of the addition.
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair
16-bit data immediate designated in the operand.
DAD Reg. pair Add register pair The 16-bit contents of the specified register pair are
to H and L added to the contents of the HL register and the sum is
registers stored in the HL register. The contents of the source
register pair are not altered. If the result is larger than 16
bits, the CY flag is set. No other flags are affected.
Example: DAD H
SUB R Subtract register The contents of the operand (register or memory ) are
or memory from subtracted from the contents of the accumulator, and the
M result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents
Opcode Operand Explanation of Description
Instruction
SBB R Subtract source The contents of the operand (register or memory ) and M
and borrow from the Borrow flag are subtracted from the contents of the
M accumulator accumulator and the result is placed in the accumulator. If
the operand is a memory location, its location is specified
by the contents of the HL registers. All flags are modified
to reflect the result of the subtraction.
SUI 8-bit data Subtract The 8-bit data (operand) is subtracted from the contents
immediate from of the accumulator and the result is stored in the
accumulator accumulator. All flags are modified to reflect the result of
the subtraction.
SBI 8-bit data Subtract The contents of register H are exchanged with the
immediate from contents of register D, and the contents of register L are
accumulator with exchanged with the contents of register E.
borrow
Example: XCHG
INR R Increment register The contents of the designated register or memory) are
or memory by 1 incremented by 1 and the result is stored in the same
M place. If the operand is a memory location, its location is
specified by the contents of the HL registers.
INX R Increment register The contents of the designated register pair are
pair by 1 incremented by 1 and the result is stored in the same
place.
Example: INX H
Example: DCX H
DAA none Decimal adjust The contents of the accumulator are changed from a
accumulator binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the auxiliary
flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY
flags are altered to reflect the results of the operation.
Example: DAA
MOV Rd, Rs Copy from This instruction copies the contents of the source
source(Rs) to register into the destination register; the contents of the
M, Rs destination(Rd) source register are not altered. If one of the operands is
a memory location, its location is specified by the
Rd, M contents of the HL registers.
Opcode Operand Explanation of Description
Instruction
MVI Rd, data Move immediate 8- The 8-bit data is stored in the destination register or
bit memory. If the operand is a memory location, its
M, data location is specified by the contents of the HL
registers.
LDA 16-bit Load accumulator The contents of a memory location, specified by a 16-
address bit address in the operand, are copied to the
accumulator. The contents of the source are not altered.
LDAX B/D Reg. Load accumulator The contents of the designated register pair point to a
pair indirect memory location. This instruction copies the contents
of that memory location into the accumulator. The
contents of either the register pair or the memory
location are not altered.
Example: LDAX B
LXI Reg. pair, Load register pair The instruction loads 16-bit data in the register pair
16-bit data immediate designated in the operand.
LHLD 16-bit Load H and L The instruction copies the contents of the memory
address registers direct location pointed out by the 16-bit address into register
L and copies the contents of the next memory location
into register H. The contents of source memory
locations are not altered.
STA 16-bit 16-bit address The contents of the accumulator are copied into the
address memory location specified by the operand. This is a 3-
byte instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address.
STAX Reg. pair Store accumulator The contents of the accumulator are copied into the
indirect memory location specified by the contents of the
operand (register pair). The contents of the
accumulator are not altered.
Example: STAX B
SHLD 16-bit Store H and L The contents of register L are stored into the memory
address registers direct location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
contents of registers HL are not altered. This is a 3-
byte instruction, the second byte specifies the low-
order address and the third byte specifies the high-
order address.
XCHG none Exchange H and L The contents of register H are exchanged with the
with D and E contents of register D, and the contents of register L
are exchanged with the contents of register E.
Example: XCHG
SPHL none Copy H and L The instruction loads the contents of the H and L
registers to the stack registers into
pointer the stack pointer register, the contents of the H register
provide the high-order address and the contents of the
L register provide the low-order address. The contents
of the H
and L registers are not altered.
Example: SPHL
XTHL none Exchange H and L The contents of the L register are exchanged with the
with top of stack stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
exchanged with the next stack location (SP+1);
however, the contents of the stack pointer register are
not altered.
Example: XTHL
Opcode Operand Explanation of Description
Instruction
PUSH Reg. pair Push register pair The contents of the register pair designated in the
onto stack operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the highorder register (B, D, H, A)
are copied into that location. The stack pointer register
is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.
POP Reg. pair Pop off stack to The contents of the memory location pointed out by the
register pair stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
memory location are copied to the high-order register
(B, D, H, A) of the operand. The stack pointer register
is again incremented by 1.
OUT 8-bit port Output data from The contents of the accumulator are copied into the
address accumulator to a I/O port specified by the operand.
port with 8-bit
Example: OUT F8H
address
IN 8-bit port Input data to The contents of the input port designated in the
address accumulator from a operand are read and loaded into the accumulator.
port with 8-bit
Example: IN 8CH
address
Explain bus structure of 8085
1. Address Bus
2. Data Bus
3. Control Bus
Address Bus
Genearlly, Microprocessor has 16 bit address bus. The bus over which the CPU sends out the
address of the memory location is known as Address bus. The address bus carries the address of
memory location to be written or to be read from.
The address bus is unidirectional. It means bits flowing occurs only in one direction, only from
microprocessor to peripheral devices. We can find that how much memory location it can using
the formula 2^N. where N is the number of bits used for address lines.
Data Bus
8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit data starting from
00000000H(00H) to 11111111H(FFH). Here 'H' tells the Hexadecimal Number. It is
bidirectional. These lines are used for data flowing in both direction means data can be
transferred or can be received through these lines. The data bus also connects the I/O ports and
CPU. The largest number that can appear on the data bus is 11111111.
It has 8 parallel lines of data bus. So it can access upto 2^8 = 256 data bus lines.
Control Bus
The control bus is used for sending control signals to the memory and I/O devices. The CPU
sends control signal on the control bus to enable the outputs of addressed memory devices or I/O
port devices.
Some of the control bus signals are as follows:
1. Memory read
2. Memory write
3. I/O read
4. I/O write
explain DMA
ADDRESS BUS
MPU 8257 DMA controller Bus
slave or bus master
memory I/O
HLDA
The Direct Memory Access a process of communication of data transfer controlled by an
external peripherals, the other data transfer method is too slow. The 8085 MP has two pins
available for this type of I/O communication HOLD and HLDA
HOLD:
This is an active high input signal to 8085 from another master requesting the use of the address
and data bus. After receiving the HOLD request, the MPU relinquishes the buses in the machine
cycle. All buses are tristated and a HOLD Acknowledge (HLDA) signal is set out.