10/1/2013

Outline:
Optimized approach
Graph-theoretical algorithm
Euler Path for Optimal Layout
Heuristics
Conclusion
References
Developed by Gregory, 2004
Modified by Li Chen, 2013

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Optimized approach (Euler Path) Two Versions of C (A + B)1

(Observe the input order)
The Euler path technique has
been used in what is called the
standard cell technique,
which results in a dense layout
for CMOS gates and one
polysilicon strip that can serve
as the input to both NMOS
and PMOS devices.
Our main aim is to have a
single strip of diffusion in both
NMOS and PMOS devices.
This depends on the
ordering of the inputs. How
do we determine the best
order?

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Graph the theoretical approach Consistent Euler Path1

X
To reduce the size of an array and an uninterrupted PUN
diffusion strip we need to find this Euler path talked A
C
j C
about previously. This is defined as the path through all B
nodes or vertices (source and drain signals) such that X i VDD
g ( transistor g
each edge( gate inputs)
p ) is onlyy visited exactly
y
X = C (A + B)
once. (vertices maybe visited more than once).
C B j A
Euler paths are not unique. i PDN
Euler paths must be consistent (same ordering in both A B A B C
GND
PUN (pull up network) and PDN (pull down network).
A
Can Run in linear time3. B
C

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The General Algorithm Heuristic Algorithm

1. Enumerate all possible
decompositions to find the
minimum number of Euler
paths that cover the graph.
2. Chain by means of diffusion
area according to the order of
edges in Euler path.
path
3. If more than 2 edges are
necessary to cover the graph
model, then provide a
separation area between each
pair of chains.
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Therefore for the previous
consistent Euler path for the
logic structure we achieve the
optimal layout below.
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(of course life not being so easy)
Theorem:
1) The following example and
any circuit will have a single
Euler path if the number of
inputs to every AND/OR
element is odd. Inaddition,
2) Th
There exist
i t a graph
h model
d l
such that the sequence of
edges on an Euler path
corresponding to the vertical
order of the inputs on a
planar representation of the
logic diagram.
The Heuristic Algorithm
1) To every gate with an even
number of inputs add a pseudo
input.
2) The pseudo input does not
contribute to separation area. But
this input is added so that there is
a minimal combination between
pseudo and real inputs.
3) Construct the graph model
according to the vertical order of
inputs on logic diagram.
4) Chain together the gates by
means of diffusion areas as
indicated by the sequence of
edges on the Euler path. A
pseudo" input gives a separation
between diffusions.
5) Delete Pesudo edges in parallel
and contacting pseudo edges in
series with other edges for final
circuit.
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Example Heuristic Works

We apply our Heuristic
We consider the following logic
approach to the previous
Circuit (a and b), the derived
example and we obtain the
Euler Path (c) and the
following sequence
corresponding Layout. For our
(p1,2,3,1,4,5,p2) where we
Euler path the PUN- and the
remove the pseudo
pseudo inputs
PDN -----.
to get the same layout
previously shown in slide
11. (Note we choose the
combination with the
minimum interlaced with real
inputs) hence circuit (b).

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Analysis Analysis (continued)

1. It must be noted that the
Here in (b) we see the final
heuristic algorithm may not
always give the optimal Euler Path interpretation
layout but if the resulting
sequence. However, if no the corresponding circuit
separation areas are diagram (c) and the a final
obtained then this is
the optimal solution. layout.
2. The heuristic gives excellent
results for circuits which do not
have a Euler path. This is
Illustrated in the four-bit carry
look-ahead adder3 circuit
shown in this slide.

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Conclusion
This Presentation has given a brief incite into
optimizing the layout of complex CMOS gates.
Using the Euler path approach and a heuristic
algorithm. The results show that by use of this
approach h we can optimize considerably
d bl on area
in our layout. Further work can be done to
simulate the real gain of this method in terms
of power and performance of a particular
design.
Gregory Holder
10/1/2013
References
1. Digital integrated circuits 2nd edition
2. Uehara, T. and Vancleemput, W. M optimal
layout of CMOS Functional Arrays.
3. Robert Sedgewick Algorithms
Algorithms in C third
edition.
4. Forbes, B. E. Silicon-on Sapphire Technology
Produces High-Speed Single- Chip Processor,
Hewlett-Packard Journal, April 1977,pp 2-8.
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