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Features
Meets Intels VR12.5 Specifications Reduced Enable to First SVID Command Latency
Implements VR12.6 PS4 State and SVID Reporting PhasetoPhase Dynamic Current Balancing
Mixed Voltage/Current Mode, Dual Edge Modulation Switching Frequency Range of 280 kHz to 1.5 MHz
for Fastest Initial Response to Transient Loading Starts up into PreCharged Loads while Avoiding False
High Impedance Differential Voltage Amplifier OVP
High Performance Operational Error Amplifier Compatible with DrMOS Power Stages
High Impedance Total Current Sense Amplifier Powersaving Phase Shedding
True Differential Current Sense Amplifiers for Vin Feedforward Ramp Slope Compensation
Balancing Current in Each Phase Pin Programming for Internal SVID parameters
Digital Soft Start Ramp Output Over Voltage Protection (OVP) & Under
Dynamic Reference Injection Voltage Protection (UVP)
Accurate Total Summing Current Amplifier Over Current Protection (OCP)
Lossless Inductor DCR Current Sensing Power Good Output with Internal Delays
Summed, Thermally Compensated Inductor Current This is a PbFree Device
Sensing for Adaptive Voltage Positioning (AVP)
Applications
48 mV/ms Fast Output Slew Rate (NCP81105)
Desktop and Notebook Microprocessors
10 mV/ms Fast Output Slew Rate (NCP81105H)
Programmable Slow Slew Rates as a Fraction of Fast
Slew Rate
1.3V
EN 1 ENABLE CSREF
UVLO & EN
VCC 2 COMPARATORS
VSP VSN 36 VSP
VRMP VSP
DIFF
OVP AMP VSN
OVP
THERMAL _
VRHOT# 3 35 VSN
MONITOR
DAC DAC
DAC CSCOMP
34 DIFFOUT
SDIO 4 SVID ENABLE DAC
INTERFACE FEED
ALERT# 5 & LOGIC DRVON FORWARD
SCALING
OCP
SCLK 6
OVP _ 33 FB
ENABLE PS#
+
DATA ERROR
REGISTERS AMP 1.3V
VR READY OVERCURRENT
VR_RDY 8
LOGIC COMPARATORS 32 COMP
CURRENT
ROSC 7 OCP MONITOR
28 IOUT
IOUT
TSENSE 9
MUX Buffer OVERCURRENT
27 ILIM
IMAX 16 PROGRAMMING
(VSP VSN) 26 CSCOMP
INT_SEL 17 ADC
IOUT ENABLE _ 25 CSSUM
VBOOT 30
BALANCE 21 CSN3
PWM
GENERATORS AMPLIFIERS
20 CSP3
I2
PWM2
PWM3
PWM1
I3 19 CSN1
I1
18 CSP1
DRVON
15 DRVON
PS#
ZERO 11 SMOD
OVP CURRENT
DETECTION 14 PWM1
OCP
DRVON
PS# 13 PWM3
POWER
STATE 12 PWM2
NCP81105 GATE
10 OD#
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2
NCP81105, NCP81105H
DIFFOUT
VBOOT
DGAIN
COMP
VRMP
IOUT
VSN
VSP
FB
36
35
34
33
32
31
30
29
28
EN 1 27 ILIM
VCC 2 26 CSCOMP
VRHOT# 3 25 CSSUM
SDIO 4 24 CSREF
NCP81105
ALERT# 5 23 CSN2
TAB: GROUND
SCLK 6 22 CSP2
ROSC 7 21 CSN3
VR_RDY 8 20 CSP3
TSENSE 9 19 CSN1
11
10
12
13
14
15
16
17
18
DRVON
OD#
IMAX
SMOD
PWM2
PWM3
PWM1
INT_SEL
CSP1
Figure 2. Pin Connections
(Top View)
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3
NCP81105, NCP81105H
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4
NCP81105, NCP81105H
VCIN VIN
BOOT
DRVON
EN
CB1
DRMOS
PWM1 PHASE
PWM
VSWH
SMOD
SMOD
NCP81105
VCIN VIN
BOOT
EN
CB2
DRMOS
PWM2 PHASE
PWM
VSWH
OD#
SMOD
VCIN VIN
BOOT
EN
CB3
DRMOS
PWM3 PHASE
PWM
VSWH
SMOD
COUT
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5
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF CSPP2
DIFFOUT COMP R138 R27
R34 100 100K
DGAIN 10.0K
VSN
C85
VSS_SENSE R12 22nF
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0.01uF 73.2K
37
36
35
34
33
32
31
30
29
28
R38 165K
R71 10.0
V_1P05_VCCP V5S R161
0.15uF 23.7K C155
VBOOT
COMP
VSP
VRMP
DGAIN
EPAD
VSN
DIFFOUT
IOUT R140
FB
R156
R162
R155
75.0
130
130
54.9
EN ILIM
6
VCC 2 26 CSCOMP 68pF
VCC CSCOMP 10.0K
VR_HOT3 U1 25 CSSUM C80
VR_HOT SDIO 4 VRHOT# CSSUM 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 R185 22nF
ALERT SCLK 6 ALERT# CSN2 22 CSN1
SCLK ROSC 7 SCLK CSP2 21 10.0
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19 10nF
TSENSE CSN1
INT_SEL
R154
DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN2
CSP1
IMAX
OD#
CSP2
CSN3
CSP3
10
12
13
14
15
16
17
18
11
TSENSE CSN1
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 95A maximum output current
PWM1 75.0K 51.1K
close to L1
PWM3 114A current limit
PWM2
SMOD
1.5mOhm loadline
OD# 1.7V boot voltage
VDC V5S VDC
VDC
1
2
42
14
13
12
10
38
42
14
13
12
10
38
11
11
C37
9
8
9
8
4
V5S C4 V5S
2 2
0.22uF V5S 0.22uF
BOOT
BOOT
VCIN VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
THWN
THWN
3 7 3 7
NC PHASE L1 NC PHASE L2
C5 15 MPCG0740LR12 C44 15 MPCG0740LR12
1uF VSWH 43 120nH VCCU 1uF VSWH 43 VCCU
U2 U3 120nH
VSWH 35 0.7mOhm VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1 1 NCP5338 VSWH 34
SMOD OD# CSNN2
ZCD_EN# VSWH 33 ZCD_EN# VSWH 33
32 SW1 32 SW2
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
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GH
GH
GL
GL
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6
5
Total VCORE Output
7
VDC Capacitor: VCCU
26 X 22uF(0805)
1
42
14
13
12
10
38
11
V5S C28
9
8
2 4
0.22uF
BOOT
VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
THWN
C52 C67 C68 C78 C84 C98 C99 C100 C196
3 7 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF DNP
NC PHASE L3
C29 15 MPCG0740LR12
1uF
U4 VSWH 43 120nH VCCU LOCATE BETWEEN L1 & L2 (PRIMARY SIDE)
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSNN3
OD# ZCD_EN# VSWH 33
VSWH 32 SW3 C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
VSWH 31 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP3 LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
40
PWM3 PWM
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GH
GL
C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6
5
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF
DIFFOUT COMP
R34 100
VSN
DGAIN
VSS_SENSE
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0.01uF 73.2K
37
36
35
34
33
32
31
30
29
28
R38 165K
R71 10.0
V_1P05_VCCP V5S R161
0.15uF 23.7K C155
VBOOT
COMP
VSP
VRMP
DGAIN
EPAD
VSN
DIFFOUT
IOUT R140
FB
R156
R162
R155
75.0
130
130
54.9
EN ILIM
8
VCC 2 26 CSCOMP 68pF
VCC CSCOMP 10.0K
VR_HOT3 U1 25 CSSUM C80
VR_HOT SDIO 4 VRHOT# CSSUM 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 R185 22nF
ALERT SCLK 6 ALERT# CSN2 22 CSN1
SCLK V5S 10.0
ROSC 7 SCLK CSP2 21
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19 R128 10nF
TSENSE CSN1
INT_SEL
R154 1K
DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN2
CSP1
IMAX
OD#
CSN3
CSP3
10
12
13
14
15
16
17
18
11
TSENSE CSN1
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 55A maximum output current
PWM1 43.2K 51.1K
close to L1
PWM3 66A current limit
SMOD
1.5mOhm loadline
OD# 1.7V boot voltage
VDC V5S
1
38
11
9
8
V5S C4
2
0.22uF
Capacitor:
BOOT
THWN
VCIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
3 7 20 X 22uF(0805)
NC PHASE L1
C5 + 11 X 10uF(0805)
15 MPCG0740LR12
1uF U2 VSWH 43 120nH VCCU
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1
SMOD ZCD_EN# VSWH 33
32 SW1
C52 C67 C68 C78 C84 C98 C99 C100 C196
VSWH 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22Uf
29
VSWH CSPP1
40
PWM1 PWM
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
GH
GL
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10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6
9
VDC C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
1
42
14
13
12
10
38
11
V5S C28
9
8
4
2
BOOT
VCIN THWN 0.22uF
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
3 7
NC PHASE L3
C29 15 MPCG0740LR12
1uF U4 VSWH 43 120nH VCCU
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSNN3
OD# ZCD_EN# VSWH 33
VSWH 32 SW3
VSWH 31
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP3
40
PWM3 PWM
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GH
GL
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
6
5
R50 37.4 C56 270pF R43 4.75K
DIFFOUT FB C57
R37 1.00K 10pF
DIFFOUT COMP
R34 100
VSN
DGAIN
VSS_SENSE
VBOOT
C51
VSENSE R19 R16 RT11
place
1nF close
69.8K 24.9K 220K
VCC_SENSE VSP
R48 100 R40
to L1
VCCU VRMP
VDC
75.0K
COMP
DIFFOUT
VRMP
DGAIN
VSP
EPAD
VSN
IOUT
FB
NCP81105, NCP81105H
R156
ILIM
R162
R155
75.0
10.0K
130
130
54.9
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SDIO 4 24 CSREF
SDIO R78 43.2 ALERT_VR 5 SDIO NCP81105 CSREF 23 CSN1
ALERT SCLK 6 ALERT# CSN2 22 10.0
SCLK ROSC 7 SCLK CSP2 21 V5S
VR_RDY 8 ROSC CSN3 20 C66
VR_RDY 9 VR_RDY CSP3 19
10
R128 10nF
INT_SEL
R154 TSENSE CSN1 1K
DRVON
SMOD
PWM2
PWM3
PWM1
80.6K CSN3
CSP1
IMAX
OD#
CSN1
10
12
13
14
15
16
17
18
11
TSENSE
CSP1
RT12 R31 INT_SEL
220K 11.0K C81 IMAX 790kHz switching frequency
place 1nF
DRVON R25 R26 32A maximum output current
close to L1 PWM1
PWM3
25.5K 51.1K
39A current limit
PWM2
SMOD
2.0mOhm loadline
OD# 1.7V boot voltage
VDC V5S
1
10
38
11
V5S
9
8
2
C4 Capacitor:
NCP81105, NCP81105H
0.22uF
BOOT
VCIN 16 X 22uF(0805)
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
THWN
3 7
NC PHASE L1 + 11 X 10uF(0805)
C5 15 MPCG0740LR12
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1uF VSWH 43 VCCU
U2 120nH
VSWH 35 0.7mOhm
1 NCP5338 VSWH 34 CSN1
SMOD ZCD_EN# VSWH 33
VSWH 32
SW1 C52 C67 C68 C78 C84 C98 C99 C100 C196
11
VSWH 31 DNP DNP DNP 22uF 22uF 22uF 22uF 22uF DNP
39 VSWH 30
DRVON DISB# VSWH 29
VSWH CSPP1 LOCATE NEAR L1 (PRIMARY SIDE)
40
PWM1 PWM
CGND
CGND
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
C214 C41 C48 C49 C215 C216 C217 C204 C205 C206 C207
GH
GL
10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
6
5
36
41
37
16
17
18
19
20
21
22
23
24
25
26
27
28
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
C212 C213 C226 C227 C176 C177 C183 C184 C273 C271 C272
22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF 22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
NCP81105, NCP81105H
THERMAL INFORMATION
Description Symbol Typ Unit
Thermal Characteristic RqJA _C/W
QFN36 Package (Notes 1 and 2) 68
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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13
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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14
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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15
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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16
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range 10C TA 100C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
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17
NCP81105, NCP81105H
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18
NCP81105, NCP81105H
SCLK
VR
latch
SDIO
tHLD
tSU
SCLK
VR
send
SDIO
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19
NCP81105, NCP81105H
VCC UVLO N/A N/A N/A Resistive pull Resistive pull down Resistive pull down
0 < VCC < threshold down
VRMP > threshold
VRMP UVLO N/A N/A N/A Resistive pull Resistive pull down Resistive pull down
VCC > threshold down
0 < VRMP < threshold
Soft Start Low Operational Active High Low until first PWM1 Low until first PWM2
EN > threshold pulse or PWM3 pulse
VCC > threshold
VRMP > threshold
Normal Operation High Operational Active High High in PS0 & PS1; High in PS0; Low in N/A
EN > threshold High or may toggle in PS1, PS2, & PS3
VCC > threshold PS2 & PS3
VRMP > threshold
Over Voltage Low Low DAC + 400 mV High High/ Toggles during High/ Toggles during EN low or cycle
output rampdown output rampdown power
Under Voltage Low Operational DACDroop High High High Output voltage >
300 mV DACDroop
300 mV
Over Current Low Operational Last DAC Code Low Low Low EN low or cycle
+ 400 mV power
VID Code = 00h Low Low Disabled High (PWM Low Low Set Valid VID
outputs low) Code
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NCP81105, NCP81105H
EN = 0 EN = 1
VCC < UVLO
Calibrate
Drive Off
Soft Start
Ramp
DAC = Vboot
Soft Start
Ramp
OVP
DAC = VID
VS > OVP
Normal
VR_RDY
VS > UVP
VS < UVP
UVP
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21
NCP81105, NCP81105H
General
The NCP81105 is a single output, onetothree phase, dualedge modulated PWM controller with a serial VID control
interface designed to meet the Intel VR12.5 & VR12.6 specifications. The NCP81105 implements PS0, PS1, PS2, PS3 and
PS4 power states. It is designed to work in notebook and desktop CPU power supply applications.
Power Status PWM Output Operating Mode
PS0 Multiphase, fixed frequency, dual edge modulation (RPM modulation when optioned for single phase), inter-
leaved PWM outputs (CCM mode)
PS1 Singlephase (PWM1) COT (CCM mode; Phases 2 & 3 disabled by OD#)
PS2 Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS3 Singlephase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS4 No switching; Memory retained; SVID active
For 81105, the VID code change rate is controlled with the SVID interface with three options as below:
Register Address (Contains
SVID Command the slew rate of VID code
DVID Option Code Feature change)
SetVID_Fast 01h 48 mV/ms VID code change slew rate 24h
SetVID_Slow 02h 12 mV/ms VID code change slew rate** 25h
SetVID_Decay 03h No control, VID code down N/A
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.
For 81105H, the VID code change rate is controlled with the SVID interface with three options as below:
Register Address (Contains
SVID Command the slew rate of VID code
DVID Option Code Feature change)
SetVID_Fast 01h 10 mV/ms VID code change slew rate 24h
SetVID_Slow 02h 2.5 mV/ms VID code change slew rate** 25h
SetVID_Decay 03h No control, VID code down N/A
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.
Serial VID
The NCP81105 supports the Intel serial VID (SVID) interface. It communicates with the microprocessor through three wires
(SCLK, SDIO, ALERT#). The table of supported registers is shown below.
Index Name Description Access Default
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to
00h Vendor ID R 1Ah
ON Semiconductor is 0x1Ah
01h Product ID Uniquely identifies the VR product. The VR vendor assigns this number. R 15h
Product Uniquely identifies the revision or stepping of the VR control IC. The VR
02h R 04h
Revision vendor assigns this data.
Product date
03h R 00
code ID
05h Protocol ID Identifies the SVID Protocol the NCP81105 supports R 03h
Informs the Master of the NCP81105s Capabilities,
1 for supported, 0 for not supported
Bit 7: Iout_format; Reg 15 FFh = Icc_Max (=1)
Bit 6: ADC Measurement of Temp; Supported (= 1)
Bit 5: ADC Measurement of Pin; Not supported (= 0)
06h Capability R D7h
Bit 4: ADC Measurement of Vin; Supported (= 1)
Bit 3: ADC Measurement of Iin; Not supported (= 0)
Bit 2: ADC Measurement of Pout; Supported (= 1)
Bit 1: ADC Measurement of Vout; Supported (= 1)
Bit 0: ADC Measurement of Iout; Supported (= 1)
Data register read after the ALERT# signal is asserted. Conveying the status
10h Status_1 R 00h
of the VR.
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NCP81105, NCP81105H
8 bit binary word ADC of current. This register reads 0xFF when the output
15h I_out R 01h
current is at ICC_Max
8 bit binary word ADC of output voltage, measured between VSP and VSN.
16h V_out R 01h
LSB size is 8 mV
17h VR_Temp 8 bit binary word ADC of temperature. Binary format in deg C, IE 100C = 64h. R 01h
8 bit binary word representative of output power. The output voltage is
18h P_out R 01h
multiplied by the output current value and the result is stored in this register.
8 bit binary word ADC of input voltage, measured at VRMP pin. LSB size is
1Ah V_in R 00h
112 mV
Status 2 Last When the status 2 register is read, its contents are copied into this register.
1Ch R 00h
read The format is the same as the Status 2 Register.
Data register containing the ICC_Max supported by the platform. The value is
21h ICC_Max measured at the IMAX pin upon power up and placed in this register. From R 00h
that point on, the register is read only.
Data register containing the max temperature the platform supports and the
22h Temp_Max level VR_hot asserts. This value defaults to 100C and is programmable over R/W 64h
the SVID Interface
Slew Rate for SetVID_fast commands. Binary format in mV/ms.
24h SR_fast NCP81105 R 32h
NCP81105H R 0Ah
Slew Rate for SetVID_slow commands. A fraction of the SR_fast rate (register
24h) determined by register 2Ah. Binary format in mV/ms
25h SR_slow
NCP81105 R 0Ch
NCP81105H R 03h
The Boot voltage is programmed using a resistor on the VBOOT pin which is
26h Vboot sensed on power up. The NCP81105 will ramp to Vboot and hold at Vboot until R 00h
it receives a new SVID SetVID command to move to a different voltage.
0001 = Fast_SR/2
SR_Slow 0010 = Fast_SR/4: default
2Ah R/W 02h
selector 0100 = Fast_SR/8
1000 = Fast_SR/16
Reflects the latency of exiting the PS4 state. The exit latency is defined as the
PS4 exit
2Bh time duration, in us, from the ACK of the SETVID Slow/Fast command to the R 8Ch
latency
beginning of the output voltage ramp.
Reflects the latency of exiting the PS3 state. The exit latency is defined as the
PS3 exit
2Ch time duration, in us, from the ACK of the SETVID Slow/Fast command until the R 55h
latency
NCP81105 is capable of supplying max current of the commanded PS state.
Reflects the latency from Enable assertion to the VR controller being ready to
Enable to accept an SVID command. The latency is defined as the time duration, in ms:
2Dh ready for SVID (x/16)*2Y. R CAh
time X = bits [3:0]: 4 bit value 0000 to 1111
Y = bits [7:4]: 4 bit value 0000 to 1111
Programmed by master and sets the maximum VID the VR will support. If a
higher VID code is received, the VR will respond with a not supported
30h Vout_Max RW B5h
acknowledgement. VR12.5 & VR12.6 VID format, e.g., B5h = 2.3 V (see VID
Table)
Data register containing currently programmed VID voltage. VID data format.
31h VID setting RW 00h
VR12.5 & VR12.6 VID format, e.g., 97h = 2.0 V
32h Pwr State Register containing the current programmed power state. RW 00h
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NCP81105, NCP81105H
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NCP81105, NCP81105H
1 Tie CSN3 to VCC through 2 kW; Tie CSN2, CSP2 & CSP3 to ground;
CSN1 connected normally Float PWM2, PWM3 & OD#
V DROOP + V CSCOMP Droop Gain Scaling (see the Droop Gain Table)
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NCP81105, NCP81105H
Rin1 Cf
Rf Cf1
Cin Rin2
_ COMP
+
Vbias ERROR
Cf
Rin1
Cin Rin2 Rf
_ COMP
+
Vbias ERROR
Initial tuning should be based on traditional Type 3 compensation. When ideal Type 3 component values have been
determined, the closest setting for the internal integrator is given by the following equation:
INT_SETTING + 4.83 10 12 Rf Rin1 CF1; Rf & Rin1 in Ohms , Cf1 in nF
The internal integrator is programmed using the INT_SEL pin according to the following table:
INTEGRATOR TABLE
RINT_SEL INT_SETTING
10k 1
22k 2
36k 4
51k 8
68k 10
91k 12
120k 16
160k 32
220k 64
Recalculation of the initial tuning should be performed using the Cf1 value given by the Cf1 equation below in order to
determine whether readjustment of other components would provide more optimal compensation.
Cf1 (nF) + 2.07 10 5 INT_SETTING(Rf Rin1)
If an acceptable tuning cannot be produced by the closest Equivalent Type 3 Cf1, then reoptimization should be tried with
a different internal integrator setting.
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NCP81105, NCP81105H
CSNx
CSPx
RCSN CCSN
SWNx VOUT
L PHASE
R CSN + DCR LPHASE
C CSN * DCR 1 2
Figure 14.
The individual phase current signals are combined with the COMP and ramp signals at each PWM comparator input. In this
way, current is balanced via a current mode control approach.
CSN1
Cref
CSN2 Rref1
SWN2 Rph1
Ccs1
SWN3 Rph2
Ccs2
Rph3
RCS2 RCS1
Rth
Figure 15.
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NCP81105, NCP81105H
An NTC thermistor (Rth) in the feedback network placed near the Phase 1 inductor senses the inductor temperature and
compensates both the DC gain and the filter time constant for the DCR change with temperature. The values of Rcs1 and Rcs2
are set based on the effect of temperature on both the thermistor and inductor. The thermistor should be placed near the Phase
1 inductor so that it measures the temperature of the inductor providing current in the PS1 power mode.
The pole frequency (FP) of the CSCOMP filter should be set equal to the zero frequency (FZ) of the output inductor. This
causes the total current signal to contain only the component of inductor voltage caused by the DCR voltage, and therefore to
be proportional to inductor current. Connecting Ccs2 in parallel with Ccs1 allows fine tuning of the pole frequency using
commonly available capacitor values. It is best to perform fine tuning during transient testing.
DCR@25 C
FZ +
2 * PI * L Phase
1
FP +
2 * PI * Rcs2 ) * (Ccs1 ) Ccs2)
Rcs1*Rth@25 C
Rcs1)Rth@25 C
Rcs2 ) Rcs1)Rth
Rph
* Iout LIMIT * DCR V CSCOMPCSREF@ILIMIT
R LIMIT + or R LIMIT +
I DS I DS
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NCP81105, NCP81105H
Rth
Rph1 Ccs1
SWN2
Rph2
SWN3
_ CONTROLLER
Rph3 CSSUM CSCOMP
CSN1 CSREF +
Rref1
CSN2 SCALING DGAIN
Rdgain
Rref2
CSN3
to Remote
Rref3 Cref Sense Amplifier
ILIM
Rilim
buffer IOUT
Current Riout
Mirror
Current Limit
Comparators
Figure 16.
Programming IOUT
The IOUT pin sources a current equal to the ILIM current gained by the IOUT Current Gain. The voltage on the IOUT pin
is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to
ICCMAX generates a 2 V signal on IOUT. A pullup resistor to 5 V VCC can be used to offset the IOUT signal positive if
needed.
V DIMAX * R LIMIT
R IOUT +
* Iout
R CS1*Rth
R )
CS2 R )Rth
AI IOUT * CS1
ICC_MAX * DCR
Rph
Programming ICC_MAX
The SVID interface conveys the platform ICC_MAX value to the CPU from register 21h. A resistor to ground on the
IMAX pin programs this register at the time the part in enabled. Current is sourced from this pin to generate a voltage on the
program resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less
than 10k.
R * I IMAX * 256 A
ICC_MAX 21h +
V IMAXFS
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NCP81105, NCP81105H
DVID UP
INCREMENT
CURRENT
PULSES
DAC
DAC
VSN
Figure 17.
Programming TSENSE
A temperature sense input is provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage
on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter and
then digitally converted to temperature and stored in SVID register 17h. A 220k NTC similar to the Murata
NCP15WM224E03RC should be used.
Precision Oscillator
A programmable precision oscillator is provided to control the switching frequency of each phase. The oscillator serves as
the master clock to the ramp generator circuits, which each run at the same frequency. The ROSC pin sources a current into
an external programming resistor. The voltage present at the ROSC pin is read by the internal ADC and used to set the frequency
according to the following table.
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NCP81105, NCP81105H
Vin
Duty
The VRMP pin also has a UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin
is a high impedance input when the controller is disabled or put into PS4. The resistance of an RC filter at the VRMP pin should
not exceed 10 kW.
PWM Comparators
The noninverting input of each comparator (one for each phase) is connected to the summation of the output of the error
amplifier (COMP) and each phase current (IL * DCR * Phase Balance Gain Factor). The inverting input is connected to the
triangle ramp voltage of that phase. The output of the comparator generates the PWM output.
During steady state PS0 operation, the main rail PWM pulses are centered on the valley of the triangle ramp waveforms and
both edges of the PWM signals are modulated. During a transient event, the duty cycle can increase rapidly as the error amp
signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load.
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NCP81105, NCP81105H
OD#
PWM1
DRVH1SW1
PH1
INDUCTOR
CURRENT
AVERAGE PHASE CURRENT
0
SMOD
DRVL1
Figure 18.
Protection Features
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined slew rate in the spec table. The CSN2 and CSN3 pins will start out applying a test resistance to collect data on
phase count. After the configuration data is collected, the controller is enabled and sets the OD# and SMOD signals low to force
the drivers to stay in diode mode. DRVON will then be asserted to enable the drivers. A period of time after the controller senses
that DRVON is high, the COMP pin is released to begin softstart. The DAC ramps from zero to the target DAC code and the
PWM outputs will begin to fire. SMOD will go high when the first PWM1 pulse is produced to preclude discharge of a
precharged output. Upon PWM2 or PWM3 going high for the first time, OD# is set high.
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NCP81105, NCP81105H
SoftStart Sequence
VCC TA
EN
DrMOS Enabled
DRON
Softstart Delay
DAC
COMP
PWM1
SMOD
PWM2
OD#
VOUT
Figure 19.
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NCP81105, NCP81105H
VSPVSN VSPVSN
DAC DAC
Fault Fault
(VSP short OVP (VSP short OVP
to ground) Triggered to ground) Triggered
Rampdown Rampdown
Latched Latched
DAC DAC
PS0 PS1
Figure 20.
VSPVSN (precharged)
Target VID
Reached
DAC
0
PWM
SMOD
OD#
Figure 21.
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NCP81105, NCP81105H
CONTROLLER
CSCOMP
43
Ccs1 Ccs2 Rcs1 Rth
KEEP THIS PATH AS SHORT PLACE AS CLOSE
AS POSSIBLE, AND WELL AWAY AS POSSIBLE TO
_ 42
CSSUM FROM SWITCHNODE LINES PHASE 1 INDUCTOR
CSREF Rcs2
+ 40
Rph1 Rph2 Rref1 Rref2
TO INDUCTOR
_ 34
CSP1 SWITCHNODE
Ccsp1 Rcsp1 TERMINAL
CSN1
+ 35 TO INDUCTOR
VOUT TERMINAL
TO INDUCTOR
_ 38
CSP2 SWITCHNODE
TERMINAL
CSN2 Ccsp2 Rcsp2
+ 39 TO INDUCTOR
VOUT TERMINAL
PER PHASE CURRENT SENSE
RC SHOULD BE PLACED
CLOSE TO CSPx PINS
Figure 22.
Place the VCC decoupling caps as close as possible to the controller VCC pin. For any RC filter on the VCC pin, the resistor
should be no higher than 5 W to prevent large voltage drop.
The small feedback cap from COMP to FB should be as close to the controller as possible. Keep the FB traces short to
minimize their capacitance to ground.
ORDERING INFORMATION
Device Package Shipping
NCP81105MNTXG QFN36 5000 / Tape & Reel
(PbFree)
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NCP81105, NCP81105H
PACKAGE DIMENSIONS
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
L1
3. DIMENSION b APPLIES TO PLATED
PIN ONE TERMINAL AND IS MEASURED BETWEEN
LOCATION
0.15 AND 0.30mm FROM THE TERMINAL TIP.
DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS
E MILLIMETERS
DIM MIN MAX
A 0.80 1.00
0.15 C EXPOSED Cu MOLD CMPD A1 0.05
A3 0.20 REF
b 0.15 0.25
0.15 C TOP VIEW D 5.00 BSC
D2 3.40 3.60
E 5.00 BSC
DETAIL B E2 3.40 3.60
DETAIL B (A3) ALTERNATE
0.10 C e 0.40 BSC
CONSTRUCTION
K 0.35 REF
A L 0.30 0.50
L1 0.15
0.08 C A1
SEATING
NOTE 4 SIDE VIEW C PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
0.10 M C A B
D2 5.30
DETAIL A 36X
10
K 3.64 0.63
19 0.10 M C A B
1
E2
3.64 5.30
1
36
36X L 36X b
e
0.10 M C A B
PKG 36X
0.05 M C NOTE 3 OUTLINE 0.40 0.25
BOTTOM VIEW PITCH
DIMENSIONS: MILLIMETERS
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and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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