Decoder

In digital electronics, a decoder can take the form of a multiple-input, multiple-

output logic circuit that converts coded inputs into coded outputs, where the input
and output codes are different e.g. n-to-2n , binary-coded decimal decoders.
Decoding is necessary in applications such as data multiplexing, 7 segment display
and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND
gate is "High" (1) only when all its inputs are "High." Such output is called as
"active High output". If instead of AND gate, the NAND gate is connected the output
will be "Low" (0) only when all its inputs are "High". Such output is called as "active
low output".

A decoder is a circuit which has n inputs and 2n outputs, and outputs 1 on the wire
corresponding to the binary number represented by the inputs.
For example, a 2-4 decoder

i1 i0 d3 d2 d1 d0 d3 = i1i0

0 0 0 0 0 1
0 1 0 0 1 0 d2 = i1 i0
1 0 0 1 0 0
1 1 1 0 0 0

d1 = i1 i0

d0 = i1 i0
Multiplexer

In electronics, a multiplexer or mux is a device that selects one of several analog or

digital input signals and forwards the selected input into a single line. A multiplexer
of 2n inputs has n select lines, which are used to select which input line to send to
the output. An electronic multiplexer can be considered as a multiple-input, single-
output switch i.e. digitally controlled multi-position switch. The digital code applied
at the select inputs determines which data inputs will be switched to output.

A common example of multiplexing or sharing occurs when several peripheral

devices share a single transmission line or bus to communicate with computer.
Each device in succession is allocated a brief time to send and receive data. At any
given time, one and only one device is using the line. This is an example of time
multiplexing since each device is given a specific time interval to use the line.
A multiplexer is a device which allows one of a number of inputs to be routed to a
single output. Here is a 4-1 multiplexer.
S=0 then z=A but when s=1 then z=b

Z=(AS)+(BS)
Demultiplexer

A demultiplexer (or demux) is a device taking a single input signal and selecting
one of many data-output-lines, which is connected to the single input. A multiplexer
is often used with a complementary demultiplexer on the receiving end. A
demultiplexer is a single-input, multiple-output switch. Demultiplexers take one
data input and a number of selection inputs, and they have several outputs. They
forward the data input to one of the outputs depending on the values of the
selection inputs.

Demultiplexers are sometimes convenient for designing general purpose logic,

because if the demultiplexer's input is always true, the demultiplexer acts as a
decoder. This means that any function of the selection bits can be constructed by
logically OR-ing the correct set of outputs. Demultiplexer is called as a distributor,
since it transmits the same data to different destinations.
A demultiplexer of 2n outputs has n select lines, which are used to select which
output line to send the input. A demultiplexer is also called a data distributor.

A 1 to 2 demultiplexer uses 1 select line (S) to determine which one of the 2

outputs (Y0, Y1) is routed from the input (D). Its simplified truth table is:
Truth Table

S Y1 Y0

0 0 D

1 D 0

Bool Expression
Y1 = D * S
Y0 = D * ~S
Truth Table
S D Y1 Y0
0 0 0 0
0 1 0 1
1 0 0 0
1 1 1 0
8-to-1 Multiplexer
An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input
select lines S2 through S0 and a single output line Y. Depending on the select lines
combinations, multiplexer decodes the inputs.
The below figure shows the block diagram of an 8-to-1 multiplexer with enable
input that enable or disable the multiplexer. Since the number data bits given to
the MUX are eight then 3 bits (23=8) are needed to select one of the eight data
bits.

The truth table for an 8-to1 multiplexer is given below with eight combinations of
inputs so as to generate each output corresponds to input.
For example, if S2= 0, S1=1 and S0=0 then the data output Y is equal to D2.
Similarly the data outputs D0 to D7 will be selected through the combinations of
S2, S1 and S0 as shown in below figure.

From the above truth table, the Boolean equation for the output is given as
From the above Boolean equation, the logic circuit diagram of an 8-to-1
multiplexer can be implemented by using 8 AND gates, 1 OR gate and 7 NOT gates
as shown in below figure. In the circuit, when enable pin is set to one, the
multiplexer will be disabled and if it is zero then select lines will select the
corresponding data input to pass through the output.

A typical IC 74151 is an 8-to-1 multiplexer with eight inputs and two outputs. The
two outputs are active low and active high outputs. It has three select lines A, B
and C and one active low enable input. The pinout of this IC is given below.
1-to-4 Demultiplexer
A 1-to-4 demultiplexer has a single input (D), two selection lines (S1 and S0) and
four outputs (Y0 to Y3). The input data goes to any one of the four outputs at a
given time for a particular combination of select lines.
This demultiplexer is also called as a 2-to-4 demultiplexer which means that two
select lines and 4 output lines. The block diagram of 1:4 DEMUX is shown below.

The truth table of this type of demultiplexer is given below. From the truth table it
is clear that, when S1=0 and S0= 0, the data input is connected to output Y0 and
when S1= 0 and s0=1, then the data input is connected to output Y1.
Similarly, other outputs are connected to the input for other two combinations of
select lines.

From the table, the output logic can be expressed as min terms and are given
below.
Where D is the input data, Y0 to Y3 are output lines and S0 & S1 are select lines.
From the above Boolean expressions, a 1-to-4 demultiplexer can be implemented
by using four 3-input AND gates and two NOT gates as shown in figure below. The
two selection lines enable the particular gate at a time.
So depends on the combination of select inputs, input data is passed through the
selected gate to the associated output.

This type of demultiplexer is available in IC form and a typical IC 74139 is most

commonly used dual 1-to-4 demultiplexer. It has two independent demultiplexers
and each DEMUX accepts two binary inputs as select lines and four mutually
exclusive active-low outputs.
Both demultiplexers share a common set of selection lines so they are selected in
parallel. Also, each demultiplexer consists of enable pin or data input, for one
demultiplexer it is active high data input and for other it is active low data input.
2-to-4 Binary Decoder
In a 2-to-4 binary decoder, two inputs are decoded into four outputs hence it
consists of two input lines and 4 output lines. Only one output is active at any
time while the other outputs are maintained at logic 0 and the output which is
held active or high is determined the two binary inputs A and B.

The figure below shows the truth table for a 2-to-4 decoder. For a given input, the
outputs Y0 through Y3 are active high if enable input EN is active high (EN = 1).
When both inputs A and B are low (or A= B= 0), the output Y0 will be active or
High and all other outputs will be low.
When A = 0 and B = 1, the output Y1 will be active and when A = 1 and B = 0, then
the output Y2 will be active. When both the inputs are high, then the output Y3
will be high. If the enable bit is zero then all the outputs will be set to zero. This
relationship between the inputs and outputs are illustrated in below truth table
clearly.

From the above truth table we can obtain Boolean expression for the each output
as
These expressions can be implemented by using basic logic gates. Thus, the logic
circuit design of the 2-to-4 line decoder is given below which is implemented by
using NOT and AND gates. Two NOT gates or inverters provide the complement of
inputs.
A common enable line is connected to each AND gate such that when EN= 0 all
the outputs are zero and if EN=1, depends on the inputs A and B, outputs are
produced. Each output represents one of the minterms of the 2 input variables.

It is also possible to design 2-to-4 decoder using NAND gates as shown in figure
below along with truth table. This is constructed with a principle of max terms as
outputs. To generate the minterms, we have to use NAND gates which act as
inverters. If both inputs are zero (A = B = 0), Y0 will be zero , if A = 0 and B= 1, then
Y1 will be 1 and so on.
Therefore, only one output will be low for any combinations of inputs at a given
time and all other outputs will be high. This type of decoders is available in IC
forms so that 3 to 8, 4 to 16, and 5 to 32 decoders can also be made depends on
the application requirement.