In Fulfillment of the Requirements for

ECE 135 CAD TOOL DESIGN

TWO-STAGE OPERATIONAL AMPLIFIER LAYOUT DESIGN

SUBMITTED BY: Benjamin M. Quidlat III

SUBMITTED TO: Prof. Jefferson A. Hora

MAY 31, 2017

SCHEMATIC
ASPECT RATIO
DEVICE (NMOS) Width (m) Length (m) Multiplier
Mn1 2 1 4
Mn2 2 1 4
Mn3 2 1 4
Mn4 2 1 4
Mn5 2 1 8
Mn6 2 1 16
Mn7 2 1 4
Mn8 2 1 4

DEVICE (PMOS) Width (m) Length (m) Multiplier

Mp9 2 1 4
Mp10 2 1 4
Mp11 2 1 4
Mp12 2 1 4
 Mp13 2 1 8

MCR 2 1 40
MCC 4 4 28

TEST BENCH SCHEMATIC

TEST BENCH FOR GAIN, GAIN BANDWIDTH, PHASE MARGIN AND SLEW RATE

FLOOR PLAN
STICK DIAGRAM
LAYOUT DESIGN
PRE-SIMULATION VS POST-SIMULATION RESULTS
 Gain(dB) Phase Margin Gain Bandwidth (MHz)
Pre-Simulation 83.5 55 21.3
Post-Simulation 84.7 52.5 19.4

Gain(dB) Phase Margin Gain Bandwidth (MHz)

TT 84.7 52.5 19.4

SS 85 54.7 15.1

FF 79 51.1 27.1
SLEW RATE

TT 25.8 V/uS

SS 19.6
V/uS

FF 38.5
V/uS

OPAMP WITH PADDING

HAND CALCULATION
For: M7 and M8
ID = 27uA

( ) ( ) ( )2 (0.02)(8.46) ( ) (0.623 0.484)2
= = = 27
2 2

( ) = 16

Setting Iref = 27uA

I4 = 27u
20
I8 = 4(I4) ( )12 = ( )9 =
1
3
() 1 10
9 2
= = ( )2 = ( )1 =
( )11 4(4 ) 8 1

20 140 20
( )12 = ( )9 = ( )11 = ( )12 = ( )9 =
1 1 1
Gain Bandwidth = 21.3MHz

GB = = 21.3MHz
2
Gm2 = (21.3MHz)(2)(5) = 670uA/V =

( ) = 10 = ( )2