Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
The use of computer is the main tool that almost all researchers of the
current generation use. In the paper, the researchers used computer
programs for the simulations such as Agilent's Advanced Design System
(ADS) for the small signal RF simulation which shows the extracted
capacitance values of each test structure and Cadence Spectre for the
Transmission Line Pulse simulation which shows the TLP and leakage plot for
the diode arrays. These programs were used to determine the correlation of a
subject in different scenarios.
c. Techniques of Measurement
d. Statistics
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The simulation used a single diode array configuration. For the simulation of
RF characterization for the diode arrays, the researchers limited the
simulation in a frequency range of 0.4GHz to 10GHz
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
To fully characterize ESD diodes, multiple back to back diode arrays have
been designed and fabricated. The stack number in the arrays range from 4
to 28 diodes. The test structure has a ground-signal-ground (GSG)
configuration for RF on wafer probe measurements. The unit cell of each
diode is identical.
2. Experimentation
For the ESD characterization, HBM and TLP measurements and simulations
are conducted. The leakage current data point is measured after each TLP
pulse to check whether the device is damaged or not. All the diode array test
structures have been characterized a specific frequency range using a 2-
PortVector Network Analyzer (VNA). The reverse bias capacitance of the test
structures is extracted from the S-Parameters across frequency at 0V reverse
bias. Because ESD diodes are nonlinear devices, the harmonics generated by
ESD diodes also need to be well characterized. For the odd harmonics, there
appears to be reasonable agreement between measurement and simulation.
In this case, there are significant discrepancies between measurement and
simulation. The simulation results using diode models that are totally
symmetric shows that no even harmonic are generated while measured
results indicate the presence of strong 2nd and 4th harmonic components in
the output.
3. Evaluation/Testing
From theory, the even harmonic components are present in a system that is
asymmetric about the horizontal V=O axis. A full-wave rectifier is a typical
example. In this work the addition of various asymmetric mechanisms were
explored including nonlinear substrate capacitance coupling and nonlinear
substrate resistance. However, none of them can explain the measured
results completely. The data suggests that there is an intrinsic asymmetry of
the diode structure even though all diode test structures use the same unit
cell in their layout.
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.
Activity 2- #2
Title: Methods of Early Short-Circuit Detection
for Low Voltage Systems
In the paper, the researchers used computer programs for data interpretation
such as the three-dimensional locus curves criterion and regression analysis
and also when doing wavelet analysis.
c. Techniques of Measurement
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The research justified that there were still methods that can be done, and
these possible techniques are the analysis of short-circuit depend voltage
drops in the network or wavelet methods interpreting the network currents
via dyadic filter banks of a Multiresolution Analysis.
The study focused on electronic tripping units that offer new methods in
system protection. Intelligent protection device and communication principles
are needed for realization. Most important is a fast detection and a reliable
behavior at grid bound disturbances to avoid nuisance tripping.
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
In the next steps, the researchers looked for a function, with functional
characteristics differing from the given values at a minimum.
2. Experimentation
Rapid failure detection and no nuisance tripping (reliability) are the key
performance parameters to benchmark early short-circuit detection
algorithms. Three phase faults are generally inherently faster to detect than
single phase faults as evidenced by combined three phase quantities.
Furthermore, a well-defined tripping value is necessary to realize
discrimination for several protection devices installed in series, as it is typical
for low-voltage power distribution networks.
3. Evaluation/Testing
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.
Activity 2 - #3
In the paper, the researchers used computer programs for data interpretation
such as the Smith Chart representation for S-Parameter performance analysis
that introduces a coplanar waveguide.
c. Techniques of Measurement
d. Statistics
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The research justified that the most general ESD protection was the basis of
their design which consists of the source, load, a resistor representing
interconnect and device loss, and the protection device and pad parasitic
capacitance.
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
2. Experimentation
A 50 ohm signal source drives the input to the protection circuit, and the
output of the protection circuit is connected to the system to be protected, as
modeled by a 50 ohms load. In each circuit, the protection device is modeled
as a capacitance and input resistance, and interconnects between the pin and
ESD circuit or between distributed ESD elements are modeled by a resistance
or a coplanar waveguide (CPW). Initially, the capacitance is assumed to be
200 fF, a value sufficient to provide a 2 kV ESD protection level. The required
CPW length was calculated using Smith Charts and impedance
transformations to minimize reflections.
Prior to determining the proper CPW length, three parameters must be fixed.
They are the maximum operating frequency, the equivalent ESD capacitance
and the CPW characteristic impedance. Selecting fmax; should consist only of
determining the maximum frequency specification for the core circuit. ESD
capacitance should be calculated after determining the proper ESD device
size required for a particular protection level. The equivalent capacitance may
then be calculated from the device junction areas, or obtained through
simulations. The CPW characteristic impedance is mainly a function of
transmission line width and signal to-ground spacing. A high characteristic
impedance is desirable, but losses should be kept to a minimum.
3. Evaluation/Testing
Since the whole system is lossless, all the power loss is due to signal
reflection caused by impedance mismatch. While most of the power reaches
the load at low frequencies, the capacitance loads the circuit at higher
frequencies.
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.
Activity 2 - #4
The use of computer is the main tool that almost all researchers of the
current generation use. In the paper, the researchers used computer
programs for the simulations such as SPICE-like (Simulation Program with
Integrated Circuit Emphasis) circuit simulation and electrothermal circuit
simulation which shows the analysis of ESD circuits. These programs were
used to determine the correlation of a subject in different scenarios.
c. Techniques of Measurement
d. Statistics
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The objective of the paper is to review the ESD protection practices and
techniques, ESD protection networks, design concepts, device simulation,
circuit simulation, and other ESD issues.
Highlighted is the unique and interesting role in ESD phenomenon that the
BJT plays in bipolar-, MOSFET-, or BiCMOS-based technologies.
The study focused on understanding the ESD phenomenon and its protection.
The researcher also focused on the physics behind it, the technology used, its
circuitry and design, the simulation made, and scaling.
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
2. Experimentation
ESD standards have been developed for the pulse waveform to represent
different physical interactions with semiconductor chips. Today, ESD models,
including the human-body model (HBM), machine model (MM), charged-
device model (CDM), and socketed-device model (SDM), are being used for
manufacturing qualification of product chips. The HBM source consists of a
1.5-k resistor and 100-pF capacitor in series applied to the device under test.
The MM source is a 200- pF capacitor. In the CDM and SDM test, the package
itself is charged, either in a standing electric field or through the ground or
power-supply leads. TLP and dynamic transmission-line pulse test systems
are being commercially offered as a technique to characterize semiconductor
components. TLP testing varies the pulse width applied to the structure under
test, allowing determination of the power-to-failure versus applied pulse
width. The WunschBell curve of power-to-failure versus pulse width provides
a universal characterization curve for ESD robustness evaluation of the
semiconductor structure. Today, an industry-standard specification does not
exist for TLP testing. As commercial systems become available, and ESD
benchmarking becomes a standard practice, TLP testing may become a tool
to evaluate the ESD robustness of semiconductor technologies and eventually
phase out todays standard testing practices for HBM and MM testing.
3. Evaluation/Testing
Advances in computer-aided design (CAD) are beginning to address ESD
issues in the design implementation and release process. ESD design
checking and verification, as well as development of ESD guidelines have
been established based on physics and unique problems that occur in
providing ESD solutions for semiconductor chips. For ESD protection, ESD
ground rules are established for the ESD networks, layout, and peripheral
circuits.
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.
Activity 2 - #5
The use of computer is the main tool that almost all researchers of the
current generation use. In the paper, the researchers used computer
programs for the simulations such as TCAD (Technology Computer-Aided
Design) circuit simulation which shows the SOI ESD applications. This
program was used to determine the correlation of a subject in different
scenarios.
c. Techniques of Measurement
The researchers interpreted the data using the scientific method, the most
common tool that engineers used when doing systematic researches and
developments.
f. Language
The objective of the paper is to present a new integrated SOI substrate diode
structure for ESD protection of SOI I/O circuits that is built under the buried
oxide of the SOI wafer using a standard CMOS process. It will also aim that
the protection level can reach four times what is achieved by the standard-
lateral SOI diode structure. Also, it aims that the device and process
simulation results to understand the self-heating effect of both standard SOI
and substrate diodes, as well as how to optimize the structure using a deep
N-well implant.
The paper provided a new approach for building ESD protection structures for
SOI technologies that are built underneath the buried oxide layer, using a
standard process flow. The diode is constructed in two ways: one is an
inherent substrate diode that forms an N+/P-substrate junction, and the
other forms a P+/N-well junction by incorporating an extra deep-well implant.
These structures will be compared to the standard SOI Polybond lateral diode
for ESD protection capability via transmission line pulsed (TLP) and intrinsic
device characteristics (leakage and capacitance) measurements.
The study focused on understanding the ESD Protection structure for SOI
Technology based on the integrated SOI substrate diode.
III. Methodology
Enumerate the authors step by step research
methodologies in terms of
1. Data Gathering
In the first few content of the paper, the researcher has indicated
comparisons between SOI ESD and bulk. Th researchers demonstrated the
use of an integrated substrate diode as a new way of protecting against ESD
for SOI technologies to provide 4x improvement in the ESD protection
capabilities, which is an improvement over previous findings that combined
bulk and SOI structures showing a 2x improvement.
2. Experimentation
3. Evaluation/Testing
As a result, it is said that two problems might arise as a result of moving the
ESD protection diode from the SOI layer to the substrate under the buried
oxide. The first one is the increase in capacitance. The second problem
encountered is the increased diode leakage current.
4. Processes to arrive at a conclusion in order to meet the
objectives and eventually solve the problem.
The researchers presented a new ESD protection structure for SOI technology
based on the integrate SOI substrate diode. The SOI substrate diode comes
in either N+/P substrate junction with no extra implant or a P+/N well
junction with extra deep N-well implant. The It2 of the P+/N-well substrate
diode is almost 4 times that of the lateral diode. It is showed that the
substrate diode sensitivity to diode length as well as the problems associated
with the new structure such as increased junction capacitance, which can be
overcome by reducing the diode size without affecting the protection level.
Increased junction leakage was another problem, and by using process and
device simulation the researchers was able to show that it could optimize the
deep N-well for minimum I/O.
Note: Write Not stated in the article if you are sure that the author/s did
not indicate it in their paper.