2010 Second International Conference on Communication Software and Networks

Implemen
ntation off OFDM Baseband
B T
Transmitt
ter Compliiant IEEE
E Std 802.116d on
FPGA

Shahid Abbaas, Waqas Alii Khan, Talhaa Ali Khan Assistannt Professor Saba
S Ahmed
Students Finaal Year Dept. of
o Electronic Enngineering, Departmennt of Electronicc Engineering,
NED Univversity of Engin neering & Techhnology, NED
D University of Engineering & Technology, Karachi,
Karachi, Pakistan
P Pakistan
{shahid..nedian, waqass035}@hotmail.com saabaa@neduet.eedu.pk

Abstract— Broaadband Wireleess Access (BWA

A A) is a promisiing
technology whicch can offer high speed voice, video
v and internnet
c
connection. Thee leading cand didate for BW WA is WiMAX,, a
technology thatt complies witth the IEEE 802.16 family of
s
standards. Thiis paper is fo ocused toward ds the hardwaare
I
Implementation n of WirelessM MAN-OFDM PhysicalP Layer of
I
IEEE Std 802.116d Transmitteer on FPGA. The RTL codiing
s
style of Verilog HDL was used d which gave a high level desiggn-
f
flow for develooping and vallidating comm munication systeem
p
protocols and provides
p flexibillity of modificaations in futuree in
Figuree 1. Speed Vs Mobbility Graph [4]
o
order to meett real world performance evaluation. The T
p
proposed design
n is fully supp portive to adaaptive modulatiion
s
schemes describ
bed in IEEE Std d 802.16d and equipped
e with soft
s describbed in the OF FDM WiMAX X standard witth channel
in
nterfaces for MAC
M layer and RF-front end, so that in futu ure bandwiidth selection of 1.75, 3.5, 7 and 14 MH Hz and CP
m
more work coulld be done in orrder to deploy complete
c WiMA AX time off 16 samples. The
T minimum and maximum m data rates
C
CPE IP core. achieveed with these specs
s were 5.664 Mbps and 50.82 Mbps
respecttively which reequire a maximmum of 6.55 MHz
M clock
Keywords: WiMAX,
W OFDM
M, IEEE Std 8022.16, PHY Layerr. for proocessing. Alteera Cyclone III EP2C35F6722C6 FPGA
chip onn DE2 Developpment kit wass used for the purpose
p of
I. INTR
RODUCTION hardwaare synthesis.
This paper elaborates thee hardware dessign strategies to Thiis document grasps
g an oveerview of OF FDM PHY
m
model OFDM baseband Trransmitter PHY Y of IEEE StdS compliaant IEEE Std 802.16d and itts FPGA impleementation
8
802.16d whicch was app proved by IEEE-Standarrds under section
s II. Secttion III providdes data rate caalculations,
A
Association (IE
EEE-SA) on June 24, 20044 to consolidaate requireed system clockk and hardwaree synthesis resuults.
IEEE Std 8022.16-2001, IEE EE Std 802.116a™-2003, and a
IEEE Std 802.16c™-2002 [1]. The revisedd system aims on II. IEEE 802.16d OF
FDM PHY & FPGA
F IMPLEMEENTATION
d
describing MA AC and multiplle physical layyer specificatioons Thee OFDM Transsmitter PHY off IEEE 802.16d basically
o fixed BWA
of A systems [2]]. The WiMAX Forum was w consists of three processes naamely channeel coding,
c
created in Junee 2001 to provide certificatioon of conformiity, modulaation and OFD DM as shown in Fig. 2. Eacch of these
c
compatibility a
and interoperaability of IE EEE Std 802..16 compriises of certain internal
i processses [4].
p
products. WiMMAX is the nam me given to the products bassed
o IEEE Std 802.16 protoccol. The arrivval of the IEE
on EE A. Chhannel Coding
s
standard 802.16 Wireless Metropolitan Area Netwoork It iss a set of proceesses by whichh one can makee the signal
(WMAN) broought great challenges
c to today’s wirred secure while transmittting through a physical channnel. In the
b
broadband withh great merits, like low cosst for installatiion proposeed design, chhannel coding typically com mprises of
a has made long-range wiireless networkk communicatiion
and three stteps [1] as show wn in Fig. 3.
(up to 40km) a reality. Its hig gh-speed voicee, video and daata
s
services becomme an alternatiive to 3G [3]. A comprom mise
b
between high speed data trransmission annd mobility was w
a
achieved and trrade-off betweeen these two factors
f was muuch
im
mproved, this can be shown by b Fig. 1.
This paper covers the OFDM PHY details and its
a
architectural view to model a real time harddware.The textt is Figure 2.. PHY Processing Sequence [1]
f
fully supportivee to adaptive modulation
m andd coding schem
mes

978-0-7695-3961-4/10 $26.00 © 2010 IEEE 22

DOI 10.1109/ICCSN.2010.83

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 Figure 3. Channel Coding [5]
1) Data Scrambling
It protects against-theoretic uncertainty, avoiding long
sequences of consecutive ones or consecutive zeros. A 15-
bit PRBS generator having polynomial, 1+ x14 + x15 was
implemented to produce scrambled data bits on each burst
of downlink data [1]. The seed value shown in Fig. 4 shall
be used to calculate the scrambled bits. The DIUC value is
simply the Rate ID values as mentioned in table 224 of
section 8.3.3.4.3 of IEEE Std 802.16d.
The FPGA implementation of scrambler is capable of
performing scrambling of 8-bits at a time instead of single
bit. This makes system to work faster 7 times with no extra
hardware as the next state of LFSR register was defined by
the XORed shifting of LSBs to eight MSBs position.
Hardware architecture is given in Fig. 5, showing I/O
interfaces of the module.
2) FEC
It is the process employed to detect and correct errors
without retransmission [6]. For OFDM PHY, the FEC is
accomplished by the concatenation of Reed-Solomon outer
code and a rate compatible Convolution inner code shown in
Fig. 6. As the WiMAX supports adaptive PHY, hence
different modulation and coding schemes could be
employed depending upon channel conditions [7], details of
whose are given in table 1.
a) Reed-Solomon Coding
RS-Encoding is specified by adding parity symbols to
the original data packet. If data packet contains ݇-symbols
each of ݉-bit(s) then encoded version is determined by
RS(݊,݇,‫)ݐ‬, with ݊ is length of coded block and ‫ ݐ‬is the
maximum number of symbols that can be corrected. RS-
Encoding governs following relations [8];
݊ ൌ  ʹ௠ Ȃ ͳ
݇ ൌ  ʹ௠  െ ͳ െ ʹ‫ݐ‬
‫ ݐ‬ൌ  ሺ݊ െ ݇ሻȀʹ
Figure 4. OFDM Scrambler Downlink Initialization Vector [1]
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Figure 5. Architecture of Scrambler
In the proposed design, RS-code shall be derived from a
systematic RS (N = 255, K = 239, T = 8) code using GF (28),
primitive and generator polynomial depicted in (4) and (5)
respectively [1].
‫݌‬ሺ‫ݔ‬ሻ ൌ ‫  ଼ ݔ‬൅  ‫ ݔ‬ସ  ൅  ‫ ݔ‬ଷ ൅ ‫ ݔ‬ଶ  ൅ ͳ (4)
଴ ଵ ଶ்ିଵ
݃ሺ‫ݔ‬ሻ ൌ ൫‫ ݔ‬൅ ҆ ൯൫‫ ݔ‬൅ ҆ ൯Ǥ Ǥ Ǥ ൫‫ ݔ‬൅ ҆ ൯Ǣ ҆ ൌ Ͳʹ‫( ݔ݁ܪ‬5)
In this project the RS-encoder was generated using
Altera Quartus-II 9.0 mega function wizard and was
wrapped in a top-level file in order to introduce variable
coding rates depicted in table 1 and to produce sop, eop,
numcheck and source_ena signals internally which are
needed by Altera’s generated RS-encoder. The I/O data path
is 8-bit wide. The numcheck signal specifies the desired
number of parity symbols. The operation is completed in
minimum 14 and maximum 124 clock cycles. The high-
level hardware design is shown in Fig. 7.
b) Convolutional Encoding
It is described by two parameters; the code rate and the
constraint length. The code rate ݉Ȁ݊, is expressed as a ratio
of the number of input bit(s) ݉ to the output bits ݊ in a
given encoder cycle. The constraint length parameter‫ܭ‬
denotes the length of the convolutional encoder, i.e. how
many ‫ܭ‬-bit stages are available to feed the combinatorial
logic that produces the output symbols [8].
In OFDM PHY, each RS encoded data is further
encoded by convolutional encoder with a native rate of 1/2,
a constraint length equal to 7. The output code bits are
generated by generator polynomial defined in (6) and (7);
(1)
(2)
(3)
Figure 6. OFDM PHY FEC Scheme [5]
‫ܩ‬ଵ  ൌ  ͳ͹ͳ௢௖௧ ‫ܴܱܺܨ‬ (6)
‫ܩ‬ଵ  ൌ  ͳ͵͵௢௖௧ ‫ܻܴܱܨ‬ (7)
23
 TABLE 1. MANDATORY CHANNEL CODING PER MODULATION [1]

Un-coded block size Coded block

Modulation Overall rate RS-Code CC Code rate
(bytes) Size (bytes)
BPSK 12 24 1/2 (12,12,0) 1/2
QPSK 24 48 1/2 (32,24,4) 2/3
QPSK 36 48 3/4 (40,36,2) 5/6
16-QAM 48 96 1/2 (64,48,8) 2/3
16-QAM 72 96 3/4 (80,72,4) 5/6
64-QAM 96 144 2/3 (108,96,6) 3/4
64-QAM 108 144 3/4 (120,108,6) 5/6

TABLE 2. PUNCTURING PATTERNS FOR CC-CODE RATES [1]

CC-Code Rates
Rate 1/2 2/3 3/4 5/6
X 1 10 101 10101
Y 1 11 110 11010
XY X1Y1 X1Y1Y2 X1Y1Y2X3 X1Y1Y2X3Y4X5

subcarrier, i.e., 1, 2, 4 or 6 for BPSK, QPSK, 16-QAM, or

Figure 7. Reed-Solomon Top-Level Module Design
Four coding rates are given in table 1, which are
achieved by puncturing patterns specified in the given table
2 due to which four convolutional encoders of rate 1/2. 2/3,
3/4 and 5/6 were implemented, each having input data path
8, 16, 24 and 40 bits respectively so that data could be
processed in parallel rather than serially to save the system
clock cycles. These four encoders were enclosed in a top-
level file which contains input and output data buffers and
selects only one encoder at a time indicated by rate_id input.
The input data path is 8-bit while output is 48-bit wide. The
whole process takes at least 16 and at most 244 clocks. The
hardware view is shown in Fig. 8.
3) Interleaving
In order to reduce probability of burst errors, interleaving is
done which makes adjacent coded bits non-adjacent. Let
ܰܿ‫ ܿ݌‬be the number of coded bits per
Figure 8. Convolutional-Encoder Top-Level Module Architecture
64-QAM respectively. Let ‫ ݏ‬ൌ ݈ܿ݁݅ሺܰܿ‫ܿ݌‬Ȁʹሻ. Within a
block of ܰ௖௕௣௦ bits at transmission, let ݇ be the index of the
coded bit before the first permutation; ݉௞ be the index of
that coded bit after the first and before the second
permutation and let ‫ܬ‬௞ be the index after the second
permutation. The first and second permutation is defined by
(8) and (9) respectively;
ே೎್೛ೞ ௞
݉௞ ൌ ቀ ቁ Ǥ ݇௠௢ௗଵଶ ൅ ݂݈‫ݎ݋݋‬ሺ ሻ (8)
ଵଶ ଵଶ
௠ೖ ଵଶǤ௠ೖ
‫ܬ‬௞ ൌ ‫ݏ‬Ǥ ݂݈‫ ݎ݋݋‬ቀ ௦
ቁ ൅ ሺ݉௞ ൅ ܰ௖௕௣௦ െ ݂݈‫ݎ݋݋‬ሺ ே ሻሻ௠௢ௗሺ௦ሻ (9)
೎್೛ೞ
Where ܰ௖௕௣௦ = 192, 384, 768 and 1152 called number of
coded bits per OFDM symbol for BPSK, QPSK, 16-QAM
and 64-QAM respectively [1].
The hardware realization of interleaver was designed
using an array of 1152, 1-bit registers. The input data bus is
48-bit which takes minimum of 4 and maximum of 24 clock
cycles in accommodation of bits to pre-calculated positions.
Writing address of array is generated inside the module
which takes decision on the value of rate_id input which
specifies the modulation scheme and then on an internal
counter’s state which denotes how many input packets have
been written to register array. There are 4-output data buses,
each corresponds to provide data to BPSK, QPSK, 16-QAM
and 64-QAM modulation mappers, having widths 1, 2, 4
and 6 bit(s) respectively. As there are 192-data carriers, so
for output 192 clock cycles are needed, hence operation of
interleaver takes minimum of 196 and maximum of 216
cycles. Hardware architectural view is presented in Fig. 9.
All the modules of channel coding are wrapped up under a
top-level file which communicates to the

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 The modulation mappers were simply modeled as For
designing of each modulation mapper, two ROMs were
implemented, one for I part and other for Q. Thus total of 8
ROMs were wrapped up in 4 sets of top-level modules each
corresponds to complete mapper of any scheme, each
having different input data bus widths and number of
locations but same 16-bit wide output path. The rate_id
input selects one of the four output lines corresponding to
requested modulation. The top level design is shown in Fig.
Figure 9. High-Level View of Interleaver 10.
modulation mapper through its four output data buses The I and Q parts each of 192 data subcarriers are fed
described in upcoming sub-section. into OFDM symbol assembler which inserts pilot, DC and
guard carriers to make total of 256 carriers for OFDM
B. Digital Modulation realization.
As the OFDM PHY is adaptive therefore it supports
multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for C. Orthogonal Frequency Division Multiplexing
data carriers’ modulation. The constellation diagrams are OFDM theory states that the IFFT of magnitude N,
gray mapped and shows the magnitudes I and Q (In-phase applied on N symbols, realizes an OFDM signal, where each
and Quadrature) components of each incoming bit(s) symbol is transmitted on one of the N orthogonal
combination along with their normalization factor C to frequencies [10]. The IFFT takes frequency domain
calculate magnitude of each point in the constellation spectrum ܺሺ݇ሻand converts it to time domain signal ‫ݔ‬ሺ݊ሻ
diagram as given in (10); by successively multiplying it by a range of sinusoids as
given by (11);
Mag. Of Carrier = (value of the carrier at that point)*C (10) ‫ݔ‬ሺ݊ሻ ൌ σேିଵ
ଶగ௞௡
ቁ െ ݆ σேିଵ
ଶగ௞௡
௡ୀ଴ ܺሺ݇ሻ •‹ ቀ ே ௡ୀ଴ ܺሺ݇ሻ …‘•ሺ ே
ሻ ሺ11)
Where C = normalization factor, its value is 1,
ͳΤξʹ ǡ ͳΤξͳͲand ͳΤξͶʹ for BPSK, QPSK, 16-QAM and Where ݇ = 0 to ܰ-1 and ܰ ൌ256 [11].
64-QAM respectively [1].
1) OFDM Symbol Assembler
Using (10), the magnitudes I and Q parts of all points in
each modulation schemes were calculated and assigned An OFDM symbol is made up of three types of basic
them Q1.14 Fixed Point Representation [9] so that each sub-carriers [3];
subcarrier is now written as a 16-bit signed number each for x 192 Data subcarriers: Frequency indices; -100 to -1
I and Q part, this simplification is given in table 3. ROMs in and +1 to +100 (except at pilot positions).
which 16-bit hex numbers were saved which are outputted
for respective combinations of input bits corresponds to the x 8 Pilot subcarriers: Frequency indices; -88, -63, -
gray mapped constellation plots. 38, -13, +13, +38, +63 and +88.
TABLE 3. Q1.14 FIXED POINT FORMAT OF I & Q x 56 Null subcarriers: Frequency indices; DC-carrier
MAGNITUDES at 0; Lower guard from -128 to -101; upper guard
from +101 to +127.
MODULATION CARRIER VALUE MAGNITUDE HEX (16-BIT)
1 1 4000 Pilots are generated by PRBS generator using
BPSK
-1 -1 C000 polynomial x11 + x9+1, which produces a sequence ܹ௞ at its
1 0.707106781 2D41 LSB and denotes the OFDM symbol number in the current
QPSK frame[1]. Pilots are BPSK modulated and their I magnitudes
-1 -0.707106781 D2BF
1 0.316227766 143D are given by ͳ െ ʹܹ௞ and ͳ െ ʹܹ ഥ௞ for carrier indices -88, -
-1 -0.316227766 EBC3 38, 63, 88 and -63, -13, 13, 38 respectively.
16-QAM
3 0.948683298 3CB7 
-3 -0.948683298 C349
1 0.15430335 09E0
3 0.46291005 1DA0
5 0.77151675 3160
7 1.08012345 4520
64-QAM
-1 -0.15430335 F620
-3 -0.46291005 E260
-5 -0.77151675 CEA0
-7 -1.08012345 BAE0

Figure 10. Hardware Realization of Mapper

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 DC and guard are null carriers with zero magnitudes. TABLE 4. SYNTHESIS RESULTS
The OFDM symbol is assembled inside a module comprises LC LC Memory DSP Mult-
of pilot generator module and two 256x16 RAMs, each for I Module
Combination Registers Bits ipliers
and Q parts to accommodate on specified locations Channel
correspond to frequency indices[12]. The input data line of coder
3007 2123 1152 0
each RAMs selects either data, pilot, DC or guard carriers. Mapper 7 8 2048 0
2) The IFFT Module OFDM 3864 4386 56577 18
The IFFT module is fed by the OFDM symbol Total 6878 6517 59777 18
assembler with 256-complex samples. The IFFT module
was generated using Altera Quartus-II 9.0 mega function
IV. CONCLUSION
wizard and wrapped in a top-level file in the same way as
for RS-encoder. It takes minimum of 512 clocks to Simulations on ModelSim-Altera were fully compliant
complete the processing. The output data is fed to CP with the IEEE test data. For hardware prototyping of the
generator which introduces the redundancy to the OFDM design, Visual Basic application software was developed
symbol thus act as a protection from inter symbol which provides GUI for data sending and receiving to
interference. FPGA Chip through UART interface. As FPGA platform
3) CP Generator provides a flexible design approach so this work could be
integrated with MAC layer and RF front end for Rx and Tx
A copy of the last ܰூிி் ‫ͳ כ‬ൗ‫ ܩ‬samples is appended to to deploy complete WiMAX CPE.
the beginning of the symbol, called CP which increases
V. REFERENCES
symbol duration hence multipath is achieved [12]. The
value of ‫ ܩ‬is taken as 1/16, thus the term ܰூிி் ‫ͳ כ‬ൗ‫ ܩ‬comes [1] IEEE Standard for Local and Metropoliton Area Networks. Part 16 :
Air Interface for Fixed Broadband Wireless Access Systems. New
out to be 16 and the overall symbol length becomes 272- York, USA : s.n., October 1, 2004.
complex samples. The hardware structure is simply [2] Jordan Douglas Guffey. OFDM Physical Layer Implementation for
achieved by designing two 256x16 RAMs, in which first the Kansas University Agile Radio. University of Kansas. Kansas :
whole 256-complex carriers are written but reading is s.n., 2008. Technical Report.
started from 239 to 255 and then 0 to 255 RAM locations. [3] Wimax-speed. wikimedia.org. [Online] [Cited: September 5, 2009.]
This is all about the hardware implementation of IEEE Std http://commons.wikimedia.org/wiki/File:Wimax-speed.jpg.
802.16d OFDM PHY on FPGA, next section would present
[4] Lili Zhang. A study of IEEE 802.16a OFDM-PHY Baseband.
various results of the project. Electrical Engineering, Linköping Institute of Technology.
Linköping : s.n., 2005. Master thesis in Electronics Systems. LiTH-
III. RESULTS ISY-EX--05/3627--SE.
A. Data Rate Calculation [5] Loutfi Nuaymi. WiMAX: Technology for Broadband Wireless Access.
Data rate = un-coded bits / OFDM symbol Duration (12) ENST Bretagne : John Wiley & Sons Ltd, 2007. p. 310.
[6] Andy Bateman. Digital Communication - Design for the Real World.
ܶ௦ = [ ͳȀሺ݊‫ܹܤ‬ሻȀܰூிி் ](1 + ‫)ܩ‬ (13) s.l. : Addison Wesley Longman Ltd., 1999.
[7] Mohammad Azizul Hasan. Performance Evaluation of WiMAX/IEEE
Where ܶ௦ ൌ OFDM symbol Duration; 802.16 OFDM Physical Layer. Department of Electrical and
݊ = 8/7 called sampling factor; Communications Engineering , Helsinki University of Technology .
‫ = ܹܤ‬Channel Bandwidth; in this design it was taken as 1.75, Espoo : s.n., 2007. Master Thesis.
3.5, 7 and 14 MHz ; [8] Bernard Sklar. Digital Communications Fundamentals and
ܰூிி் = 256 called IFFT points; Applications. 2nd. Los Angeles : Pearson Education, Inc.
‫ = ܩ‬1/16; called ratio of CP time to useful symbol time.
[9] MATLAB 7.8.0 (R2009a), Help. s.l. : MathWorks, Inc., 2009.

Using (12) and (13) for each modulation and coding
scheme depicted in table 1, the minimum and maximum
data rates were found to be 5.64 Mbps and 50.82 Mbps for
which 6.55 MHz clock is required which was easily
achieved by scaling down the oscillator of frequency 50
MHz on Altera DE2 FPGA development kit. Timing
analysis suggests that implemented system could attain a
maximum of 109.26 MHz.
[10] van Nee, R. and Prasad, R. OFDM for Wireless Multimedia
Communications. s.l. : Artech House, 2000.
[11] Charan Langton. OFDM. Intuitive Guide to Principles of
Communications. [Online] http://www.complextoreal.com/.
[12] Amalia Roca Persiva . Implementation of a WiMAX simulator in
Simulink. Institute of Communications & Radio-Frequency
Engineering, Vienna University of Technology. Vienna : s.n., 2007.
Master Thesis.

B. Hardware Resources
Table 4 shows Synthesis results of the design using
Altera Quartus II 9.0 software and device resource
summary for Altera Cyclone II EP2C35F672C6 FPGA chip.

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