16nm Metascan Development Plan

16nm Metascan Development Plan

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Copyright

Revision History
Issue No. Issue Date Details of Change
[0.01] Oct 5th 2016 Initial Version Created

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 16nm Metascan Development Plan

Table of Contents
Copyright ................................................................................................................................. 1
Revision History ...................................................................................................................... 1
1 References .............................................................................................................................. 5
2 Objectives ............................................................................................................................... 6
3 Frontend Design ..................................................................................................................... 7
3.1 RTL ................................................................................................................................ 7
3.2 Synthesis ....................................................................................................................... 7
4 Backend Design ...................................................................................................................... 8
4.1 Create Layout Design ................................................................................................... 8
4.2 Timing Closure .............................................................................................................. 8
5 Produce Deliverables .............................................................................................................. 9
5.1 List of Deliverables ........................................................................................................ 9
6 Schedule and Manpower Estimation .................................................................................... 10
7 Risks ..................................................................................................................................... 11

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List of Figures
No table of figures entries found.

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 16nm Metascan Development Plan

List of Tables
Table 1 Task Schedule ............................................................................................................... 10

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1 References
1. http://bby1dms01/DocMgmt/getfile.cfm?file_id=366727
2. http://bby1dms01/DocMgmt/getfile.cfm?file_id=363801
3. http://intranet.pmc-sierra.internal/wiki/index.php/Metascan

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2 Objectives
This document covers development plan details of the 16nm Metascan block.

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3 Frontend Design
This step is to create RTL and gate level netlists of the Metascan block. The design will be
based on the 28nm Metascan block.

3.1 RTL
The current 28nm Metascan block (LW16_48_10_A) will be used as base rtl for 16nm
metascan.
Test vectors from 28nm Metascan component will be reused with necessary changes to test the
block. Simulation will be executed by using Cadence IES.

3.2 Synthesis
Gate level netlists will be generated using Cadence Genus. Equivalence between netlists and
RTL designs will be tested using Cadence LEC. The SDC file that is used for 28nm block will
be used for 16nm design. The new netlist will be also tested through functional verification
using the vectors of RTL functional verification using Cadence IES.
Gate level functional simulation will be executed using the same test vectors created in section
3.1.
Netlist and SDCs will be delivered to layout .

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4 Backend Design
This step is to create layout of the block and to simulate the layout through static timing
analysis and glitch analysis.

4.1 Create Layout Design

A physical block will be created using Cadence Innovus 16nm Layout flow. Equivalence
between pre-layout and post-layout netlists will be tested using Cadence Conformal.
Parasitic extraction will be performed using Quantus QRC.
At the same time, DRC and LVS will be performed using PVS
Post-layout Netlist, SDFs, SPEFs, CLP netlist will be delivered to IG

4.2 Timing Closure

STA will be performed using Cadence Tempus and LEC between pre-layout and post-layout
netlist.

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5 Produce Deliverables

5.1 List of Deliverables

Following items will be delivered
1. RTL codes
2. Gate level netlists
3. SDC files
4. Block level LEF, SPEF and SDFs
5. STA scripts
6. Physical design files:
- DEF
- GDSII
7. Documents

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6 Schedule and Manpower Estimation

Table 1 Task Schedule

Task Description # of work days Deliverable Date

Frontend Design 25-Oct-16 (11 working days)

- Verify the RTL using HAL and LEC 2
- Modify test vectors (if required) and 5
Perform functional verification using IES
- Create gate level netlist using RTL 3
Compiler
- Verify the gate level netlist using LEC 1
Backend Design 24-Nov-16 (20 working days 4 weeks)
- Layout using Innovus and produce 8
design files (SPEF and post-layout
netlist)
- Verify post-layout netlist using LEC 2
- Run STA using Tempus and fix 4
timing violations
- Run glitch analysis using ETS and 2
fix noise
- Run DRC and LVS checks 4
Produce Deliverables 8-Dec-16 (10 working days 2 weeks)
- Prepare Deliverables 3
- Produce documents 7

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7 Risks
16nm timing signoff corners are not yet finalized. Timing closure effort could be higher
than current estimation as numbers of corners are 3-4x compared to 28nm.
Availability of 16nm templates for power mesh and pre-place

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