Ankit Jain

57, Royal Vaibhav Homes, Adalaj, Gandhinagar, Gujarat, India, Pincode - 382421 9427324873 ankit1312@gmail.com

Objective:
Looking for a position as an ASIC verification engineer in a prestigious organization.
Summary:
Holding H1B Visa valid until November 2016.
Result oriented and dynamic professional with wide exposure in ASIC verification. Sound knowledge of verification tools,
methodology and logic design.
Expertise in writing Verilog/Systemverilog designs from specifications, Static Timing Analysis, Verification using UVM
and Systemverilog Testbenches including Directed and Random testcases generation, Perl scripting.
Solid background in Digital Logic Design, Computer Architecture, FPGA Architecture and PCI Express protocol
Deep understanding in ASIC Design Flow, Formal Verification, Semiconductor Device Physics and Physical Design.
Unique combination of hardware and software skills.
Proven initiator and strategic thinker with effective leadership, presentation, organizational and communication skills.

Education:
Master of Science, Electrical and Electronics Engineering
California State University, Sacramento, CA; Graduation Date - December 2011; GPA 3.6
Bachelor of Science, Electrical and Electronics Engineering
Saurashtra University, India; Graduation Date - June 2008; GPA 3.8

Technical Skills:
Languages: Verilog, Systemverilog, VHDL, C, C++, Assembly
Verification Methodology: UVM
Scripting: Perl, TCL
Protocols: SATA, PCI Express, PCI, I2C, MESI
OS/Platforms: UNIX, Windows
Tools/Simulators: Jaspergold Formal Property Verification and other Apps, Synopsys VCS, NC-Verilog, Modelsim, Primetime,
Synopsys Design Vision, PSPICE, Xilinx ISE, MATLAB, Quartus II, L-Edit

Work Experience:
Perfect VIPs Technologies Pvt. Ltd., India October 2014 until present,
PHY IP and VIP integration (SATA protocol):
Downloaded E12 PHY with Synopsys coreConsultant tool, removed E12 PHY from VMT VIP, found corresponding tasks
and signals and attached the E12 PHY with the Host of SVC VIP.
Debugged the errors through DVE tools and log files after connecting E12 PHY with the Host.
Mapped the signals of E12 PHY with the SVC Host VIP and made necessary connections.
Learnt SATA Protocol and got clear understanding of different layers of SATA.
SATA Testplan development for Random Scenario
Wrote the testplan for random scenarios of SATA.
Contributed in writing testcases in UVM, running simulations, debugging log files and waveforms.
Quality Engineer, Jasper Design Automation, USA March 2013 to May 2014
Performing formal verification and equivalence checking on the designs.
Performing QA activities including testing of new features and bug-fixes as it relates to fixes and enhancements for the customer.
Providing post-sales support, including working closely with Field Application Engineers and R&D as needed. Also working with
cross functional teams of different countries.
Automating the testing process through scripting in different languages, in special TCL, perl and bash script.
Developing regression testcases, testplans and reporting them into JIRA, writing test scripts and inserting them in hg mercury.
Helping in documentation for DDR4 proof kit and different apps related to Jaspergold Formal Verification software.

Internships: 2008 to 2013

Physical Design Intern, Silverline Design Inc., USA
Performed Cell characterization on Muller-C element using NGspice tool for 28nm technology.
Simulated the cells for different voltage levels, wrote and simulated .sp files and .cmd files, performed tradeoff for area vs. speed
using logical effort, fan out 4 and gate sizing.
Drew layouts using L-Edit and generated GDS file.
Graduate Technical Intern, Jasper Display Corporation, USA
Designed and placed binary clock tree through TCL scripts using SOC Encounter tool and generated a symmetrical clock tree
with skew less than 6ps on 65nm technology.
Performing duties of writing scripts in perl and testbenches in Verilog HDL, writing .spice file.
 Learned about challenges in physical design such as clock synchronization, clock skew, Interconnect delay etc.
Lecturer, Government Polytechnic, India (Contract Job), India
Designed and conducted lessons in major subject areas: Digital Electronics and Engineering Mathematics.
Attended professional growth seminars and workshops.
Hardware Design Intern, MCBS Pvt. Ltd., India
Designed and implemented a prototype automatic identity authentication system which is called Advanced Access System
which uses magnetic card reader to authenticate the identity of an individual.

Projects:
Design and Verification of the Arbiter and DMA: (Jasper Design Automation, March 2013 to May 2014)
This project was the verification of state-of-the-art ASICs. Designed and Verified a DMA system with 4 DMA clients, one
Arbiter and a Memory module in Systemverilog.
Advanced features of Systemverilog e.g. objects, classes and OOPs concepts, program blocks, clocking blocks,
constraint based randomization, Systemverilog Assertions were used to test the design thoroughly for different size of
read/write transactions.
Verification concepts of Interfaces were used to communicate between different modules.
Used Synopsys VCS tool for the design and verification of the DUT.
Pipelined Vector Multiplier and Verification (Jasper Design Automation, March 2013 to May 2014)
Performed multiplication between two 64-element vectors, element by element, and stored the product in another vector
using 32-bit single precision floating point numbers expressed in IEEE 754 format using Verilog HDL.
Performed pipelining to fetch, multiply, rounding, normalization and store the data. Verified the design using
Systemverilog and Synopsys VCS.
Performed static timing analysis to check setup and hold violations, provided timing constraints and LSI10k library to
synthesize the code to gate level netlist using Synopsys Design Compiler.
32-bit ALU and Verification (Jasper Design Automation, March 2013 to May 2014)
Designed a 32-bit ALU which can perform signed logical and arithmetic manipulations; implemented overflow, negative and
zero flags in Verilog HDL and performed Verification using Synopsys VCS.
PCI Card and Cache Logic (Jasper Design Automation, March 2013 to May 2014)
Designed two 32 bit PCI compliant devices to perform memory read and write transaction between them. The read transaction
should be retried first and performed after write operation to read the correct data.
Designed in Verilog HDL with the given Arbitration Logic and then performed data transactions with cache memory
management.
PCI Express Card Model (Jasper Design Automation, March 2013 to May 2014)
Designed transaction layer and data link layer for transmitter and receiver of PCI Express card to perform non-posted memory
write transaction between two devices using Verilog HDL.
Implemented the concept of ACK/NAK protocol to confirm the reception of the packets and resend the packets if required.
Advanced Timing Analysis (Jasper Display Corporation, May 2012 to December 2012)
Wrote a TCL script to set constraints such as operating condition area, delay time, rise time and fall time for the several
combinational and sequential designs and synthesized them using characterization technique and technology library
lsi10K.
Verified Timing reports, delays, clock skew, clock latency, clock gating of designs using Synopsis Prime Time tool
Analyzed timing constraints like setup time, hold time, data arrival time, require time for several paths and learned
different RTL optimization techniques.
Digital Standard Cell Library (Jasper Display Corporation, May 2012 to December 2012)
Designed and laid out Digital Standard Cell Library in 90nm CMOS using Microwind layout and simulation tool. Developed
back-end-designs and area optimized layouts for mask creation and simulated using cmos90n.rul technology.
Drew and simulated schematics in PSPICE and used hand calculation to find performance parameters for each library cells.
Calculated rise-time, fall-time and delay-time for different values of capacitance and different cases of MOS switching
For the D-flip-flop, found the clock-to-Q and clock-to-Qbar delays as well as the delays from the set/reset inputs to Q and Qbar.
Also determined the maximum frequency at which each D-flip-flop can toggle with a 40fF load.
Balanced Clock Tree Placement (Jasper Display Corporation, May 2012 to December 2012)
Wrote a TCL script and generated DEF file to place clock buffers at different level such that they pass the clock signal to each IO
pad at the same instant.
The clock tree had symmetrical and binary like structure.
Advanced Access System (MCBS Pvt. Ltd., January 2008 to May 2008)
Designed and implemented a prototype automatic identity authentication system which is called Advanced Access System that
uses magnetic card reader to authenticate the identity of an individual
Implemented I2C Protocol to read and write multiple bytes to EEPROM
Used sensor module to make attendance and implemented hardware having P89V51RD2, Microcontroller, LCD, EEPROM, IC
MAX 232, RS 232, Keyboard, RTC
Used Topview Simulator for Assembly Language Programming; Keil Software for C programming; Protel DXP for schematics;
Flash Magic Software, Hyper Terminal, Docklight Tool for testing
Related Course Work:
DIGITAL INTEGRATED CIRCUIT DESIGN
COMPUTER ARCHITECTURE
SYSTEMVERILOG FOR DESIGN AND VERIFICATION
HIERARCHICAL DIGITAL DESIGN METHODOLOGY
PCI EXPRESS SYSTEM ARCHITECTURE
MICRO-PROCESSORS & INTERFACING
ADVANCED TOPICS IN LOGIC DESIGN
PCI SYSTEM ARCHITECTURE
STATIC TIMING ANALYSIS
SEMICONDUCTOR DEVICE PHYSICS
NUMERICAL ANALYSIS
MICRO-CONTROLLERS & APPLICATIONS