Introduction aux FPGA

Introduction aux FPGA

Mickal Dardaillon

M2RTS

16/11/2011
Introduction aux FPGA
Introduction

Hirarchie
Circuits Logiques

Processeurs Circuits programmables ASIC

CPU micro-contrleurs DSP CPLD FPGA

Dfinitions
I CPU : Computer Processing Unit
I DSP : Digital Signal Processor
I CPLD : Complex Programmable Logic Device
I FPGA : Field Programmable Gate Array
I ASIC : Application Specific Integrated Circuit
Introduction aux FPGA
Introduction
ASIC
I Dveloppement long
I Cot de fabrication (en
augmentation)
I Full custom : Performances
maximales
I Fabrication grande srie
FPGA
I Dveloppement rapide
I Cot lunit (en
diminution)
I Contraint par la technologie
du FPGA
I Prototypage rapide
Introduction aux FPGA
Introduction

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Rappels sur les circuits intgrs

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Rappels sur les circuits intgrs

Le transistor MOS

MOS : Metal Oxide Semiconductor

I Composant lectronique de base
I Porte logique ON/OFF

Oxyde Drain

Grille Canal
Semiconducteur

Mtal Source
Introduction aux FPGA
Rappels sur les circuits intgrs

Technologie CMOS

CMOS : Complementary MOS Types de MOS

source source
I Niveaux logiques grille
grille g=1 g=0
I 0 = 0V
I 1 = 3V drain drain

I Deux types de MOS nMOS pMOS

I nMOS : conducteur si la grille=1
I pMOS : conducteur si la grille=0 Exemples
1
I Puissance dissipe 1 x y
I P CV 2 f x
(xy)
x x
I C : Capacit dun MOS y
I V : Tension sur la grille 0 0
I f : Frquence de fonctionnement Inverseur porte NAND
Introduction aux FPGA
Rappels sur les circuits intgrs

Portes lmentaires

Amplificateur : Inverseur :
x F x F x F x F
0 0 0 1
F =x 1 1 F =x 1 0

ET : NON ET :
x y F x y F
x
F 0 0 0 x F 0 0 1
y 0 1 0 y 0 1 1
F =x y 1 0 0 F =x y 1 0 1
1 1 1 1 1 0
Introduction aux FPGA
Rappels sur les circuits intgrs

Conception de circuit combinatoire

1. Description du problme : 3. quations logiques :
Addition entre deux bits S = abc + abc + abc + abc
a et b et une retenue c cout = abc + abc + abc + abc
2. Table de vrit : 4. quations simplifies :
entres sorties S = (a b) c
a b c S cout cout = ab + (a b)c
0 0 0 0 0
5. Portes logiques :
0 0 1 1 0
0 1 0 1 0 A
B
0 1 1 0 1 S
C
1 0 0 1 0
1 0 1 0 1 Cout
1 1 0 0 1
1 1 1 1 1
Introduction aux FPGA
Rappels sur les circuits intgrs

Logique squentielle
Bascule RS
R
Q S R Q Q
0 1 0 1
1 1 interdit interdit
Q
1 0 1 0
S 0 0 Qn1 Qn1
Bascule RS

Bascule D : mmorise D lorsque lhorloge passe 1

Horloge
11
00
11
00 Valeur
00
11

11
00
00
11 Valeur
Donne
1
0
Introduction aux FPGA
Structure matrielle

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Structure matrielle
Structure gnrale

Ressources globales

bloc de configuration

mmoire RAM (sur certains circuits)

entre/sortie programmable

logique programmable

routage programmable

gnrateur dhorloge programmable

+ mmoire de configuration
Introduction aux FPGA
Structure matrielle
Structure gnrale

Routage des signaux

connection longue distance

connection directe
canaux gnraux
bloc logique
matrice de routage
point de routage
Introduction aux FPGA
Structure matrielle
Structure gnrale

Gnration dhorloge

Les horloges sont distribues dans lensemble du FPGA par des

circuits de routage spcifique, aucun travail de la part du
concepteur !

plots dhorloge
CLK CLK0
CLK90
CLKFB CLK180
CLK270
DCM
CLKx2
CLK180x2
signal CLKDIV
interne
CTRL
STATUS

BUF
DCM
vers distribution par zone
Introduction aux FPGA
Structure matrielle
Structure gnrale

Entres / Sorties
Il existe plusieurs niveaux de tensions dentre / sortie, qui sont
prendre en compte pour :
I La conception de la carte (compatibilit entre composants)
I Les contraintes de routage (technologie utiliser sur I/O)

V in V out
porte

5V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V 5.0 V

1
4.5 V 1
1
4V 1 3.9 V
1 3.5 V 1 3.3 V 3.3 V
3V 1
2.7 V 1
x 2.4 V
2V 2.0 V 2.0 V 2.0 V

x x x
1V 1.0 V
0.8 V 0.8 V 0.8 V
0 0.4 V 0 0.5 V 0 0.4 V 0 0.4 V
0 0 0 0
0V 0.0 V 0.0 V 0.0 V 0.0 V 0.0 V 0.0 V 0.0 V 0.0 V

TTL CMOS TTL/CMOS CMOS 3V

Introduction aux FPGA
Structure matrielle
Cellules lmentaires

Composants logiques
Chaque constructeur dfinit sa propre cellule de base, qui varie
selon les familles de FPGA.
Les cellules lmentaires :
I Portes logiques configurables : fonctions de base (AND, OR...)
I Registres : mmoire et synchronisme

Les composants matriels (hardcore) :

I Logique complexe : additionneurs, multiplieurs...
I Mmoire RAM
I Processeurs (ARM, PowerPC...)

Les composants logiciels (softcore) :

I UART, USB, contrleur dcran...
I Processeurs (ARM, RISC...)
I FFT, JPEG, SHA-1...
I ...
Introduction aux FPGA
Structure matrielle
Cellules lmentaires

Xilinx Virtex 4 : Slice

0*1/1

? B
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Introduction aux FPGA In addition to the adaptive LUT-based resources, each ALM contains four
Structure matrielle programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can efficiently
Cellules lmentaires implement various arithmetic functions and shift registers. Each ALM drives all types
of interconnects: local, row, column, carry chain, shared arithmetic chain, register
chain, and direct link. Figure 15 shows a high-level block diagram of the Stratix V
ALM.
Altera Stratix 5 : ALM (Adaptative Logic Module)
Figure 15. High-Level Block Diagram of the Stratix V ALM
shared_arith_in carry_in reg_chain_in

Combinational/Memory ALUT0 labclk

To general or
local routing
dataf0
D Q
6-Input LUT adder0 To general or
datae0 local routing
reg0
dataa

datab

To general or
local routing
D Q
To general or
reg1 local routing

To general or
local routing
datac D Q
datad adder1 To general or
reg2 local routing
datae1 6-Input LUT

dataf1

D Q
Combinational/Memory ALUT1 To general or
reg3 local routing

To general or
shared_arith_out carry_out local routing

reg_chain_out
Introduction aux FPGA
Structure matrielle
Cellules lmentaires

Actel Pro Asic 3 : VersaTile

ProASIC3 Flash Family FPGAs

Refer to Figure 1-3 for VersaTile configurations.

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

X1 Data Y Data Y
X2 LUT-3 Y CLK D-FF CLK D-FF
X3 CLR
Enable

CLR

Figure 1-3 VersaTile Configurations

User Nonvolatile FlashROM

ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can
be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Introduction aux FPGA
Structure matrielle
Composants matriels

Composants logiques
Chaque constructeur dfinit sa propre cellule de base, qui varie
selon les familles de FPGA.
Les cellules lmentaires :
I Portes logiques configurables : fonctions de base (AND, OR...)
I Registres : mmoire et synchronisme

Les composants matriels (hardcore) :

I Logique complexe : additionneurs, multiplieurs...
I Mmoire RAM
I Processeurs (ARM, PowerPC...)

Les composants logiciels (softcore) :

I UART, USB, contrleur dcran...
I Processeurs (ARM, RISC...)
I FFT, JPEG, SHA-1...
I ...
 FPGAs are efficient for digital signal processing (DSP) applications because they can
Introduction aux FPGA
implement custom, fully parallel algorithms. DSP applications use many binary
Structure matrielle
multipliers and accumulators that are best implemented in dedicated DSP slices. All
Composants matriels
7 series FPGAs have many dedicated, full-custom, low-power DSP slices, combining high
speed with small size while retaining system design flexibility. The DSP slices enhance the
speed and efficiency of many applications beyond digital signal processing, such as wide
DSP Slice pour Virtex 4
dynamic bus shifters, memory address generators, wide bus multiplexers, and
memory-mapped I/O registers. The basic functionality of the DSP48E1 slice is shown in
Entres
Figure 1-1.18
For bits avecdetails,
complete multiplication
refer to Figure/2-1
accumulation sur 32 Description
and Chapter 2, DSP48E1
and Specifics.
chantillons
X-Ref Target - Figure 1-1

48-Bit Accumulator/Logic Unit

B

+
A X P

+/ 25 x 18
Multiplier
D
Pre-adder =

Pattern Detector
C

UG479_c1_21_032111

Figure 1-1: Basic DSP48E1 Slice Functionality

Introduction auxData
FPGA can be written to either or both ports and can be read from either or both ports. Each
write operation is synchronous, each port has its own address, data in, data out, clock,
Structure matrielle
clock enable, and write enable. The read and write operations are synchronous and require
Composants a clock edge.
matriels
There is no dedicated monitor to arbitrate the effect of identical addresses on both ports. It
is up to the user to time the two clocks appropriately. Conflicting simultaneous writes to
RAM double port the same location never cause any physical damage but can result in data uncertainty.
X-Ref Target - Figure 1-1

CASCADEOUTA CASCADEOUTB

36-Kbit Block RAM

32
DIA
4
DIPA
16 Port A
ADDRA
4
WEA
ENA
RSTREGA
32
RSTRAMA DOA
CLKA DOPA 4
REGCEA
36 Kb
Memory
Array
32 32
DIB DOB
4 4
DIPB DOPB
16
ADDRB
4
WEB
ENB Port B
RSTREGB
RSTRAMB
CLKB
REGCEB

CASCADEINA CASCADEINB
Introduction aux FPGA
Structure matrielle
Composants matriels

ADC
Chapter 1: Introduction and Quick Start

X -R e f Target - F igure 1-1

Te m pe rature S upply VREFP VREFN

S e nsor S e nsors
V C C IN T
D ie
Tem pe rature C V C C AU X O n-C hip R e f
V C C BR AM 1 .25 V

VP 1 2 -bit, C ontrol S tatus

VN M ux 1 MSPS R e giste rs R egiste rs
VAU X P [0] AD C A
VAU X N [0]
3 2 x 1 6 bits 3 2 x 1 6 bits
R ea d/W rite R ea d O nly
E xte rnal VAU X P [12]
VAU X N [12] M ux
Analog Inputs
VAU X P [13] 1 2 -bit,
VAU X N [13] 1 MSPS
VAU X P [14] AD C B
VAU X N [14]
VAU X P [15]
VAU X N [15]
DRP
FPGA
JTAG
Inte rconnect
U G 4 80_ c1_ 01_090710

Figure 1-1: XADC Block Diagram

The XADC also includes a number of on-chip sensors that support measurement of the
Introduction aux FPGA
Structure matrielle
Composants matriels

Processeur ARM sur SmartFusion

Introduction aux FPGA
Structure matrielle
Composants logiciels

Composants logiques
Chaque constructeur dfinit sa propre cellule de base, qui varie
selon les familles de FPGA.
Les cellules lmentaires :
I Portes logiques configurables : fonctions de base (AND, OR...)
I Registres : mmoire et synchronisme

Les composants matriels (hardcore) :

I Logique complexe : additionneurs, multiplieurs...
I Mmoire RAM
I Processeurs (ARM, PowerPC...)

Les composants logiciels (softcore) :

I UART, USB, contrleur dcran...
I Processeurs (ARM, RISC...)
I FFT, JPEG, SHA-1...
I ...
 MicroBlaze Architecture
Introduction aux FPGA
Structure matrielle
Composants logiciels

This chapter contains an overview of MicroBlaze features and detailed information on

Xilinx MicroBlazeMicroBlaze
(propritaire)
architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit general
purpose registers, virtual-memory management, cache software support, and Fast Simplex Link
(FSL) or AXI4-Stream interfaces.

I 5.1K LUTs at 241MHz on Xilinx Virtex 6

Overview
I 2.4K LUTs atThe131MHz on processor
MicroBlaze embedded Xilinx Spartan
soft core 6 set computer (RISC)
is a reduced instruction

optimized for implementation in Xilinx Field Programmable Gate Arrays (FPGAs). Figure 2-1
shows a functional block diagram of the MicroBlaze core.

Instruction-side Data-side
bus interface bus interface
Memory Management Unit (MMU)

ITLB UTLB DTLB

M_AXI_IC M_AXI_DC

D-Cache
I-Cache

IXCL_M DXCL_M
Program ALU
IXCL_S Counter DXCL_S
Special Shift
Purpose
Registers Barrel Shift M_AXI_DP
Branch Multiplier
M_AXI_IP Target DPLB
Cache Divider
DLMB
IPLB FPU
Bus Bus
IF IF M0_AXIS..
Instruction
ILMB M15_AXIS
Buffer
Instruction S0_AXIS..
Decode S15_AXIS
Register File MFSL 0..15 or
32 X 32b DWFSL 0..15
SFSL 0..15 or
Optional MicroBlaze feature DRFSL 0..15

Figure 2-1: MicroBlaze Core Block Diagram

Introduction aux FPGA
Structure matrielle
Composants logiciels

Processeur OpenRISC (open-source)

I 7K core cells, 4 block RAMs at 35MHz on Actel ProASIC3
I 2.4K LUTs, 1 block RAM at 125MHz on Xilinx Virtex 5
Introduction aux FPGA
Les constructeurs

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Les constructeurs

Les constructeurs

Part de march en termes de CA en 2010

!"#"$%&'()(*

Technologie
SRAM
I Xilinx
<="3>27?"3&0)@* I Altera
6"3.78-9"&:+3,-#;&')1*
I Lattice
2/,,"3-&4)5* Flash
I Actel
I QuickLogic

+#,-./&'0)1*
Introduction aux FPGA
Les constructeurs

Familles

Xilinx Altera Actel

Hautes performances Virtex Stratix
Rentable Kintex (ex Spartan) Arria Pro Asic 3
conomie dnergie Artix Cyclone Igloo
Introduction aux FPGA
Les constructeurs

Xilinx Virtex 7
I 28nm Process
I 6,8 Milliards de transistors
(intel core i7 : 995 Millions)
Introduction aux FPGA
Les constructeurs
SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion cSoC Block Diagram

Actel SmartFusion
Supervisor Cortex-M3 PPB
SysReg

PLL OSC RC
+ JTAG NVIC SysTick

ENVM Microcontroller Subsystem

WDT 32 KHz RTC
3V SWD MPU Programmable Analog
ESRAM FPGA Fabric

S D I
SPI 1 APB APB SPI 2

AHB Bus Matrix

UART 1 EFROM Timer1 UART 2

10/100
I2C 1 IAP PDMA APB EMC
EMAC Timer2 I2C 2

SCB
Analog Compute
Temp. Volt Mon.
Mon. (ABPS) Engine

Curr. DAC
Comparator ADC (SDD)
Mon.
Sample Sequencing
Engine VersaTiles
............

............

........
....

SCB
Temp. Volt Mon. DAC
Mon. (ABPS) ADC (SDD)
Post Processing
Engine

Curr.
Mon.
Comparator SRAM SRAM SRAM ........ SRAM SRAM SRAM
Introduction aux FPGA
Programmation

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Programmation
Flot de conception

Design process (1)

Flot de conception (1)

Design and implement a simple unit permitting to

Specification (Lab Experiments)

speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds..

VHDL description (Your Source Files)

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RC5_core is
Functional simulation
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;

Synthesis
Post-synthesis simulation
Introduction aux FPGA
Programmation

Design process (2)

Flot de conception

Flot de conception (2)

Implementation
Timing simulation

Configuration
On chip testing
Introduction aux FPGA
Programmation
Flot de conception

Environnement de dveloppement

Synthse
I Actel Libero
I Altera Quartus II
I Synopsys Synplify
I Xilinx ISE
I ...

Simulation
I ModelSim
I ...
Introduction aux FPGA
Programmation
Synthse

Translation
Traduction

Synthesis

Circuit netlist Timing Constraints

Constraint Editor
Electronic Design Native
Interchange Format Constraint
File
EDIF NCF UCF User Constraint File

Translation

NGD Native Generic Database file

Introduction aux FPGA
Programmation
Synthse

Pin assignment file (UCF)

NET "clock" LOC = "P8" ;

NET "control<0>" LOC = "K4" ;
NET "control<1>" LOC = "K3" ;
NET "control<2>" LOC = "K2" ;
NET "reset" LOC = "E11" ;
NET "segments<0>" LOC = "R10" ;
NET "segments<1>" LOC = "P10" ;
NET "segments<2>" LOC = "M11" ;
NET "segments<3>" LOC = "M6" ;
NET "segments<4>" LOC = "N6" ;
NET "segments<5>" LOC = "T7" ;
NET "segments<6>" LOC = "R7" ;
Introduction aux FPGA
Programmation
Synthse
Assigning I/O Locations Using PlanAhead Software

Pin assignment graphique

3. Click Close on the Welcome dialog to proceed in the PlanAhead software.
X-Ref Target - Figure 6-12

Figure 6-12: PlanAhead Software for I/O Planning

Introduction aux FPGA
Programmation
Synthse

Logic
Synthse Synthesis
Netlist

VHDL description Circuit netlist

architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;

MUX_0<=A1 and B1;

MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;

with (L1 & L0) select

Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;

end MLU_DATAFLOW;

ECE 449 Computer Design Lab 46

Introduction aux FPGA
Programmation
Placement / Routage

Mapping
Mapping

LUT0
LUT4

LUT1
FF1
LUT5

LUT2

FF2
LUT3

ECE 449 Computer Design Lab 55

Introduction aux FPGA
Programmation
Placement / Routage

Placement/Routage
FPGA

Programmable Connections
Introduction aux FPGA
Programmation
Tests

Analyse des temps de propagation

Static Timing Analysis
I Recherche du chemin critique (chemin le plus long)
I ! Critical
Dtermine Path The
la frquence Longest
maximale Path From
de fonctionnement
I Outputs
Simulation of Registers
post-routage to ces
bas sur Inputs of
donnes
Registers
tP logic

in out
D Q D Q

clk

tCritical = tP FF + tP logic + tS FF

ECE 449 Computer Design Lab 59

 Introduction aux FPGA
Chapter 5: Behavioral Simulation
Programmation
Tests

5. Drag all the selected signals to the waveform.

Simulation : ModelSim
X-Ref Target - Figure 5-13
Note: Alternatively, right-click on a selected signal and select Add to Wave Window.

Figure 5-13: Adding Signals to the Simulation Waveform

Automatisation des tests
Notice that the waveforms have not been drawn for the newly added signals. This is
because ISim did not record the data for these signals. By default, ISim records data only
Gnration Vecteurs Testbench Rsultats Analyse
for the signals that are added to the waveform window while the simulation is running.
C Therefore, whentxt
new signals are added to the waveform
VHDL txt
window,
C you must rerun the
simulation for the desired amount of time.

Rerunning Simulation
Introduction aux FPGA
Programmation
Tests Figure 8-8: Operation Status

When the Program operation completes, a large blue message appears showing that
programming was successful, as shown in the following figure. This message
Programmation disappears after a few seconds.
X-Ref Target - Figure 8-9
Introduction aux FPGA
Recherche sur les FPGA Lyon

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
Recherche sur les FPGA Lyon
Sources
Introduction aux FPGA
Recherche sur les FPGA Lyon

Arithmtique sur FPGA

Projet Arenaire
I quipe INRIA / Laboratoire LIP / ENS
I Dveloppement de larithmtique sur ordinateur
I FloPoCo (Floating Point Cores)
I Gnration doprateurs de calculs pour
FPGA
I Oprateurs classiques (+,,,/ et x)
I Oprateurs exotiques (multiplication par une constante...)
I Virgule fixe, flottant, formats exotiques...

Cryptographie
I Laboratoire CITI / INSA
I Dveloppement/exprimentations de nouvelles architectures
pour la cryptographie
 Introduction aux FPGA
Recherche sur les FPGA Lyon

Radio Logicielle
a complete array
for any Plateforme
type of matrielle
I quipe
ring for each Airelle / Laboratoire CITI / INSA
I Dveloppement de composants radio en logiciel
h the host device
I Plateforme dexprimentation
I
gration from Lyrtech Small Form Factor

- Digital processing module

Data conversion module Virtex-4
RF module FPGA

LYRIO
to RX ADC

RX ADC
Virtex-4
LYRIO
TX
FPGA DM6446
Antenna Transceiver IF TX DM SoC
Clk Ref

F GPIO
Introduction aux FPGA
Recherche sur les FPGA Lyon

Exemple : Cryptographie sur FPGA (GPS)

Les rseaux de capteurs sans fil PowWow

I Actel Igloo AGL250

I TI MSP430
I TI CC2420
 Introduction aux FPGA
Recherche sur les FPGA Lyon

Architecture
20 classique Introduction

Sensor Computation Communication

Subsystem Subsystem Subsystem

Sensor MCU Tx

Power Supply Rx

Power Subsystem

Figure 1.1: General architecture of a WSN node.

Architecture PowWow
versality. However, when looking more carefully to actual design practices, we observe
, version 1 - 6 Ja n 2011

that the need for flexibility/programmability is essentially geared toward the user ap-
plication layer, which happens to represent only a small fraction of a WSN nodes
processing workload. Whereas most of the processing workload is almost dedicated
to the communication protocol stack. Hence, in our opinion, it is worth-studying to
explore the hardware specialization approach in WSN node design as well to meet the
ultra low-power requirement. In order to reduce the power consumption in a WSN
node, we first need to look at the generic node architecture to find out the hotspots for
power consumption. The generic architecture of a WSN node is discussed in the next
section.
 nk 0
Ba
Introduction aux FPGA ISP AES User Nonvolatile Flash*Freeze Charge
Decryption* FlashRom Technology Pumps
Recherche sur les FPGA Lyon
Bank 1
* Not supported by AGL015 and AGL030 devices
Figure 1-1 IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and
Actel Igloo AGL250 AGL125)

Bank 0
CCC

RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
Bank 3

Bank 1
I/Os

VersaTile
Bank 3

Bank 1
RAM Block
ISP AES User Nonvolatile Flash*Freeze Charge
4,608-Bit Dual-Port
Decryption* FlashRom Technology Pumps SRAM or FIFO Block
(AGL600 and AGL1000)
Bank 2

Figure 1-2 IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and
I 250 000 portes logiques ' 6144 VersaTiles
AGL1000)

I Horloge cadence 8 MHz

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Implmentation de GPS
Raliser une multiplication :
I Une cl connue de 128/256/512 bits
I une valeur de 32 bits
De manire efficace ?
Multiplication srie : mthode shift and add

1 0 0 1 0 1 0
1 1 0 1
1 1 0 0 1 0 1 0
1 + 1 0 0 1 0 1 0
0 + 0 0 0 0 0 0 0
1 + 1 0 0 1 0 1 0
1 1 1 1 0 0 0 0 1 0

Multiplication par une constante : mthode KCM

Introduction aux FPGA
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Multiplication srie : McLoone and Robshaw, 2007

Stores intermediate
multiplication values

11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0 Performs left
11 10 9 8 7 6 ... 0 shift by 1-bit
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0
11 10 9 8 7 6 ... 0

16

0 15

s
r
16
+ 1

Control
c Logic

I Architecture de rfrence en cryptographie embarque

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Multiplication par une constante : Architecture KCM

A0 -A3
16 4 bits rom
A4 -A7
4 bits adder

A8 -A11

1 4 4 4 4 4

I Architecture gnre par FloPoCo

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Rsultats

secret size 128 bits 256 bits 512 bits

parallel impl. 10476 20755 44307
Actel Igloo
serial impl. 1546 2253 3698
VersaTiles
parallel/serial ratio 6.8 9.2 12
parallel impl. 8 12 20
Run cycles serial impl. 339 603 1131
serial/parallel ratio 42.4 50.3 56.55

I AGL250 ($20) : 6144 VersaTiles

I AGL1000 ($100) : 24576 VersaTiles
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Rsultats

secret size 128 bits 256 bits 512 bits

parallel impl. 2213 4358 7115
Xilinx Virtex4
serial impl. 493 784 1377
Slices
parallel/serial ratio 4.5 5.5 5.2
parallel impl. 8 12 20
Run cycles serial impl. 339 603 1131
serial/parallel ratio 42.4 50.3 56.55

I XC4VSX35 ($600) : 15360 Slices

I source prix : Digi-Key, 11/2011
Introduction aux FPGA
Sources

Sommaire
Introduction
Rappels sur les circuits intgrs
Structure matrielle
Structure gnrale
Cellules lmentaires
Composants matriels
Composants logiciels
Les constructeurs
Programmation
Flot de conception
Synthse
Placement / Routage
Tests
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Sources
Introduction aux FPGA
Sources

Sources
I Introduction aux circuits FPGA, Arnaud Tisserand
I Introduction to FPGA Devices, Boards and tools (Slides from
George Manson University)
I http://www.fpgadeveloper.com/2011/07/
list-and-comparison-of-fpga-companies.html
I http://www.actel.com
I http://www.xilinx.com
I http://www.altera.com
I http://www.lyrtech.com
I http://www.digikey.com
I http://powwow.gforge.inria.fr
I http://opencores.org