Introduction to the PIC18

Microcontroller

Hsiao-Lung
H i L Chan
Ch
Dept Electrical Engineering
Chang Gung University, Taiwan
chanhl@mail cgu edu tw
chanhl@mail.cgu.edu.tw
Outline

Introduction to the PIC18 microcontroller

PIC18 assembly language programming
Interrupts, resets, and configuration
Parallel ports
Timers and CCP modules
Serial interface
Analog-to-digital
Analog to digital converter

2
Grading
g policy
p y

Midterm examinations + final test 60%

Attendance + efforts 20%
Reports 20% (No plagiarism)

3
PIC microcontroller vs. Intel MCS-51 (8051)
( )

"Peripheral
Peripheral Interface Controller"
Controller made by Microchip
Technology

8-bit ALU
Intel's original
g in the 1980s.
Several companies offer MCS-51 as IP cores in FPGAs or
ASICs.
68HC MCU and AVR

68HC microcontroller
8-bit microcontroller family introduced by Motorola in 1985.
Now produced by Freescale Semiconductor
CISC (complex instruction set computer) design

AVR
8-bit RISC MCU was sold to Atmel from Nordic VLSI

5
Computer
p hardware organization
g

P ro c e sso r

C o m m o n B u s ( ad d r e s s , d at a, & c o n t r o l )

C o ntro l U nit

D at app at h

Arithm e tic
L o gic U nit M e m o ry

O utput In p u t
P r o g r am D at a
U nits U nits
R e gis te rs S t o r ag
g e S t o r ag
ge

F i g u r e 1 .1 C o m p u t e r O r g an i zat i o n
Microprocessor
p vs. microcontroller (MCU)
( )

Microprocessor
A processor implemented on a very large scale

integration
g (VLSI)
( ) chip
p
Peripheral chips are needed to construct a product

Microcontroller
The processor and peripheral functions implemented on

one VLSI chip

7
Features of PIC18 MCU

8-bit
8 bit CPU
Memory
Electrical erasable programmable read-only memory (EEPROM)
Flash memory
Static random-access memory (SRAM)
Ti
Timers, including
i l di counters,
t input
i t capture,
t output
t t compare, real-time
l ti
interrupt, and watchdog timer
Pulse-width modulation (PWM)
Parallel I/O ports
SPI, I2C, controller area network (CAN) serial interface
Universal asynchronous receiver transmitter (UART)
10-bit A/D converter

8
Computer
p software

Machine instruction
Assembly language
High-level
High level language

Source code
Object code

9
Source code and object
j code examples
p

address object code line no. Source code

-------------------------------------------------------------------------------------------
---
00001E 0E06 00010 movlw 0x06
000020 6E11 00011 movwf 0x11,A
000022 0E07 00012 movlw 0x07
000024 6E12 00013 movwf 0x12,A
000026 0E08 00014 movlw 0x08
000028 6E13 00015 movwf 0x13,A
00002A 0E05 00016 movlw 0x05
00002C 5E10 00017 subwf 0x10,F,A
00002E 5E11 00018 subwf x11,F,A

10
PIC18 memoryy organization
g

Data memory and program memory are separated

This makes possible the simultaneous access of data and
instruction.
Data memory
General-purpose registers
Hold dynamic data
Special function registers
R i t
Registers used
d by
b CPU and
d peripheral
i h l modules
d l

11
PIC18 memoryy access

up to 2 MB of Inside the
c chipp
program memory

4096 registers
Program
Program
P counter
21-bit progam address 12-bit register address Data
Memory (PC)
Memory
Space Space
(a portion
PIC18 (Special
of this function
space is on CPU registers and
the c general
16-bit instruction bus 8-bit data bus
chip) purpose
RAM))

Fi
Figure 1.3
1 3 The
Th PIC18 memory spaces
12
 P C < 2 0 :0 >
21

s ta c k le v e l 1
.
.
.
s ta c k le v e l 3 1

After power-on, the PIC18 starts to R e s e t V e c to r

000000
h
execute instructions from address 0.
H ig h P r io r it y I n t e r r u p t V e c to r 000008h

L o w P r io r ity I n t e r r u p t V e c t o r 000018h
Up to 128KB (at present time) of

Memory Space
program memory is inside the MCU
chip O n - c h ip a n d e x t e r n a l
p r o gr a m m e m o r y

User M
y x x xx x h

U n im p le m e n te d
p r o gr a m m e m o r y
R ea d '0 '

1FFFFFh
N o te . y c a n b e 0 o r 1 w h e re a s x c a n b e 0 -F
F ig u r e 1 . 5 P I C 1 8 P r o g r a m m e m o r y O r g a n iz a tio n ( r e d r a w w ith p e r m is s io n o f
M ic r o c h ip )
13
PIC18 pipeline
pp

TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

MOVLW 55h fetch 1 execute 1

MOVWF PORTB f h2
fetch execute 2
BRA sub_1 fetch 3 execute 3
BSF PORTA
PORTA,BIT3
BIT3 fetch 4 flush
Instruction @address sub_1 fetch sub_1 execute
sub_1
N t All instructions
Note: i t ti are single
i l cycle,
l exceptt for
f any program branches.
b h

Figure 1.7 An example of instruction pipeline flow

No data dependency hazard in PIC18 MCU because of 2
2-stage
stage pipeline.
pipeline

14
15
BSR<3:0>
000h
= 0000 Access RAM 05Fh
B k0
Bank 060h
GPRs
0FFh
100h
= 0001
Bank 1 GPRs
1FFh
200h
= 0010
Bank 2 GPRs
2FFh
300h
= 0011 Access Bank
Bank 3 GPRs 000h
Access RAM low
3FFh 05Fh
400h Access RAM high 060h
SFRs
0FFh
Bank 4
to GPRs
Bank 13
DFFh
E00h
= 1110
Bank 14 GPRs
EFFh
Unused F00h
= 1111 F5Fh
Bank 15 F60h
SFRs
FFFh
16-bit instruction
Note. 1. BSR is the 4-bit bank select register.
Figure 1.4 Data memory map for PIC18 devices (redraw with permission of Microchip)
16
Access bank

PIC18 banks
4096 registers are divided into 16 banks.
Only one bank is active at a time.
B k switching
Bank it hi
When operating on a register in a different bank, bank
switching is needed.
Bank switching incurs overhead and may cause program
errors.
A
Access bank
b k
is created to minimize the problems of bank switching.
the lowest
o 96 bytes
by are
a general-purpose
g a pu po registers;
g ; the
highest 160 bytes, special function registers.
When operands (f) are in the access bank, no bank switching
is needed
needed.
17
Data movement instructions

18
movff

a 32-bit instruction
Copy a file register in one bank to a file register in another
bank without referring to the BSR register
Example
movff 0x100,0x300 ; copy data register 0x100 to data register 0x300

19
Instruction format: Byte-to-byte
y y operations
p

movff fs,, fd

1
15 12 11 0
opcode f (source file register)
15 12 11 0
1111 f (destination file register)

f = 12-bit file register address

Figure 1.9 Byte to byte move operations (2 words) (redraw with permission of Microchip)

20
movwf

a 16-bit instruction
Copy a working register (WREG) to a file register in the
force access bank or the selected bank
Example
movwf 0x30,A ; copy WREG to a register in access bank

WREG: A special register that is involved in the execution

of many instructions

21
 Instruction format: byte-oriented
y operations
p

movwf f,a
,

15 10 9 8 7 0
opcode d a f

d = 0 for result destination to be WREG register.

register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for
f BSR to select l bbankk
f = 8-bit file register address
Figure 1.8
1 8 Byte-oriented file register operations (redraw with permission of
Microchip)

22
movf

a 16-bit instruction
Copy a file register to the WREG register
Examples
p
movf 0x20,W,A
Copy register 0x20 in access bank to WREG
movff 0x20,W,BANKED
0 20 W BANKED
Copy register 0x20 in the specified by the BSR register to WREG

23
Status register
g

24
movlw/movlb

16-bit instructions
Copy a value to the WREG register/ set bank active
Examples
p
movlw 0x10 ; WREG 0x10
movb 3 ; load 3 into BSR (set bank 3 active)

25
Instruction format: literal operations
p

movlb k
movlw k

15 8 7 0
opcode k

k = 8-bit immediate value

Figure 1.11 Literal operations (redraw with permission of Microchip)

26
swapf
p

a 16-bit instruction
Swap nibbles
Example
p
swapf 0x30,F,A
swap the upper and lower 4 bits of the register 0x30

27
lfstr

a 32
32-bit
bit instruction
Load 12-bit value in the FSR (file select register)
3 FSR (FSR0, FSR1, FSR2), each FSR has low byte and
high byte
Example
p
lfsr FSR1,0xB00 ; place the value 0xB00 in FSR1

28
ADD instruction: addwf

Add WREG and f

addwf f,d,a
Examples
p
addwf 0x20,W,A
add data register
g in access bank and WREG and place sum in
WREG
addwf 0x20,F,A

29
ADD instruction: addwfc

Add WREG, carry bit and f

addwfc f,d,a
Examples
p
addwfc sum,F,A
add WREG, the register with the name sum, and carry and leave the
result in sum
addwfc sum,W,A

30
ADD instruction: addlw

Add literal and WREG

addlw k
Example
p
addlw 0x5 ; increment WREG by 5

31
Example: write an instruction sequence to increment the
contents of three registers 0x30-0x32 by 3

movlw 0x3 ; WREG 0x3

addwf 0x30, F, A
addwf 0x31, F, A
addwf 0x32, F, A

32
Example: write an instruction sequence to add the contents
of three registers 0x40-0x42 and store the sum at 0x50

movf 0x40, W, A ; WREG [0x40]

addwf 0x41, W, A
addwf 0x42, W, A
movwf 0x50, A ; [0x50] WREG

33
Examples
p

addwf 0x20,F,A
add the register at 0x20 in access bank with WREG
and store the sum in 0x20.
addwf 0x20,F,BANKED
add the register 0x20 in the bank specified by the BSR
register and
d store the
h sum in 0x20.

34
SUB instruction: subwf

Subtract WREG from f

subwf f,d,a
Examples
p
subwf 0x50, W, A ; WREG [0x50] [WREG]
subwf 0x30, F, A ; 0x30 [0x30] [WREG]

35
ADD instructions: subfwb, subwfb

Subfwb f, d, a ; subtract f from WREG with borrow

Subwfb f, d, a ; subtract WREG from f with borrow
Examples
subfwb 0x30,W,A ; WREG [WREG] [0x20] borrow flag
subwfb 0x10,F,A ; 0x10 [0x10] [WREG] borrow flag

36
SUB instruction: sublw

Subtract WREG from literal

sublw k
Example
p
sublw 0x10 ; WREG 0x10 [WREG]

37
Example: write an instruction sequence to subtract 9 from
the registers 0x50-0x53

movlw 0x09 ; WREG 0x9

subwf 0x50, F, A
subwf 0x51, F, A
subwf 0x52, F, A
subwf 0x53,
0x53 F,
F A

38
PIC18 addressing
g modes

Register direct
Immediate mode
Inherent mode
Indirect mode
Bit-direct
Bit direct addressing mode

39
Register
g direct

Use an 8
8-bit
bit value to specify a data register as operand.
movwf 0x45,A
movwf 0x1A,BANKED
,
movff 0x120,0x220

40
Immediate mode

A value in the instruction to be used as an operand.

addlw 0x20 ; add the hex value 0x20 to WREG
movlw 0x15 ; load 0x15 into WREG
movlb 3 ; place decimal value 3 to the lower 4 bits of
; the BSR register

41
Inherent mode

The operand is the opcode

andlw 0x3C ; the operand WREG is implied
movlw 0x20 ; the operand
p WREG is implied
p

42
Indirect mode

A special function register is used as a pointer to the data

memory location (actual data register) based on file select
registers (FSRn n = 0, 1, 2)
Indirect file register pointers: INDFn
Do nothing to FSRn after indirect access
Postdecrement register: POSTDECn
Auto-decrement FSRn after an indirect access
Postincrement
P ti t register:
i t POSTINC
POSTINCn
Preincrement register: PREINCn
Auto increment FSRn before an indirect access
Auto-increment
Use the value of WREG as an offset to FSRn: PLUSWn
FSRn is not modified after the access

43
Indirect addressing
g through
g FSR register
g

File select registers

FSR0, FSR1, FSR2
12 bits for addressing the
entire memory (4096 bytes)

44
Examples
p

movwf INDF0
copy the contents of WREG to the memory specified by the
FSR0
movwf POSTDEC0
The same operation as the above but the content of FSR0 is
decremented by 1 after the operation.
movwf PREINC0
First increments FSR0 by 1 an then copy the contents of
WREG to the memory specified by the FSR0
clrf PLUSW0
Clear the memory at the address equal to the value of
WREG and that of FSR0

45
Examples
p (cont.)
( )

movf POSTDEC0,W
Copy the memory specified by the FSR0 to the WREG.
The content of FSR0 is incremented byy 1 after the operation.
p
movff POSTINC0,PRODL
Similar operation
p as the above but data is copied
p to the
register with the name PRODL
movff PLUSW2,PRODL
Copy the memory at the address (= WREG + FSR2) to
PRODL
addwf
dd f PREINC1 F
PREINC1,F
FSR1 is incremented by 1
Add the
th content
t t off memory b
by FSR1 with
ith that
th t off WREG.
WREG
The sum leave the memory specified by FSR1 46
Bit-direct addressing
g mode

Deal with individual bit

15 12 11 9 8 7 0
opcode
d b a f

b = 3-bit pposition of bit in the file register

g (f).
()
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register
g address
Figure 1.10 Bit-oriented file register operations (redraw with permission of
Microchip)
BCF PORTB,3, A ; pull the port B pin RB3 to low (clear)
BSF PORTA,4,A
PORTA 4 A ; pullll the
h port A pin
i RA4 to high
hi h (set)
( )

47
Instruction format of control operations
p

Change the program execution sequence

15 8 7 0
opcode
p n<7:0>
n 7:0 (literal)
15 8 7 0 GOTO label
1111 n<19:8> (literal)
n = 20
20-bit
bit immediate value
15 8 7 0
opcode S n<7:0> (literal)
15 8 7 0 CALL funct_name
funct name
1111 n<19:8> (literal)
S = fast bit
15 11 10 0
opcode n<10:0> (literal) BRA label
15 8 7 0
opcode n<7:0> (literal) BC label

Figure 1.12 Control operations (redraw with permission of Microchip)

48
RISC vs. CISC
Reduced instruction set Complex
computer
Simple instruction set
Regular and fixed instruction
format
Simple address modes
Pi li d instruction
Pipelined i t ti execution ti
Most operations are register to
register
Take shorter time to design and
debug
p instruction set
computer
Complex instruction set
Irregular instruction format
Complex address modes
May also pipeline instruction
execution
ti
Most operations can be register
to memory
Take longer time to design and
debug
49
Reference

Han Way Huang, PIC Microcontroller: An Introduction to

Han-Way
Software and Hardware Interfacing, Thomson Delmar
Learning, 2005.
Wikipedia

50