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UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT 221 DIGITAL ELECTRONICS II LABORATORY

UNIVERSITI MALAYSIA PERLIS

SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING

EKT 221 DIGITAL ELECTRONICS II

LABORATORY MODULE

LAB 3

REGISTER TRANSFER LEVEL

UniMAP

DIGITAL ELECTRONICS II

LAB 3 : REGISTER TRANSFER LEVELE

LABORATORY OUTCOME

1. Ability to describe the functions of Register Transfer Level inside a digital system design.

2. Ability to discuss the types of micro-operations inside the Register Transfer Level.

3. Ability to transfer Algorithmic State Machines system flow onto registers or register cell operations.

4. Ability to construct a simple digital system that includes a Control Unit and Datapath Unit.

EQUIPMENTS/COMPONENTS

Computer Unit

Altera Quartus II software

INTRODUCTION

Register Transfer Level (RTL)

A digital system is a sequential logic system constructed using flip-flops and gates.

Sequential circuits can be specified by means of state tables and finite state diagrams as

done in the previous lab module. To specify larger digital systems using state tables may

be more difficult albeit possible because the number of states may be very large. To

overcome this difficulty, digital systems are usually designed in a modular approach and

partitioned into smaller subsystems that perform fundamental tasks. These modules are constructed from simple digital devices such as registers, decoders, multiplexers, arithmetic elements and control logics. Combining some or more of these devices and interconnected with common control paths and data paths will lead to the development of microprocessors and microcontrollers and other complex digital system controllers.

Digital systems are best defined by a set of registers and its operations like shift, count, clear and load. The information flow and operations on the data stored inside the registers are often referred to as Register Transfer Level or RTL in short. Three main components are specified when dealing with digital systems at the register transfer level:

The set of registers in the system

- The hardware that will have the ability to perform the elementary operations from the stored data such as shift, count, clear and load.

The operations that are performed on the data stored in the registers

- Elementary operations or better known as micro-operations such as

- R1R1+R2

The control that supervises the sequence of operations in the systems

- The control that initiates the sequence of events to perform the micro- operations in a prescribed manner

LAB 3

1

UniMAP

Types of micro-operations

DIGITAL EL ECTRONICS II

Micro-oper ation

Example

Transfer

R0 R1

Arithmetic

R0 R1 + 1

Logic

R0 R1 ^ R2

Shift

R0 sl R0

even though

they are represented by the s ymbols ‘*’ for multiplications and ‘/’ for divisi ons. They are

assumed to be implemented by the shift and add micro-operations.

Multiplications and divisions s are not listed as basic sets of micro-operations

multiple ‘R’s

which signifies the usage

specifications of a digital s ystem. The controller section of a digital syst em is usually represented by the variable ‘ K’ to show the conditional statements of the sy stem (control signals). A system may have more than one ‘K’ controller to meet the purpo se of multiple transfer operations.

of more than one sets of registers to mee t the desired

The register is usually repr esented by the variable ‘R’ and may include

An important note is that all registers have a load enable controller (LE) to allow data to

be stored into the destinati on register. Example 3.0 shows a particular operation and implementing the rules above.

RTL micro-

Example 3.0

An RTL for an n-bit adder/su btractor system can be represented as the follo wing RTL micro-operations :

can be represented as the follo wing RTL micro-operations : ; The block diagram for the

;

be represented as the follo wing RTL micro-operations : ; The block diagram for the tw

The block diagram for the tw o statements above can be built as shown below

:

R2 Adder - Subtractor K2 R1 K1
R2
Adder - Subtractor
K2
R1
K1

Figure 3.0 : Block Diagram of an n-bit Adder/Subtractor

UniMAP

DIGITAL EL ECTRONICS II

The diagram shows that K 2 is

load enable for register R1 . When K2=0 and K1 = 1, then R2 will be

contents of R1 and stored ba ck into R1. When K2=1 and K1=1, then the R2 will be subtracted from the contents of R1 and stored back into R1.

the selector for the add/subtract operation and K1 is the

added to the

For this example, the carry b it and overflow operations are not represented a nd left out, but can still be constructed if desired.

Note that RTL operations are registers are orignated from

always based on the edge transitions of clock p ulses as flip-flops.

PRE-LAB ASSIGNMENT

You are advised to do read operations before coming

preparation before coming in for the lab.

this chapter on RTL to fully understand the

in for this lab. Try on any exercise related

RTL micro-

as

to RTL

HOMEWORK EXERCISE

1. Show the diagram of the hardware that implements the register trans fer statements below :

a. A digital syst em with a controller function of

C3 : R 2 R1, R1 R2

b. A digital syst em that implements a 4:1 MUX and with the RT L function of

C0 : R 4 R0, C1 : R 4 R1, C2 : R 4 R2, C3 : R 4 R3

2. A digital system has

an n-bit register with S1 and S0 controls. Draw the RTL

block for a cell regist er with S1 and S0 input controllers that implem ent the

follwing function tab le :

S1

S0

Register Operation

0

0

Load parallel data

0

1

Clears register to 0

1

0

Complement output

1

1

No change

3. Using two 4-bit regis ters R1 and R2, draw a bit slice of the logic diag ram that implements the follo wing statements :

C0 : R 2 0; C1 : R 2 C2 : R 2 R1;

;
;
UniMAP DIGITAL ELECTRONICS II 4. Using D flip-flops to implement this design, a register cell
UniMAP
DIGITAL ELECTRONICS II
4. Using D flip-flops to implement this design, a register cell is to be used for an n-
bit register R0 that implements the register transfer functions of :
R0  0;
:
:
R0  R0  R1;
:
R0  R0  R1;
R0  R0  R1;
:
LAB 3
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