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Abstract: This article presents the design and construction of a transformer-typed Switch-
Mode Power Supply (SMPS) with multiple DC outputs. The developed circuit utilized the
SG3524 control circuitry at a fixed frequency to generate pulse width train. It was desired to
incorporate a transformer into the circuit so as to provide DC isolation and the desired
multiple-output voltages. The circuit was built with preferred values of components with a
DC input voltage of 12.00V. The voltages designed for the output terminals, Vo1, Vo2, Vo3,
Vo4 and Vo5 were 15.00V, 26.00V, 30.00V, 50.00V and 80.00V respectively. The overall
output power of the converter was found to be 169.7W while the total power loss in the
circuit was determined to be 20.3W with an efficiency of 89.3%. Also, the DC voltage
transfer function at the terminals: Vo1, Vo2, Vo3, Vo4 and Vo5 were found to be 1.08, 2.00,
2.33, 3.75 and 6.50 respectively. The developed circuit results in significant cost and space
savings for multiple output power supplies. This device is useful in digital systems and
electronic appliances such as TV, DVD, Cameras and Laptops which operate internally on
DC voltages.
Keywords: DC-to-DC, PWM, control circuitry, driver amplifier, power switch, rectifier.
Introduction
The term switched mode converter is used to describe a circuit which takes DC input
(unregulated) and provides single or multiple DC outputs, again of same or opposite polarity
and of a lower or higher voltage (Bakshi et al, 2010). The equipment for DC conversion can
be divided into four technologies (Fang and Hong, 2004):
i) AC/AC Transformers
ii) AC/DC Rectifiers
iii) DC/AC Inverters
iv) DC/DC Converters
DC/DC Converters
DC/DC Converters can be used to increase, decrease and/or reverse the voltage polarity at the
output. The basic equations of an ideal DC/DC converter are given as (Erickson, 1998):
Pin=Pout (1)
P=VI (2)
V=M(D)Vg (3)
Ig=M(D)I (4)
where Pin and Pout - input and output powers respectively, Vg - input voltage, V - output
voltage, Ig -input current, I- output current, M - conversion ratio and D is the duty cycle.
The oscillating frequency of the PWM circuit can be determined with the equation
(datasheetcatalog, 2010):
1.18
fs = (5)
RT CT
where RT and CT are Timing Resistor and Capacitor respectively, the range of practical values
specified in the manufacturers data sheet; RT is between 1.8 and 100k, while CT falls
between 1nF and 0.1 F. By choosing RT to be 24 k and CT to be 0.1 F,
1.18
fs = = 492 Hz
24, 000 (0.1 106 )
The period of oscillation, T of the PWM can be obtained from (datasheetcatalog, 2010):
T = R TC T (6)
Therefore,
T = 24000 x (0.1x10-6) = 2.4ms
Driver amplifier and power switch
Digital ICs are low power devices because they can supply only small load current (Malvino
and Bates, 2007). Therefore, there was need to amplify the pulse width train generated by the
SG3524 IC. The C1815 NPN Epitaxial Silicon Transistor is the selected transistor for the
driver amplifier stage due to its high dc current gain (hFE) linearity, high frequency
oscillation, and because, its a general purpose transistor. The Common-Emitter configuration
is the chosen connection for operating the circuit. This is because it has got high Current gain,
dc (50-300), very high Voltage gain (up to 1500) and Power gain (up to 10,000 or 40 dB)
(Akande et al, 2007).
In addition, the Voltage Divider Bias (VDB) technique is preferred for operating the
transistor. This is because it requires only a dc power supply, provides good bias stability and
operating point is almost independent of dc variation (Akande et al, 2007). The supply
voltage, VCC chosen for the design is 12V dc with 10 % tolerance. This was determined by
picking an approximate dc voltage based on the analysis of circuit limitation and availability
of 12V dc battery. The C1815 electrical characteristic table shown in Appendix B
specified collector-emitter voltage, VCE =6.0V, minimum hFE or dc =130 and collector
current, IC = 2.0mA. Let the load resistance be RL = 3K. The dc load line for the driver stage
amplifier is obtained using the equation (Akande et al, 2007):
VCE= VCC ICRC (7)
559 E.O. Ijoga and Dr. B.J. Kwaha
Ic
= (8)
IB
2mA
IB = = 15 A
130
The emitter voltage, VE can be obtained as (Malvino and Bates, 2007):
VE = 0.1 VCC (9)
VE= 0.1 x 12V = 1.2V
The emitter resistor, RE can be found using the expression (Akande et al, 2007):
VE
RE = (10)
IE
IC IE
1.2V
RE = = 600 (1k preferred).
2mA
The base voltage, VBB can be obtained from the relation given by (Malvino and Bates, 2007):
VE = VBB Vbe (11)
VBB = 1.2V + 0.7V = 1.9V
where, the base-emitter voltage for Silicon transistor is , Vbe = 0.7V
A well deserved VDB circuit satisfies the stiff voltage source condition given by (Malvino
and Bates, 2007):
R2 0.01dc RE (12)
Therefore,
R2 0.01 x (130) x (1000 ) = 1.3k (1.3k preferred)
The output of a VDB circuit is expressed as (Malvino and Bates, 2007):
R2 (Vcc VBB )
R1 = (13)
VBB
1.3K (12V 1.9V )
R1 = = 6910 (6.8k preferred)
1.9V
The choice of the semiconductor technology utilized for this power switch function was
influenced by factors such as low cost, peak voltage and current, frequency of operation and
heat sinking. Hence, the IRF1010E power FET was chosen for this design due to its ultra low
on-resistance (RDS(ON)) of about 12m . Other benefits includes: fast switching and
ruggedized device, low thermal resistance, provides high power capability, and good
switching capability (SMPSRM, 2007). The selected switching topology for the design is
561 E.O. Ijoga and Dr. B.J. Kwaha
called "push-pull" Converter, because the transformer has a double primary (centre-tapped).
The centre tap is connected to the 12V DC battery. The two ends of the primary are connected
to a pair of paralleled IRF1010 E MOSFETs. Each ties the MOSFET to ground in each
conduction cycle.
Power transformer stage
The design specifications are shown in Table 1.The overall output power, Pts for the DC
converter given as 190W. The voltage across the primary winding of a centre tap transformer
is twice the input dc voltage (bcae1, 2011). Thus, Vp = 24V ac and efficiency, = 0.95. The
current through the primary winding, IP is given by (McLyman, 2004):
PCS
Ip = (14)
V p
190W
A Ip = = 8.3 A
0.95 24
And the transformer input power; Pin is calculated as (McLyman, 2004):
Pin=IPVP (15)
Pin = 8.3A x 24 =199.2 W
The apparent power, Pt is calculated as (McLyman, 2004):
Pt = Pin + Pts (16)
Pt= 199.2 W + 190 W = 389. 2 W
The transformer operating frequency, fT is determined from the switching frequency, fS by
(datasheetcatalog, 2010):
1 (17)
fT = fs
2
1
fT = x 492 =246 Hz
2
The value of fT and the design parameters in Table 1 can be used to compute the windings.
The number of turns, Np at the primary winding can be computed by (Gottlieb, 1998):
E108
Np = (18)
4 fBS A
where E is the voltage, f is the transformer frequency, Bs is the flux density and A is the core
area.
24 x108
Np = = 47.2 (48 turns preferred value)
4 x 246 x15000 x3.448
Design and Construction of a Switch-Mode . 562
Appendix G: 0.000673cm AWG #29. And of 2685 (2.685 x 10-3 )
cm
Resistance: 5th secondary winding, Rs5 = 11.2 x 188 x (2.685 x 10-3) = 5.65
The copper loss for the 5th winding: Ps5 = (0.76)2 x 5.17 = 3.0W
The total secondary copper loss (McLyman, 2004):
PSL = Ps01 + Ps02 +Ps03 + Ps04 + Ps05 (28)
PsL= 1.04W + 1.38W +1.27W + 2.46W + 3.0 = 9.15W
The total copper loss is given by (McLyman, 1993):
Pcu= Pp + PsL (29)
Pcu = 7.6 + 9.2 = 16.8W
Appendix E: Core loss equation factors for EI lamination of 14.00 mils thickness with values
of the constants: k, m and n.
Manufacturers present core loss in the form of an equation such as (McLyman, 2004):
W/Kg = K fm Bn (30)
Pfe = (W/Kg) (Wtfe) (31)
where K, m, n are core constants, f is transformer frequency, B is core magnetic flux density,
Pfe is core lose, W/Kg is the Watt/Kilogram and Wtfe is the core weight.
W/Kg = 0.0005570 x (246 Hz) 1.68 x (1.5 T) 1.86 = 12.3 W/Kg
(Appendix D: The weight of the core is 108.8g (0.109Kg)).
Pfe = 12.3 x 0.109 = 1.3W
The total power loss, P can be expressed as (McLyman, 2004):
P = Pcu + Pfe (32)
P0
P = P0 (33)
where Pcu the copper loss, Pfe the core or iron lose, Po the output power and the efficiency
P = 16.8 + 1.3 = 18.1W
Therefore, the total loss in the designed circuit is calculated as 18.1W
Rectifier circuit and filtering capacitor
There are four choices of rectifier technology: the standard recovery diodes, fast recovery
diodes, the Ultra-fast recovery diode and Schottky rectifier (SMPSRM, 2007). The two
rectifier technologies utilized in this design are the full wave rectification using MUR120
ultra fast rectifier. This was chosen due to its fast turn off and high reverse voltage capability
of up to 1000V (SMPSRM, 2007). The other rectifier technology utilized is the GBPC1508W
Design and Construction of a Switch-Mode . 566
bridge rectifier; this was chosen due to its suitability for high voltage application. The cut off
Frequency, fc of a filter is given by (Malvino and Bates, 2007):
1
fc = (34)
2 RC
where C is capacitance and R resistance.
1
R= = 0.07 (80 preferred for convenience)
2 x3.143 x 492 x 4400 F
Implementation of the switch-mode dc/dc converter:
The proposed switch-mode DC/DC boost converter has been developed and tested. The
electrical circuitry of the system is depicted in Fig. 2. The circuit was powered by a 190W DC
source. Output currents as well as voltages were measured using digital multi-meter and
different values of dc lamp (4.1 , 5.5 , 8.2 , 9.6 , 12.3 , 13.7 and 16.4 ) as load
resistors.
The power can be expressed by (Akande et al, 2007):
V2
P= (35)
R
where V is the output voltage and R is the resistance (of the dc bulb)
Using equation (35) with the measurements obtained in Table 4, the output powers from the
terminals of the developed circuit in Table 5 were computed. To determine the overall output
power of the DC converter, maximum output powers obtained from each terminal were
collated and summed using the expression (McLyman, 2004):
Po (Total) = Po1(max) + Po2(max) + Po3(max) + Po4(max) + Po5(max) (36)
Po (Total) = 19.0 + 25.0 + 20.0 + 46.8 + 58.1 = 169.7W
The efficiency of a DC converter can be expressed by (Malvino and Bates, 2007):
= x 100% (37)
where is efficiency of the dc converter, Po the output power and Pin the input . With an
input power of 190W and total output power of 169.7W, the efficiency of the DC converter
can be calculated:
= x 100% = 89. 3%
Replacing with in equation (33), the Total loss in the developed circuit:
P0
PL = P0 (38)
where the efficiency of the DC converter
567 E.O. Ijoga and Dr. B.J. Kwaha
PL = 169.7 = 20.3W
DC voltage transfer function MV(DC) is given by (Rashid, 2007):
MV(DC) = (39)
D1
3K 3K
16V/2200F 13.0V DC
IRF10 10E
D2
100K
0.1F
24K
10K
G
6.8K G IRF1010E
D1
8 G ND
7 C
6 R
5 (-) S E N S E
4 (+ ) S E N S E
3 O sc. O ut
350K
(+ ) IN
(-) I N
16V/2200F 24.0V DC
T
D2
15K
SG3524 C1815
S H TD O W N 10
0 .3 3 F
COMP
4.0V D1
V REF
EA
CA
CB
EB
V IN
50V/4400 F 28.0V DC
9
11
12
13
14
15
16
+12V D2
S G
G
Bridge Rectifier
6.8K
F
00 78.0V DC
44
V/
50
4.0V
C1815
20K 1.3K 1K 1K
-12V DC
Results
The developed circuit was powered by a 12V DC supply (190W source). Table 2 shows
experimental measurements of output currents, Io as well as load voltages, Vload taken at the
various terminals using three different load resistances (4.1 , 5.5 and 8.2 ). Figs.3, 4 and 5
are graphical interpretation of Table 2. The readings in Table 3 compares the voltages
measured across the various output terminals of the developed circuit when there were no
loads connected and that of the designed values (Vexp). Also, Table 3 shows the voltage
transfer function (AV) and percentage errors (P.E) computed from the measurements. Table 4
is the summary of the load voltages measured at the various output terminals of the DC/DC
converter when the load resistances were varied; the dc load resistances connected ranged
from 4.1 to 16.4. Table 5 is the summary of output powers at the various terminals of the
power converter with different load resistances. These values were computed using the
measurements obtained from the various output terminals of the dc converter. Fig 6 shows
the graph of load Voltage, (Vload) ploted against Load resistance (R). The load voltages were
obained from the various output terminals of the power converter. Fig 7 shows the graph of
the output power (Po) obtained from the various terminals plotted against the Loads
resistances (R).
Fig. 3: Graph of Vload versus Io for a load resistance of 4.1 (dc lamp)
Fig. 4: Graph of Vload versus Io for a load resistance of 5.5 (dc lamp)
Fig. 5: Graph of Vload versus Io for a load resistance of 8.2 (dc lamp)
Design and Construction of a Switch-Mode . 570
Table 4: Summary of load voltages at various output terminals with load resistance
R( ) Vload1(V) Vload2 (V) Vload3(V) Vload4(V) Vload5(V)
(0utput,#o.1) (0utput,#o.2) (0utput,#o.3) (0utput,#o.4) (0utput,#o.5)
4.1 8.68 7.30 7.46 11.11 13.00
5.5 10.22 9.30 8.89 13.37 16.50
8.2 12.16 11.48 12.30 19.60 20.50
9.6 13.43 13.15 14.11 18.24 22.85
12.3 15.12 15.13 14.64 20.42 26.32
13.7 16.07 18.50 15.62 22.33 28.22
16.4 17.57 19.68 16.89 26.24 30.83
571 E.O. Ijoga and Dr. B.J. Kwaha
Discussion
Figs 3 through 5 are characteristic linear plots for Ohmic conductor. They show voltage-
current proportionality; voltages increase with increase in currents. The gradients are
positive. In the absence of an applied potential difference, there is no current flow. Thus, the
plots pass through the origin. The slopes obtained from each of the graphs corresponded to
the values of the load resistances used for the experiment. These show that the developed
circuit obeys ohms principle. Hence, validates the circuit. Table 3 shows a strong correlation
between theory and experiment. It compares the no-load voltages measured across the
various output terminals of the developed circuit and that of the designed values (Vexp). The
voltages from the developed circuit have slight deviations from the designed values. These
were determined using the percentage error (P.E) method as shown in Table 3. The
deviations ranged from 15.3% to 2.6%. Though, it was envisaged that there may be slight
deviations. These were due to the non-ideal properties of the component utilized and losses.
The losses in the designed circuit were found to be 18.1W while the Loss from the developed
circuit was 20.3W. Electromagnetic Interference was a major issue. However, passive filters
were employed to attenuate interferences radiated from the power devices. Table 5 shows
that, as the load resistances are being increased, the output power also increase in direct
573 E.O. Ijoga and Dr. B.J. Kwaha
proportion. Maximum output power was computed from the terminals. These powers were
summed so as to obtain the overall output power of the Converter. This was found to be
169.7W. The measurements shown in Table 4 revealed that, for each output terminal of the
dc Converter, the load resistances increase in direct proportion with the load voltage. Fig 6
shows that output terminal five has the maximum load voltage of 30.83V at 16.4 while
output terminal three has the least voltage of 7.46V at 4.1. In addition, the resistance of the
dc circuit increase as voltage increase. From Fig. 5, it can also be seen that the plot for
terminal four has a shape increase and a drastic drop. This was caused by the effect of stray
and parasitic capacitances; these were unavoidable as they were the unwanted capacitance
that exists between the parts of the circuit due to component proximity to each other. Also,
all actual circuit elements such as: inductors, diodes and transistors have internal capacitance,
which can cause their behaviour to depart from that of ideal circuit elements. Closely
spaced conductors, such as wires or Printed Circuit Board (PCB) traces were also a factor.
leakages to chassis from circuit as well as temperature effect on voltage transformation were
also responsible for the sharp increase nd drop. Fig 6 shows that output terminal five has the
maximum power of 58.1W while output terminal two has the least output power of 13.0W.
In the design of this circuit, it was assumed that the circuit will be most utilized at its
maximum power output. Thus, the need for several readings at the various output terminals.
The maximum output powers obtained at the various terminals were summed so as to
compute the overall output power of the circuit. This was found to be 169.7W. Having
determined the total output power of the developed circuit, the efficiency of the DC/DC
converter was found to be 89.3% with a power loss of 20.3W. The power loss and efficiency
calculation of the converter system were utilized for the overall performance evaluation of
the converter. It can be observed that the practical results obtained from the experiments are
reasonable compared to theoretical results obtained from the design if the losses in the system
are taken into account. For safe use of DC voltage without specific insulating precautions, the
voltage must not exceed 50 V as reported by Peter (2005). Therefore, the DC voltages
obtained from terminal one through terminal four as presented in Table 3 are within the
acceptable limit, and can be tolerated in real life. However, adequate precaution should be
taken in handling the DC voltage from terminal five for safety reason. The stabilized voltages
obtained from the developed circuit can be used where high voltage fluctuations are present.
Design and Construction of a Switch-Mode . 574
Conclusion
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