HOW TO USE EMBEDDED

INSTRUMENTS AND
IJTAG/JTAG

AN IEEE P1687 TUTORIAL

 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

An IJTAG Tutorial

By Al Crouch

Al Crouch, Chief Technologist Core Instruments

at ASSET InterTech, is a Senior Member of the
IEEE. Al has served as the vice chairman of the
IEEE P1687 IJTAG working group that is
developing the IJTAG standard and has
contributed significantly to the hardware
architecture definition. Al is the editor of the
P1838 Working Group on 3D test and debug and
co-chair of the iNEMI BIST group investigation
defining the use of Chip-Embedded Instruments to
assist with Board Test.

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

Table of Contents
Overview ......................................................................................................................................... 4

Industry Drivers .......................................................................................................................... 4

The Synergy of Standards ........................................................................................................... 5

Who will use IEEE P1687 IJTAG? ............................................................................................ 5

The Basic P1687 On-Chip Architecture ......................................................................................... 6

The Instrument Gateway (Interface) ............................................................................................... 7

Managing 1687 scan paths with the Segment Insertion Bit (SIB) .................................................. 8

IJTAG Description Languages ....................................................................................................... 8

The IJTAG Network Building Block .............................................................................................. 9

Conclusion .................................................................................................................................... 10

Table of Figures
Figure 1: The Basic IEEE P1687 IJTAG Architecture ................................................................... 6

Figure 2: The Basic IEEE P1687 IJTAG Architecture ................................................................... 6

Figure 3: The Instrument Gateway Interface .................................................................................. 7

Figure 4: The Gateway Segment-Insertion-Bit (SIB) ..................................................................... 8

Figure 6: The simplest IEEE P1687 IJTAG Network .................................................................... 9

2011 ASSET InterTech, Inc.

ASSET and ScanWorks are registered trademarks while the ScanWorks logo is a trademark of ASSET InterTech,
Inc. All other trade and service marks are the properties of their respective owners.

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

Overview
The goal of IEEE P1687 Internal JTAG (IJTAG) is to streamline the use of instruments that have
been embedded in chips. The intent is to facilitate the deployment of these embedded
instruments in a wider array of chip, board and system level validation, test and debug
applications. Over the last decade, semiconductor manufacturers have embedded instruments in
their chips to simplify the characterization, testing and debugging of these devices. Given the
right standards-based tools environment, these same instruments can perform a much broader
spectrum of chip, board and system level validation, test and debug applications.

Industry Drivers

Several conditions in the electronics industry are motivating this trend toward embedded
instrumentation and thereby have created a need for the IEEE P1687 IJTAG standard. For circuit
boards, the progress of advanced technologies such as complex microprocessors and very high-
speed buses has outstripped the capabilities of the older legacy validation and test equipment. By
and large, this legacy equipment is intrusive in that it is external to the board being tested and it
relies upon placing a physical probe on some sort of an access point on the board or on a chip on
the board. For a number of reasons, the effective availability of these access points is rapidly
diminishing and this is reducing the validation and test coverage that can be achieved with
legacy intrusive testers, such as oscilloscopes and logic analyzers for validation, and in-circuit
test (ICT) and manufacturing defect analyzers (MDA) for production test. Because the testing of
boards with external, intrusive instrumentation has become increasingly less effective, the
industry has turned to non-intrusive software-based embedded instrumentation which executes
out of hardware on the board being test and is not limited by physical probes.

At the chip level, there are several other factors that are driving the industry toward embedded
instrumentation. Keeping pace with Moores Law has meant that chips have become much
denser in terms of the number of transistors per square millimeter. In addition, chip frequencies
have gone up significantly and devices are much more complex. All of this means that
characterization times are longer and more sophisticated test equipment is needed. Advanced
chip packaging concepts such as stacking multiple die in three-dimensional packages also
complicates chip-level characterization and debug.

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

The time-to-market for electronic products is rapidly shrinking and this affects all aspects of a
products development cycle, including validation and test. For example, the average life of a
cell phone today is approximately eight months. In the past, test routines were developed
separately for each phase of product development and manufacturing. Now, the industry cannot
afford the luxury of the extra time that is needed to re-develop tests for a product as it transitions
from each phase in its life. Portable tests and other routines that accompany chips and which can
be re-applied in every phase of a products life cycle are becoming a necessity because of the
shorter life cycles. To achieve this level of portability the tests must capitalize on embedded
instrumentation. One way to do so will be the capabilities of the IEEE P1687 IJTAG standard.

The Synergy of Standards

To fully capitalize on embedded instrumentation, several other standards besides the IEEE
P1687 IJTAG standard often work together. These would include the IEEE 1149.1 Boundary-
Scan Standard and its enhanced version, the IEEE 1149.7 Enhanced Boundary-Scan Standard, as
well as the IEEE 1500 Core Test Standard.

Who will use IEEE P1687 IJTAG?

The IEEE P1687 IJTAG standard will be applied at the chip and board levels. Chip designers, for
example, will find IJTAG useful during design verification when it will be used in conjunction
with a simulator or emulator. IJTAG will also be deployed in the ATE test environment where it
will become part of chip test, chip debug/diagnostics and chip characterization.

At the circuit board level, the IEEE P1687 IJTAG standard will be used to access instruments
that are embedded in chips to perform board-level test, debug/diagnostics and characterization.

Finally, when a system is failing in the field, maintenance personnel can utilize the same tests
based on embedded instruments to extract failure data from a device. This data, along with other
environmental data, such as voltage and temperature, can be fed back to the organizations
failure analysis team when it can analyze the root causes of failures. This will allow the
duplication of the failure conditions and as a consequence reducing reduction in the amount of
No Trouble Found (NTF) cases.

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

The Basic P1687 On-Chip Architecture

Figure 1 illustrates the architecture that the IEEE P1687 IJTAG standard would implement at the
chip level. On the right, it shows how the IJTAG network interfaces to the IJTAG-compliant
embedded instruments with the IEEE 1149.1 boundary-scan standards Test Access Port (TAP)
on the left. The TAP functions as the interface for the embedded P1687 IJTAG architecture to
the world outside of the chip.

The Graphic View of the P1687 Architecture

Yes, P1687

SiB T Done M
D Fail B
Not P1687 R I
Reset
S
Run
TMS RW T
TAP
TCK Controller
TDI PDL Vectors go here Not P1687
IR=10111 SiB
TDO

T Done M
D B
SiB Fail
R I
Reset
S
Run
RW T

PDL Vectors go here

The Controller The P1687 Scan-Path Network The Instrument

1149.1 TAP & Design-ware, EDA Generated IP, Design-ware, EDA Gen
TAP Controller Compliant to P1687 Rules Portable/Reusable
BSDL P1687 Network ICL Raw Instrument ICL, PDL

ASSET 2011 Tutorial: IJTAG Basics 2 # 17

Figure 1: The Basic IEEE P1687 IJTAG Architecture

Essentially, IEEE P1687 IJTAG allows the boundary-scan TAP and its TAP Controller to access
instruments that are embedded on-chip. Several IJTAG concepts are shown in this illustration,
including the Segment Insertion Bit (SIB) and Procedural Description Language (PDL). These
will be described at greater length below.

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

The Instrument Gateway (Interface)

Figure 2 illustrates how the hardware interface or gateway for the IEEE P1687 IJTAG standard
on-chip architecture can interface to a standard IEEE 1149.1 boundary-scan standard Test Data
Register (TDR). Isolating the P1687 IJTAG architecture from the requirements of the interface
leading off the chip ensures the portability of embedded instrument intellectual property (IP) as
well as any vector IP that may be associated with them. In fact, an off-chip interface other than
the IEEE 1149.1 boundary-scan TDR could emerge in the future and this would not affect the
portability of IEEE P1687 IJTAG instruments or vectors.

1687 Hardware Interfaces: 1687 Starts at GW

Level-0 Gateway for IP
Level-0 Gateway is Scalability becomes Level-1 Gateway
beginning of 1687 and when integrated
IP Reusability Vectors are delivered
Embedded IP with the Instrument
toSerialIn
with and tools retarget
Embedded them = portable reuse
Select A Instruments
TDI
TCK TDO and its own
B Gateway
ResetN C
D Embedded IP
Capture-En
E Doubly
Embedded IP with its own
TDI
Shift-En TDO with Embedded
Embedded Instruments,
F Instruments
Update-En Gateway, and
G and its own
Gateway doubly
H embedded IP
fromSerialOut
Level-0 Gateway for IP becomes Level-1 Gateway to
TDR Interface Port Functions compound IP and Level-2 Gateway when integrated into chip

The 1687 Standard starts at the Gateway, not the TAP, to allow portable IP and other future controllers

ASSET 2011 Tutorial: IJTAG Basics 2 # 16

Figure 3: The Instrument Gateway Interface

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

Managing 1687 scan paths with the Segment Insertion Bit (SIB)
One of the key elements defined in the IEEE P1687 IJTAG standard is the Segment Insertion Bit
(SIB). The composition of a SIB is shown in Figure 3. A SIB is similar to an IEEE 1149.1
boundary-scan shift/update cell, but the SIB is used to dynamically configure an on-chip P1687
IJTAG scan path to meet the requirements of a particular set of test vectors. Selecting a certain
SIB can activate a portion of the chips IJTAG scan path and consequently activate the
instrument(s) on that segment of the scan path. Conversely, de-selecting a SIB will deactivate a
portion of the chips overall scan path and render the instruments on that segment inaccessible.
Instruments on a deactivated segment of the scan path cannot be accessed as long as the scan
path segment is deactivated, but they can still execute test vectors while they are offline.

The Gateway Segment-Insertion-Bit (SIB)

The Key Element for Adding, Organizing, Managing Embedded Content

Shift-Update Cell TDO

used as a SIB

fromScanOut

toScanIn

TDI Select
SC U
The HIP

TCK
Scan Path Management Bit
Violates 1149.1/1500 Tenet of Separation of Instruction & Data

The Gateway Register is made of one or more of these SIBs

ASSET 2011 Tutorial: IJTAG Basics 2 # 12

Figure 4: The Gateway Segment-Insertion-Bit (SIB)

IJTAG Description Languages

There are two description languages defined by the IEEE P1687 IJTAG standard: Instrument
Connectivity Language (ICL) and Procedural Description Language (PDL).

ICL describes the IEEE P1687 hardware architecture that is implemented on a chip. Essentially,
it describes the scan paths and the instruction registers that are associated with each scan path.
Since an IEEE P1687 SIB can activate or deactivate segments of a chips total scan path, any

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 How to use embedded instruments and IJTAG/JTAG An IEEE P1687 Tutorial

number of different scan paths can be implemented on a particular chip. ICL is used to describe
each of these scan paths.

PDL defines the instruments operations and functions and it is eventually turned into test
vectors that are associated with each IEEE P1687 IJTAG instrument that is embedded on a
device. In addition, PDL will document each instruments actions and sequences.

The IJTAG Network Building Block

Figure 5 illustrates the most basic unit or building block in an IEEE P1687 IJTAG architecture.
Shown here as a block diagram is an IEEE 1149.1 boundary-scan standards TAP controller on
the left, which provides access from the outside world to the on-chip IJTAG architecture. The
TAPs Test Data In (TDI) and Test Data Out (TDO) registers are connected in a scan path to a
boundary-scan Test Data Register (TDR) which acts as a read/write front-end to an IEEE P1687
IJTAG embedded instrument. As noted in the drawing, IJTAGs ICL language defines the
read/write signals that interface the TDR to the embedded instrument. And IJTAGs PDL defines
the actions, test vectors and other operations that the instrument executes.

Depiction of the Simplest Network

ICL Here

TDR I
TMS TAP n
TCK Controller T s
TDI y t
TDO p r
e Write u
Signal Legend m
Blue = Data H e
Red = Status Read n
Green = ScanPath t

PDL Applied Here

A Legal 1149.1 TDR accessed from an Instruction

- The difference = ICL/PDL

ASSET 2011 Tutorial: IJTAG Basics 2 # 20

Figure 5: The simplest IEEE P1687 IJTAG Network

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Conclusion
This is very brief overview tutorial of the IEEE P1687 IJTAG embedded instrumentation
standard. It is by no means comprehensive. An expanded version of this tutorial will be
forthcoming from ASSET as the standard nears ratification.

For further information on the IEEE P1687 IJTAG standard visit the working groups web site at
http://grouper.ieee.org/groups/1687/.

Learn More

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(IJTAG)? Register for our
whitepaper and learn the
objectives of the IEEE P1687
working group, how it achieved
those objectives and the
resulting IJTAG architecture
that is embodied in the
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standard.