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Code: R7210203 R07

B.Tech II Year I Semester (R07) Supplementary Examinations December 2014


PULSE AND DIGITAL CIRCUITS
(Common to EEE & EIE)

Time: 3 hours Max. Marks: 80


Answer any FIVE questions
All questions carry equal marks
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1 (a) Derive the expression for rise time of integrated circuit and prove that it is proportional to time constant
and inversely proportional to upper 3 dB frequency.
(b) A symmetrical square wave of peak to peak amplitude V and frequency f is applied to a high pass RC
circuit. Find the % of tilt and how it can be reduced.

2 (a) Design a diode clamper circuit to clamp the positive peaks of the input signal at zero level. The frequency
of the input signal is 500 Hz.
(b) For the circuit shown in figure given below. Sketch the input and output wave forms .
R
+ +
0

- 0 -

3 (a) Explain how transistor can be used as a switch in the circuit, under what conditions a transistor is said to
be OFF and ON respectively.
(b) A transistor has and operater with and . The
transistor is operating initially in the neighborhood of the cut in point. What base current must be applied
to drive the transistor to saturation in 1 sec?

4 (a) Explain the reason for the occurrence of overshoot at the base of normally ON transistor of one shot.
Derive an expression for overshoot.
(b) Discuss some of the applications of monostable multivibrator and explain how it differs with that of binary.

5 (a) Define the three errors that occur in a sweep circuit and obtain an expression for these errors for an
exponential sweep circuit.
(b) With reference to voltage sweeps explain the following terms:
(i) Sweep speed. (ii) Linearity of sweep. (iii) Recovery time.

6 (a) Explain the principle of synchronization and synchronization with frequency division.
(b) Write about: (i) Phase delay. (ii) Phase jitters.

7 (a) Differentiate a sampling gate from logic gate with an example.


(b) How a four diode gate is superior to two diode gate? Justify.

8 (a) Draw the circuit of 3 input OR gate using diodes and resistors and explain with truth table.
(b) Draw the circuit diagram of NAND gate using DTL logic and explain.

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