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A B C D E

Compal Confidential
Model Name : Z5WAH
File Name : LA-B161P
1 1

Compal Confidential
2 2

EA50_HB M/B Schematics Document


Intel Broadwell ULT (Broadwell + Wildcat point)

3 2014-03-04 3

REV:1.0

For 20140225 pre-MP gerber

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, March 04, 2014 Sheet 1 of 44
A B C D E
A B C D E

LCD Conn. Fan Control


page 30
CRT Conn.
LVDS LVDS-Translator
1
RTD2132R
page 17 1

page 21 page 18

DP to VGA Memory BUS 204pin DDR3L-SO-DIMM X1


BANK 0, 1, 2, 3 page 15
ITE IT6513FN eDP
Intel Broadwell ULT Dual Channel
page 20
1.35V DDR3L 1333/1600
HDMI Conn.
DDI 204pin DDR3L-SO-DIMM X1
DP x 2 lanes HDMI x 4 lanes
page 19 Broadwell ULT BANK 4, 5, 6, 7 page 16

Processor

MINI Card OPI USB 3.0 USB 2.0 CMOS


WLAN conn x1 conn x2 Camera
page 24
USB port 0 USB/B (port 1,2) USB port 7
page 26 page 18
2
PCIe 2.0 page 26 Finger 2

5GT/s Print
port 4
Wildcat point USB (port 5)
Flexible IO
26
SATA3.0 SATA3.0 PCH
PCIe 2.0 page 25
6.0 Gb/s 6.0 Gb/s USBx8 48MHz
5GT/s page 25 port 2 port 0
port 3
HD Audio 3.3V 24MHz
Touch
LAN(GbE)/ Card Reader Screen
HDA Codec I2C (PORT1)
Realtek 8411B SATA CDROM 1168pin BGA USB (port 6)
page 22 ALC283
Conn. page 04~14
SPI page 29 page 18
Card Reader RJ45 conn.
2 in 1 (SD) page 23
SATA HDD
page 23
Conn.
3
LPC BUS SPI ROM x2 3

CLK=24MHz Int. Speaker Int. MIC Combo Jack


page 7
ENE page 29 page 29 page 29

KB9012/9022
page 27

RTC CKT. Sub Board Touch Pad page 28


page 6 PS2 / I2C page 28 Int.KBD
LS-B161P
PWR/B
Power On/Off CKT. page 26
page 28

LS-B162P
USB/B (port 1,2)
DC/DC Interface CKT.
page 26
page 31

4
LS-B163P 4

Power Circuit DC/DC BATT/B (UMA)


page 39~50

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 2 of 44
A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.675VS +0.675VS power rail for DDR3L terminator ON OFF OFF
+1.05VS_VTT +1.05V power rail for CPU ON OFF OFF Board ID / SKU ID Table for AD channel
+1.35V +1.35V power rail for DDR3L ON ON OFF Vcc 3.3V +/- 5%
+1.5VS +1.5V power rail for CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW +3VALW always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 0 0 0 V 0 V 0 V
+3VS +3VALW to +3VS power rail ON OFF OFF 1 12K +/- 5% 0.347 V 0.354 V 0.360 V
+5VALW +5VALWP to +5VALW power rail ON ON ON* 2 15K +/- 5% 0.423 V 0.430 V 0.438 V
+5VS +5VALW to +5VS power rail ON OFF OFF * 3 20K +/- 5% 0.541 V 0.550 V 0.559 V
+RTCVCC RTC power ON ON ON 4 27K +/- 5% 0.691 V 0.702 V 0.713 V
5 33K +/- 5% 0.807 V 0.819 V 0.831 V
6 43K +/- 5% 0.978 V 0.992 V 1.006 V
7 56K +/- 5% 1.169 V 1.185 V 1.200 V
8 75K +/- 5% 1.398 V 1.414 V 1.430 V
9 100K +/- 5% 1.634 V 1.650 V 1.667 V
2 2
10 130K +/- 5% 1.849 V 1.865 V 1.881 V
11 160K +/- 5% 2.015 V 2.031 V 2.046 V
12 200K +/- 5% 2.185 V 2.200 V 2.215 V
13 240K +/- 5% 2.316 V 2.329 V 2.343 V

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
EC SM Bus1 address EC SM Bus2 address BTO Item BOM Structure
Board ID PCB Revision Unpop @
Device Address Device Address 0 0.1 Connector CONN@
Smart Battery 0001 011X On Board Thermal Senser 0100 110x 1 0.2 EC 9022 9022@
VGA Internal Thermal Senser 0100 000x 2 0.3 EC 9012 9012@
G Senser 0011 000x 3 1.0 UMA Component UMA@

PCH SM Bus address 4 2 SPI ROM 2ROM@


5 1 SPI ROM 1ROM@
Device Address 6 For EDP panel EDP@
ChannelA DIMM0 1001 000x JDIMM1 7 eDP to LVDS LVDS@
3 3
ChannelB DIMM1 1001 010x JDIMM2 Touch Screen TS@
USB Port Table 1 DMIC EA50@
3 External 2 DMIC EA54@
USB 2.0 Port USB Port EMC Component EMC@
0 USB Port(Left 3.0) Reservec for EMC XEMC@
1 USB Port(Right 2.0) G-Sensor BA@
2 USB Port(Right 2.0) TPM Module BA@
3 HDD redriver BA@
EHCI1
4 Mini Card (WLAN+BT)
5 Finger Print
6 Touch Screen
7 Camera
USB 3.0 Port
0 USB Port(Left 3.0)
1
4 XHCI 4
2
3

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 3 of 44
A B C D E
5 4 3 2 1

ZZZ

DAZ15400100
PCB
DAZ15400100
DAZ15400100
U1
PDC2957@
CPU 4319SOBOL01
D PDC2957 S IC CL8064701570000 SR1DV D0 1.4G ABO!
D

SA00007G060
HASWELL_MCP_E
U1 U1A
I34158@
CPU 4319SOBOL02
I3-4158 S IC CL8064701526902 SR18B C0 2G ABO!
SA00006VW40 C54 C45
20 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 18
C55 B46
U1
20
20
CPU_DP1_P0
CPU_DP1_N1
B58 DDI1_TXP0
DDI1_TXN1
EDP_TXP0
EDP_TXN1
A47
EDP_TXP0
EDP_TXN1
18
18
eDP Panel
PMD3558U@ C58 B47
CPU 4319SOBOL03 DP to CRT 20 CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 18
A55 C47
PMD3558U S IC CL8064701569500 SR1E8 D0 1.7G ABO! A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
SA00007G260 DDI1_TXP3 EDP_TXN3
DDI EDP B49
U1 C51 EDP_TXP3
19 CPU_DP2_N0 DDI2_TXN0
I54258@ 4319SOBOL04 C50 A45
CPU 19
19
CPU_DP2_P0
CPU_DP2_N1
C53 DDI2_TXP0
DDI2_TXN1
EDP_AUXN
EDP_AUXP
B45
EDP_AUXN
EDP_AUXP
18
18
B54
I5-4258 S IC CL8064701481503 SR18A C0 2.4G ABO! HDMI 19 CPU_DP2_P1
C49 DDI2_TXP1 D20 EDP_COMP R1 1 2 24.9_0402_1%
19 CPU_DP2_N2 DDI2_TXN2 EDP_RCOMP +VCCIOA_OUT
SA00006VZ60 B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
19 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
19 CPU_DP2_N3 DDI2_TXN3
U1 B53
19 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 18
I34010@
CPU 4319SOBOL05
I3-4010 S IC CL8064701478202 SR16Q C0 1.7G ABO!
SA00006SX70 1 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
U1 @
I34030@
C CPU 4319SOBOL08 C

I3-4030 S IC CL8064701552900 SR1EN D0 1.9G BGA 1168


SA00007TA60
U1
I54200@ 4319SOBOL09
CPU HASWELL_MCP_E
U1B
I5-4200 S IC CL8064701477702 SR170 C0 1.6G ABO!
SA00006SMB0 C94 1 2 6.8P_0402_50V8C
XEMC@ T20 @ D61
U1 T2 @ K61 PROC_DETECT
CPU I54210@
27 H_PECI
N62 CATERR
PECI
MISC

PRDY
J62 XDP_PRDY#_R @ T157
4319SOBOL10 K62 XDP_PREQ#_R @ T158
I5-4210 2 1 R68 R8 JTAG
PREQ E60 XDP_TCK_R @ T159
+1.05VS_VTT PROC_TCK
S IC CL8064701477802 SR1EF D0 1.7G BGA 1168 ABO ! 62_0402_5% 56_0402_5% E61 XDP_TMS_R @ T160
1 2 H_PROCHOT#_R K63 PROC_TMS E59 @ T161
SA00007LO70 27,32 H_PROCHOT# PROCHOT PROC_TRST
XDP_TRST#_R
THERMAL F63 XDP_TDI_R @ T162
C95 1 2 6.8P_0402_50V8C PROC_TDI F62 XDP_TDO_R @ T163
XEMC@ PROC_TDO
R6 1 2 10K_0402_5% H_CPUPWRGD C61
PROCPWRGD PWR
C60 1 2 6.8P_0402_50V8C J60 XDP_BPM#0_R @ T164
U1 XEMC@ BPM#0 H60 XDP_BPM#1_R @ T165
CPU QG21@ BPM#1 H61 @ T148
4319SOBOL06 BPM#2 H62 @ T149
BDW-ES1 DDR3 Compensation Signals R11 1 2 200_0402_1% SM_RCOMP0 AU60 BPM#3 K59 @ T150
S IC CL8065801674128 QG21 C0 1.2G BGA 1168 R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 @ T151
Trace width=12~15 mil, Spcing=20 mils R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 @ T152
SA00007OS10 SM_RCOMP2 BPM#6
Max trace length= 500 mil DIMM_DRAMRST# AV15 J61 @ T153
U1 DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
CPU QG22@
15 DDR_PG_CTRL SM_PG_CNTL1
B 4319SOBOL06
BDW-ES1 33P_0402_50V8J
B

1
2 OF 19 Rev1p2
S IC CL8065801675027 QG22 C0 1.2G BGA 1168 C2144 HASWELL-MCP-E-ULT_BGA1168
SA00007OT10 EMC@ @

2
+1.35V
1

R184
470_0603_5%
2

DIMM_DRAMRST# 15,16

2
C96
6.8P_0402_50V8C
1
XEMC@

Close to AV15
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(1/11) DDI,MSIC,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, March 04, 2014 Sheet 4 of 44
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E HASWELL_MCP_E
U1C U1D

DDR_A_D0 AH63 AU37


SA_DQ0 SA_CLK#0 SA_CLK_DDR#0 15
DDR_A_D1 AH62 AV37 DDR_B_D0 AY31 AM38
SA_DQ1 SA_CLK0 SA_CLK_DDR0 15 SB_DQ0 SB_CK#0 SB_CLK_DDR#0 16
DDR_A_D2 AK63 AW36 DDR_B_D1 AW31 AN38
SA_DQ2 SA_CLK#1 SA_CLK_DDR#1 15 SB_DQ1 SB_CK0 SB_CLK_DDR0 16
DDR_A_D3 AK62 AY36 DDR_B_D2 AY29 AK38
SA_DQ3 SA_CLK1 SA_CLK_DDR1 15 SB_DQ2 SB_CK#1 SB_CLK_DDR#1 16
DDR_A_D4 AH61 DDR_B_D3 AW29 AL38
SA_DQ4 SB_DQ3 SB_CK1 SB_CLK_DDR1 16
DDR_A_D5 AH60 AU43 DDR_B_D4 AV31
SA_DQ5 SA_CKE0 DDRA_CKE0_DIMMA 15 SB_DQ4
DDR_A_D6 AK61 AW43 DDR_B_D5 AU31 AY49
SA_DQ6 SA_CKE1 DDRA_CKE1_DIMMA 15 SB_DQ5 SB_CKE0 DDRB_CKE0_DIMMB 16
DDR_A_D7 AK60 AY42 DDR_B_D6 AV29 AU50
SA_DQ7 SA_CKE2 SB_DQ6 SB_CKE1 DDRB_CKE1_DIMMB 16
DDR_A_D8 AM63 AY43 DDR_B_D7 AU29 AW49
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D8 AY27 SB_DQ7 SB_CKE2 AV50
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D9 AW27 SB_DQ8 SB_CKE3
SA_DQ10 SA_CS#0 DDRA_CS0_DIMMA# 15 SB_DQ9
DDR_A_D11 AP62 AR32 DDR_B_D10 AY25 AM32
SA_DQ11 SA_CS#1 DDRA_CS1_DIMMA# 15 SB_DQ10 SB_CS#0 DDRB_CS0_DIMMB# 16
DDR_A_D12 AM61 DDR_B_D11 AW25 AK32
SA_DQ12 SB_DQ11 SB_CS#1 DDRB_CS1_DIMMB# 16
DDR_A_D13 AM60 AP32 DDRA_ODT0 @ T4 DDR_B_D12 AV27
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 DDR_B_D13 AU27 SB_DQ12 AL32 DDRB_ODT0 @ T5
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D14 AV25 SB_DQ13 SB_ODT0
SA_DQ15 SA_RAS DDR_A_RAS# 15 SB_DQ14
DDR_A_D16 AP58 AW34 DDR_B_D15 AU25 AM35
SA_DQ16 SA_WE DDR_A_WE# 15 SB_DQ15 SB_RAS DDR_B_RAS# 16
DDR_A_D17 AR58 AU34 DDR_B_D16 AM29 AK35
SA_DQ17 SA_CAS DDR_A_CAS# 15 SB_DQ16 SB_WE DDR_B_WE# 16
DDR_A_D18 AM57 DDR_B_D17 AK29 AM33
SA_DQ18 SB_DQ17 SB_CAS DDR_B_CAS# 16
DDR_A_D19 AK57 AU35 DDR_B_D18 AL28
SA_DQ19 SA_BA0 DDR_A_BS0 15 SB_DQ18
DDR_A_D20 AL58 AV35 DDR_B_D19 AK28 AL35
SA_DQ20 SA_BA1 DDR_A_BS1 15 SB_DQ19 SB_BA0 DDR_B_BS0 16
DDR_A_D21 AK58 AY41 DDR_B_D20 AR29 AM36
SA_DQ21 SA_BA2 DDR_A_BS2 15 SB_DQ20 SB_BA1 DDR_B_BS1 16
DDR_A_D22 AR57 DDR_B_D21 AN29 AU49
SA_DQ22 SB_DQ21 SB_BA2 DDR_B_BS2 16
DDR_A_D23 AN57 AU36 DDR_A_MA0 DDR_B_D22 AR28
DDR_A_D24 AP55 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D23 AP28 SB_DQ22 AP40 DDR_B_MA0
DDR_A_D25 AR55 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D24 AN26 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D26 AM54 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D25 AR26 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D27 AK54 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D26 AR25 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
C DDR_A_D28 AL55 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D27 AP25 SB_DQ26 SB_MA3 AR45 DDR_B_MA4 C
DDR_A_D29 AK55 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D28 AK26 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D30 AR54 SA_DQ29 SA_MA6 AW39DDR_A_MA7 DDR_B_D29 AM26 SB_DQ28 SB_MA5 AW46DDR_B_MA6
DDR_A_D31 AN54 SA_DQ30 SA_MA7 AY39 DDR_A_MA8 DDR_B_D30 AK25 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D32 AY58 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D31 AL25 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D33 AW58 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D32 AY23 SB_DQ31 SB_MA8 AU46 DDR_B_MA9
DDR_A_D34 AY56 SA_DQ33 SA_MA10 AW41DDR_A_MA11 DDR_B_D33 AW23 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D35 AW56 SA_DQ34 DDR CHANNEL A SA_MA11 AU41 DDR_A_MA12 DDR_B_D34 AY21 SB_DQ33 DDR CHANNEL B SB_MA10 AV47 DDR_B_MA11
DDR_A_D36 AV58 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D35 AW21 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D37 AU58 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D36 AV23 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D38 AV56 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D37 AU23 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D39 AU56 SA_DQ38 SA_MA15 DDR_B_D38 AV21 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D40 AY54 SA_DQ39 AJ61 DDR_A_DQS#0 DDR_B_D39 AU21 SB_DQ38 SB_MA15
DDR_A_D41 AW54 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D40 AY19 SB_DQ39 AW30DDR_B_DQS#0
DDR_A_D42 AY52 SA_DQ41 SA_DQSN1 AM58 DDR_A_DQS#2 DDR_B_D41 AW19 SB_DQ40 SB_DQSN0 AV26 DDR_B_DQS#1
DDR_A_D43 AW52 SA_DQ42 SA_DQSN2 AM55 DDR_A_DQS#3 DDR_B_D42 AY17 SB_DQ41 SB_DQSN1 AN28 DDR_B_DQS#2
DDR_A_D44 AV54 SA_DQ43 SA_DQSN3 AV57 DDR_A_DQS#4 DDR_B_D43 AW17 SB_DQ42 SB_DQSN2 AN25 DDR_B_DQS#3
DDR_A_D45 AU54 SA_DQ44 SA_DQSN4 AV53 DDR_A_DQS#5 DDR_B_D44 AV19 SB_DQ43 SB_DQSN3 AW22DDR_B_DQS#4
DDR_A_D46 AV52 SA_DQ45 SA_DQSN5 AL43 DDR_A_DQS#6 DDR_B_D45 AU19 SB_DQ44 SB_DQSN4 AV18 DDR_B_DQS#5
DDR_A_D47 AU52 SA_DQ46 SA_DQSN6 AL48 DDR_A_DQS#7 DDR_B_D46 AV17 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D48 AK40 SA_DQ47 SA_DQSN7 DDR_B_D47 AU17 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D49 AK42 SA_DQ48 AJ62 DDR_A_DQS0 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
DDR_A_D50 AM43 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D49 AR22 SB_DQ48 AV30 DDR_B_DQS0
DDR_A_D51 AM45 SA_DQ50 SA_DQSP1 AN58 DDR_A_DQS2 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AW26DDR_B_DQS1
DDR_A_D52 AK45 SA_DQ51 SA_DQSP2 AN55 DDR_A_DQS3 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AM28 DDR_B_DQS2
DDR_A_D53 AK43 SA_DQ52 SA_DQSP3 AW57DDR_A_DQS4 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AM25 DDR_B_DQS3
DDR_A_D54 AM40 SA_DQ53 SA_DQSP4 AW53DDR_A_DQS5 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AV22 DDR_B_DQS4
DDR_A_D55 AM42 SA_DQ54 SA_DQSP5 AL42 DDR_A_DQS6 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AW18DDR_B_DQS5
DDR_A_D56 AM46 SA_DQ55 SA_DQSP6 AL49 DDR_A_DQS7 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D57 AK46 SA_DQ56 SA_DQSP7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D58 AM49 SA_DQ57 AP49 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
SA_DQ58 SM_VREF_CA SM_DIMM_VREFCA 15 SB_DQ57
DDR_A_D59 AK49 AR51 DDR_B_D58 AK18
SA_DQ59 SM_VREF_DQ0 SA_DIMM_VREFDQ 15 SB_DQ58
DDR_A_D60 AM48 AP51 DDR_B_D59 AL18
SA_DQ60 SM_VREF_DQ1 SB_DIMM_VREFDQ 16 SB_DQ59
B DDR_A_D61 AK48 DDR_B_D60 AK20 B
SA_DQ61 SB_DQ60 16 DDR_B_D[0..63]
DDR_A_D62 AM51 DDR_B_D61 AM20
DDR_A_D63 AK51 SA_DQ62 DDR_B_D62 AR18 SB_DQ61
SA_DQ63 SB_DQ62 16 DDR_B_MA[0..15]
DDR_B_D63 AP18
SB_DQ63
16 DDR_B_DQS#[0..7]
15 DDR_A_D[0..63]
16 DDR_B_DQS[0..7]
15 DDR_A_MA[0..15]

15 DDR_A_DQS#[0..7]

15 DDR_A_DQS[0..7]
3 OF 19 Rev1p2 4 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 HASWELL-MCP-E-ULT_BGA1168
@ @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(2/11) DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 5 of 44
5 4 3 2 1
5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
R101 10M_0402_5%

Y1
32.768KHZ_12.5PF_Q13FC135000040
2 1
D D
15P_0402_50V8J

18P_0402_50V8J
1 1

C153 C154
2 2

HASWELL_MCP_E
U1E
+RTCVCC
1
C149
+RTCVCC 1U_0402_6.3V6K ME CMOS PCH_RTCX1 AW5
PCH_RTCX2 AY5 RTCX1
R69 2 R72 1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
+RTCVCC INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 25
20K_0402_1% PCH_INTVRMEN AV7 RTC H5
1 2 PCH_SRTCRST# AV6 INTVRMEN
SRTCRST
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
B15
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
25
25
HDD
1 2 PCH_RTCRST# AU7 A15
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 25
PCH_INTVRMEN R73 1 2 330K_0402_5% R70
R74 1 @ 2 330K_0402_5% 20K_0402_1% 1 27 PCH_RTCRST# J8 SATA_PRX_DTX_N1 25

2
C150 SATA_RN1/PERN6_L2 H8
SATA_RP1/PERP6_L2 SATA_PRX_DTX_P1 25

* HLIntegrated
INTVRMEN 1U_0402_6.3V6K JME1 reserve PCH_RTCRST# to EC pin 27 for clear CMOS A17
Integrated VRM enable SHORT PADS
SATA_TN1/PETN6_L2 B17
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
25
25
ODD

1
2 SATA_TP1/PETP6_L2
VRM disable @
HDA_BIT_CLK AW8 J6
HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# AU8 HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 B14
HDA_SDIN0 AY10 HDA_RST/I2S_MCLK SATA_TN2/PETN6_L1 C15
RTCRST close RAM door 29 HDA_SDIN0
T6 @ AU12 HDA_SDI0/I2S0_RXD AUDIO SATA SATA_TP2/PETP6_L1
C HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5 C
T7 @ AW10 HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 E5
T8 @ AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17
HDA for AUDIO T9 @ AY8 HDA_DOCK_RST/I2S1_SFRM
I2S1_SCLK
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
D17
RP14 EMC@
29 HDA_RST_AUDIO# 1 8 HDA_RST#
29 HDA_SYNC_AUDIO 2 7 HDA_SYNC V1 PCH_GPIO34 PCH_GPIO34 9
3 6 HDA_BIT_CLK SATA0GP/GPIO34 U1 PCH_GPIO35
29 HDA_BITCLK_AUDIO SATA1GP/GPIO35 PCH_GPIO35 9 +1.05VS_ASATA3PLL
29 HDA_SDOUT_AUDIO 4 5 HDA_SDOUT V6 PCH_GPIO36
SATA2GP/GPIO36 PCH_GPIO36 9
AC1 PCH_GPIO37
SATA3GP/GPIO37 PCH_GPIO37 9
33_0804_8P4R_5% T95 @
PCH_JTAG_RST# AU62
51_0402_5% 1 @ 2 R97 PCH_JTAG_TCK AE62 PCH_TRST A12 SATA_IREF R75 1 @ 2 0_0603_5%
R122 1 @ 2 0_0402_5% T21 @ PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11 @ T13
27 HDA_SDO PCH_TDI RSVD
T19 @ PCH_JTAG_TDO AE61 K10 @ T14
T15 @ PCH_JTAG_TMS AD62 PCH_TDO JTAG RSVD C12 SATA_RCOMP R2 1 2 3.01K_0402_1%
ME Debug T10 @ AL11 PCH_TMS
RSVD
SATA_RCOMP
SATALED
U3 R10 1 2 +3VS
T11 @ AC4 10K_0402_5%
T22 @ PCH_TCK_JTAGX AE63 RSVD
JTAGX SATA_RCOMP, IREF
T12 @ AV2
RSVD Trace width=12~15 mil, Spcing=12 mils
Max trace length= 500 mil

W=20mils trace width 10mil W=20mils 5 OF 19 Rev1p2


HASWELL-MCP-E-ULT_BGA1168
+RTCBATT +CHGRTC +RTCVCC @
D23
2

B BAS40-04_SOT23-3 1 B
C151
0.1U_0402_16V4Z

+RTCBATT
+RTCBATT
2

+CHGRTC
R446
+

1K_0402_5%
@
3 1

+RTCBATT_R
2

20mil
20mil
+RTCVCC

D32
1

CHN202UPT_SC70-3 JBATT1
-

1 @ LOTES_AAA-BAT-054-K01
2

C168 CONN@
0.1U_0402_16V4Z SP07000H700
@
2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(3/11) RTC,SATA,XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 6 of 44
5 4 3 2 1
5 4 3 2 1

HASWELL_MCP_E
U1F

XTAL24_IN C43 A25 XTAL24_IN


C42 CLKOUT_PCIE_N0 XTAL24_IN B25 XTAL24_OUT
2 1 XTAL24_OUT PCH_GPIO18 U2 CLKOUT_PCIE_P0 XTAL24_OUT
9 PCH_GPIO18 PCIECLKRQ0/GPIO18
1M_0402_5% R48 K21 @ T16
B41 RSVD M21 @ T17
Y2 A41 CLKOUT_PCIE_N1 RSVD C26 XCLK_BIASREF R78 1 2 3.01K_0402_1%
CLKOUT_PCIE_P1 DIFFCLK_BIASREF +1.05VS_AXCK_LCPLL
24MHZ_12PF_X3G024000DC1H PCH_GPIO19 Y5
9 PCH_GPIO19 PCIECLKRQ1/GPIO19
1 3 C35 R140 1 2 10K_0402_5%
D TESTLOW_C35 D
2 4 CLK_PCIE_LAN# C41 CLOCK C34 R141 1 2 10K_0402_5%
22 CLK_PCIE_LAN# CLKOUT_PCIE_N2 TESTLOW_C34
CLK_PCIE_LAN B42 AK8 R142 1 2 10K_0402_5%
15P_0402_50V8J

15P_0402_50V8J
1 1
PCIE LAN 22 CLK_PCIE_LAN
+3VS R52 1 2 10K_0402_5% AD1 CLKOUT_PCIE_P2
PCIECLKRQ2/GPIO20
SIGNALS TESTLOW_AK8
TESTLOW_AL8
AL8 R148 1 2 10K_0402_5%
22 LAN_CLKREQ#
C2 C3 CLK_PCIE_MINI1# B38 AN15 CLKOUT_LPC0 R390 2 EMC@ 1 22_0402_5%
2 2 24 CLK_PCIE_MINI1# CLKOUT_PCIE_N3 CLKOUT_LPC_0 CLK_PCI_LPC 27
CLK_PCIE_MINI1 C37 AP15 CLKOUT_LPC1 R395 2 TPM@ 1 22_0402_5%
24 CLK_PCIE_MINI1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM 28
MINI1_CLKREQ# N1
WLAN 24,8 MINI1_CLKREQ# PCIECLKRQ3/GPIO21
CLKOUT_ITPXDP_N
B35 CLK_BCLK_ITP# @ T184
A39 A35 CLK_BCLK_ITP @ T183
B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
PCH_GPIO22 U5 CLKOUT_PCIE_P4
PCIECLKRQ4/GPIO22
B37
A37 CLKOUT_PCIE_N5
PCH_GPIO23 T2 CLKOUT_PCIE_P5
9 PCH_GPIO23 PCIECLKRQ5/GPIO23

6 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@
HASWELL_MCP_E
U1G

LPC_AD0 AU14 AN2 PCH_GPIO11


+3VS 27,28 LPC_AD0 LAD0 SMBALERT/GPIO11 PCH_GPIO11 9
LPC_AD1 AW12 AP2 PCH_SMBCLK
27,28 LPC_AD1 LAD1 LPC SMBCLK PCH_SMBCLK 24
LPC_AD2 AY12 AH1 PCH_SMBDATA
27,28 LPC_AD2 LAD2 SMBDATA PCH_SMBDATA 24
LPC_AD3 AW11 AL2 PCH_GPIO60
27,28 LPC_AD3 LAD3 SML0ALERT/GPIO60 PCH_GPIO60 9
1

LPC_FRAME# AV12 SMBUS AN1 SML0CLK +3VALW_PCH


27,28 LPC_FRAME# LFRAME SML0CLK
R115 AK1 SML0DATA
10K_0402_5% SML0DATA AU4 PCH_GPIO73
SML1ALERT/PCHHOT/GPIO73 PCH_GPIO73 9
AU3 SML1CLK SML0CLK RP8 1 8 2.2K_0804_8P4R_5%
SML1CLK/GPIO75 AH3 SML1DATA SML0DATA 2 7
2

PCH_GPIO22 PCH_SPI_CLK AA3 SML1DATA/GPIO74 PCH_SMBCLK 3 6


C PCH_SPI_CS0# Y7 SPI_CLK AF2 @ T23 PCH_SMBDATA 4 5 C
PCH_SPI_CS1# Y4 SPI_CS0 CL_CLK AD2 @ T24
AC2 SPI_CS1 SPI C-LINK CL_DATA AF4 @ T25 SML1CLK R114 1 2 2.2K_0402_5%
PCH_SPI_MOSI AA2 SPI_CS2 CL_RST SML1DATA R113 1 2 2.2K_0402_5%
PCH_SPI_MISO AA4 SPI_MOSI
PCH_SPI_WP1# Y6 SPI_MISO
PCH_SPI_HOLD1# AF1 SPI_IO2
SPI_IO3

7 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

+3V_SPI
for Share EC ROM, +3VS change to +3VALW
PVT modify 01/20
R105 1 2 1K_0402_5% PCH_SPI_IO2_1 R126
R106 1 2 1K_0402_5% PCH_SPI_IO3_1 +3V_SPI +3V_SPI 1 @ 2 0_0402_5% +3VALW
R123
R103 1 @ 2 1K_0402_5% PCH_SPI_HOLD1# +3V_SPI 1 @ 2 0_0402_5% +3VS
R102 1 @ 2 1K_0402_5% PCH_SPI_WP1#
SPI ROM ( 8MByte ) +3VS

C66 1 2 +3VS

2
U6 RP19
PCH_SPI_CS0# 1 8 0.1U_0402_16V4Z PCH_SPI_MOSI_1 1 8 PCH_SPI_MOSI R116 R119
PCH_SPI_MISO_1 2 CS# VCC 7 PCH_SPI_IO3_1 PCH_SPI_CLK_1 2 7 PCH_SPI_CLK SPI ROM Q7A 4.7K_0402_5% 4.7K_0402_5%

2
PCH_SPI_WP1# 2 1 PCH_SPI_IO2_1 3 DO(IO1) HOLD#(IO3) 6 PCH_SPI_CLK_1 PCH_SPI_IO3_1 3 6 PCH_SPI_HOLD1# DMN66D0LDW-7_SOT363-6
R108 15_0402_5% 4 WP#(IO2) CLK 5 PCH_SPI_MOSI_1 PCH_SPI_MISO_1 4 5 PCH_SPI_MISO

1
B GND DI(IO0) PCH_SMBDATA 6 1 D_CK_SDATA B
D_CK_SDATA 15,16,30
EN25QH64-104HIP_SO8 15_0804_8P4R_5%

5
DDR, G-sensor
PVT PCH_SMBCLK 3 4 D_CK_SCLK D_CK_SCLK 15,16,30
Reserve for EMI(Near SPI ROM)
C152 PCH_SPI_MOSI_1 R498 1 @ 2 0_0402_5% EC_SPI_SO 27 Q7B
10P_0402_50V8J PCH_SPI_CLK_1 R500 1 @ 2 0_0402_5% EC_SPI_CLK 27
From EC DMN66D0LDW-7_SOT363-6
1 2 2 1 PCH_SPI_CLK_1 PCH_SPI_MISO_1 R502 1 @ 2 0_0402_5% EC_SPI_SI 27
(For share ROM)
R104 XEMC@ 33_0402_5% PCH_SPI_CS0# R505 1 @ 2 0_0402_5% EC_SPI_CS# 27
XEMC@
+3VS

Q8A

2
DMN66D0LDW-7_SOT363-6
PU 2.2K at EC side (+3VS)
SML1CLK 6 1 EC_SMB_CK2 27

5
+3V_SPI VGA, LVDS, EC
SPI ROM ( 4MByte ) RP20 SML1DATA 3 4 EC_SMB_DA2 27
C67 1 2 PCH_SPI_MISO_2 1 8 PCH_SPI_MISO
U7 @ PCH_SPI_IO3_2 2 7 PCH_SPI_HOLD1# Q8B
PCH_SPI_CS1# 1 8 0.1U_0402_16V4Z PCH_SPI_CLK_2 3 6 PCH_SPI_CLK DMN66D0LDW-7_SOT363-6
PCH_SPI_MISO_2 2 CS# VCC 7 PCH_SPI_IO3_2 PCH_SPI_MOSI_2 4 5 PCH_SPI_MOSI
PCH_SPI_WP1# 2 @ 1 R109 PCH_SPI_IO2_2 3 DO HOLD# 6 PCH_SPI_CLK_2 33_0804_8P4R_5%
4 WP# CLK 5 PCH_SPI_MOSI_2 @
33_0402_5% GND DI
EN25QH32-104HIP_SO8
@

A A

2ROM is SPI ROM 2M + 4M Byte


Reserve for EMI(Near SPI ROM)
C453
10P_0402_50V8J
R108 33 Ohm SD028330A80 1 2 2 1 PCH_SPI_CLK_2
RP19 33 Ohm SD309330A80 R402 XEMC@ 33_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
XEMC@ 2013/10/30 2014/10/30 Title
U6 SA00004UG00 Issued Date Deciphered Date BDW MCP(4/11) CLK,SPI,SMBUS
POP R102,R103,RP20,C67,U7,R109 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 7 of 44
5 4 3 2 1
5 4 3 2 1

+3VS

1
R227

* HLDisable
10K_0402_5% DSWODVREN - On Die DSW VR Enable
Enable(DEFAULT)
2
SYS_RESET# +RTCVCC
2 HASWELL_MCP_E
U1H
C513 R124 1 2 330K_0402_5%
D 0.01U_0402_16V7K R125 1 @ 2 330K_0402_5%
D
1 R206 SYSTEM POWER MANAGEMENT
XEMC@
SUSWARN# 1 @ 2 0_0402_5% SUSACK# AK2 AW7 DSWODVREN
SYS_RESET# AC3 SUSACK DSWVRMEN AV5 PCH_RSMRST#_R
SYS_PWROK R61 1 @ 2 0_0402_5% SYS_PWROK_R AG2 SYS_RESET DPWROK AJ5
place near AC3 SYS_PWROK WAKE
PCH_PCIE_WAKE# PCH_PCIE_WAKE# 22
27 PCH_PWROK R62 1 @ 2 0_0402_5% PCH_PWROK_R AY7 1K_0402_5% 1 2 R120 +3VALW_PCH
R63 1 @ 2 0_0402_5% PM_APWROK AB5 PCH_PWROK 8.2K_0402_5% 1 2 R157
11,27 VCCST_PG_EC APWROK +3VS
AG7 V5 CLKRUN# CLKRUN# 28
PCH_PWROK_R R64 1 @ 2 0_0402_5% PLTRST CLKRUN/GPIO32 AG4
PLT_RST# SUS_STAT/GPIO61 AE6 SUSCLK R127 1 @ 2
27,28 PLT_RST# SUSCLK/GPIO62 AP5 PM_SLP_S5# 10K_0402_5%
SLP_S5/GPIO63 PM_SLP_S5# 27
PCH_RSMRST# R117 1 2 10K_0402_5% 27 PCH_RSMRST# R79 1 @ 2 0_0402_5% PCH_RSMRST#_R AW6 @ T27
SUSWARN# AV4 RSMRST @ T28 @ T29
9 SUSWARN# SUSWARN/SUSPWRDNACK/GPIO30
27 PBTN_OUT# R110 1 @ 2 0_0402_5% PBTN_OUT#_R AL7 AJ6 PM_SLP_S4#
PWRBTN SLP_S4 PM_SLP_S4# 27
PCH_ACIN AJ8 AT4 PM_SLP_S3#
ACPRESENT/GPIO31 SLP_S3 PM_SLP_S3# 27
+3VALW_PCH R156 1 2 8.2K_0402_5% PCH_BATLOW# AN4 AL5 @ T30
T31 @ AF3 BATLOW/GPIO72 SLP_A AP4 @ T96
AM5 SLP_S0 SLP_SUS AJ7 PM_SLP_LAN# R118 1 @ 2
+3VALW_PCH SLP_WLAN/GPIO29 SLP_LAN +3VALW_PCH
10K_0402_5%
1

not support Deep S4,S5 can NC


R245 8 OF 19 Rev1p2
100K_0402_5% HASWELL-MCP-E-ULT_BGA1168
@ @
@ D21 Note: Deep Sx need use EC GPIO for
2

27,32,34 ACIN 1 2 PCH_ACIN


ACPRESENT function
RB751V-40_SOD323-2

+3VS
5

C R65 C
DDPB_CTRLDATA: Port B Detected
PCH_PWROK 2 0_0402_5%
P

B 4 SYS_PWROK 1 2 PCH_PWROK
Y DDPC_CTRLDATA: Port C Detected
VGATE_3V 1
A
G
1

U43 1: Port B or C is detected


*
3

R208 MC74VHC1G08DFT2G_SC70-5 R207


10K_0402_5% @ 10K_0402_5% 0: Port B or C is not detected
@
(Have internal PD)
2

HASWELL_MCP_E
U1I

+3VS
+3VS

+1.05VS_VTT B8 B9
17,18 PCH_INV_PWM EDP_BKLCTL DDPB_CTRLCLK
1

A9 C9 R271 1 2 2.2K_0402_5%
27 ENBKL EDP_BKLEN DDPB_CTRLDATA
U17 R310 C6 eDP SIDEBAND D9 DDI2_CTRL_CK
18 PCH_ENVDD EDP_VDDEN DDPC_CTRLCLK DDI2_CTRL_CK 19
1 5 10K_0402_5% D11 DDI2_CTRL_DATA
NC VCC DDPC_CTRLDATA DDI2_CTRL_DATA 19
@
11,39 VGATE 2
2

A 4 VGATE_3V PCH_GPIO77 U6
Y VGATE_3V 27 PIRQA/GPIO77
3 PCH_GPIO78 P4 C5 DDI1_AUX_DN
GND 9 PCH_GPIO78 PIRQB/GPIO78 DISPLAY DDPB_AUXN DDI1_AUX_DN 20
PCH_GPIO79 N4 B6
9 PCH_GPIO79 PIRQC/GPIO79 DDPC_AUXN
74AUP1G07GW_TSSOP5 PCH_GPIO80 N2 B5 DDI1_AUX_DP
PIRQD/GPIO80 DDPB_AUXP DDI1_AUX_DP 20
@ T26 @ AD4 A6
PME GPIO DDPC_AUXP
TP_INT# U7
28,9 TP_INT# GPIO55
30 G_SEN_INT G_SEN_INT L1
Project_ID1 L3 GPIO52 C8
GPIO54 DDPB_HPD CPU_DP_HPD 20
PCH_GPIO51 R5 A8 CPU_HDMI_HPD 19
9 PCH_GPIO51 GPIO51 DDPC_HPD
+3VS Project_ID0 L4 D6 CPU_EDP_HPD 18
B GPIO53 EDP_HPD B

RP27 1 8 G_SEN_INT
2 7 PCH_GPIO80
3 6 MINI1_CLKREQ# MINI1_CLKREQ# 24,7 9 OF 19 Rev1p2
4 5 DEVSLP0 DEVSLP0 25,9 HASWELL-MCP-E-ULT_BGA1168
10K_0804_8P4R_5% @

+3VS

R210 1 2 PCH_GPIO77

10K_0402_5%

+3VS

5
VCC
+3VS +3VS PLT_RST# 1
IN1 4
OUT PLT_RST_BUF# 22,24
2

GND
1

1
IN2
R205 R204 R416
10K_0402_5% 10K_0402_5% Project_ID1 Project_ID0 100K_0402_5%
Project ID

3
@ EA54@ U30
GPIO54 GPIO53 MC74VHC1G08DFT2G_SC70-5
2

2
Project_ID1 Project_ID0
*EA50 0 0
2

A R214 R215 EA54 0 1 A


10K_0402_5% 10K_0402_5%
EA50@ Reserved 1 0
Reserved 1 1
1

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(5/11) PM,GPIO,DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 8 of 44
5 4 3 2 1
5 4 3 2 1

+3VS +3VS

RP23 1 8 PCH_GPIO87 RP36 1 8 EC_SMI#_SCI#


2 7 PCH_GPIO51 PCH_GPIO51 8 2 7 PCH_GPIO85
3 6 PCH_GPIO78 PCH_GPIO78 8 3 6 PCH_GPIO92
4 5 PCH_GPIO83 4 5 PCH_GPIO88
10K_0804_8P4R_5% 10K_0804_8P4R_5%
RP24 1 8 PCH_GPIO68
2 7 PCH_GPIO69
3 6
4 5 change to I2C0 for TS use for PVT 1/10 modify
10K_0804_8P4R_5%
RP25 1 8 PCH_GPIO1 +1.05VS_VTT
2 7 PCH_GPIO94
D D
3 6 PCH_GPIO93

1
HASWELL_MCP_E
4 5 PCH_GPIO2 U1J
10K_0804_8P4R_5% R144
RP26 1 8 PCH_GPIO91 1K_0402_5%
2 7 PCH_GPIO0
3 6 PCH_GPIO90

2
4 5 PCH_GPIO38 PCH_GPIO76 P1 D60 H_THERMTRIP#
10K_0804_8P4R_5% PCH_GPIO8 AU2 BMBUSY/GPIO76 THERMTRIP V4
GPIO8 RCIN/GPIO82 EC_KBRST# 27
RP16 1 8 PCH_GPIO19 PCH_GPIO19 7 AM7 T4 SERIRQ SERIRQ 27,28
2 7 PCH_GPIO36 EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 1 2 R145
PCH_GPIO36 6 27 EC_LID_OUT# GPIO15 PCH_OPI_RCOMP
3 6 TP_INT# PCH_GPIO16 Y1 MISC AF20 @ T106 49.9_0402_1%
TP_INT# 28,8 GPIO16 RSVD
4 5 SERIRQ PCH_GPIO17 T3 AB21 @ T32
10K_0804_8P4R_5% PCH_GPIO24 AD5 GPIO17 RSVD
RP28 1 8 PCH_GPIO18 CPU_IDEN AN5 GPIO24
PCH_GPIO18 7 GPIO27
2 7 PCH_GPIO35 PCH_GPIO35 6 PCH_GPIO28 AD7
3 6 PCH_GPIO48 PCH_GPIO26 AN3 GPIO28
4 5 PCH_GPIO34 GPIO26 R6 PCH_GPIO83
PCH_GPIO34 6 GSPI0_CS/GPIO83
10K_0804_8P4R_5% PCH_GPIO56 AG6 L6 PCH_GPIO84
RP29 1 8 PCH_GPIO71 PCH_GPIO57 AP1 GPIO56 GSPI0_CLK/GPIO84 N6 PCH_GPIO85
2 7 PCH_GPIO16 PCH_GPIO58 AL4 GPIO57 GSPI0_MISO/GPIO85 L8 PCH_GPIO86 +3VS
3 6 EC_KBRST# PCH_GPIO59 AT5 GPIO58 GSPI0_MOSI/GPIO86 R7 PCH_GPIO87
4 5 PCH_GPIO37 PCH_GPIO44 AK4 GPIO59 GSPI1_CS/GPIO87 L5 PCH_GPIO88
PCH_GPIO37 6 GPIO44 GPIO GSPI1_CLK/GPIO88
10K_0804_8P4R_5% PCH_GPIO47 AB6 N7 PCH_GPIO89
PCH_GPIO48 U4 GPIO47 GSPI1_MISO/GPIO89 K2 PCH_GPIO90 R275 R274 R276 R277

2
RP30 8 1 PCH_GPIO67 DGPU_PRSNT# Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_GPIO91

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%

2.2K_0402_5%
7 2 PCH_GPIO65 TS_INT# P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_GPIO92
18 TS_INT# GPIO50 UART0_TXD/GPIO92
6 3 PCH_GPIO79 PCH_GPIO79 8 PCH_GPIO71 Y2 J2 PCH_GPIO93
5 4 PCH_GPIO64 PCH_GPIO13 AT3 HSIOPC/GPIO71 LPIO UART0_RTS/GPIO93 G1 PCH_GPIO94
10K_0804_8P4R_5% PCH_GPIO14 AH4 GPIO13 UART0_CTS/GPIO94 K4 PCH_GPIO0

1
RP31 8 1 PCH_GPIO84 PCH_GPIO25 AM4 GPIO14 UART1_RXD/GPIO0 G2 PCH_GPIO1
7 2 PCH_GPIO45 AG5 GPIO25 UART1_TXD/GPIO1 J3 PCH_GPIO2
6 3 PCH_GPIO3 PCH_GPIO46 AG3 GPIO45 UART1_RST/GPIO2 J4 PCH_GPIO3
5 4 PCH_GPIO89 GPIO46 UART1_CTS/GPIO3 F2 PCH_I2C0_SDA
C I2C0_SDA/GPIO4 PCH_I2C0_SDA 18 C
10K_0804_8P4R_5% PCH_GPIO9 AM3 F3 PCH_I2C0_SCL Touch Screen
GPIO9 I2C0_SCL/GPIO5 PCH_I2C0_SCL 18
RP32 8 1 PCH_GPIO17 PCH_GPIO10 AM2 G4 PCH_I2C1_SDA
GPIO10 I2C1_SDA/GPIO6 PCH_I2C1_SDA 28
7 2 PCH_GPIO23 PCH_GPIO23 7 DEVSLP0 P2 F1 PCH_I2C1_SCL Touch Pad
25,8 DEVSLP0 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PCH_I2C1_SCL 28
6 3 PCH_GPIO76 PCH_GPIO70 C4 E3 PCH_GPIO64
5 4 PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PCH_GPIO65
10K_0804_8P4R_5% EC_SMI#_SCI# N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66
27 EC_SMI#_SCI# DEVSLP2/GPIO39 SDIO_D0/GPIO66
PCH_SPKR V2 E4 PCH_GPIO67 for PVT 1/10 modify
29 PCH_SPKR SPKR/GPIO81 SDIO_D1/GPIO67
R216 1 2 PCH_GPIO70 C3 PCH_GPIO68
SDIO_D2/GPIO68 E2 PCH_GPIO69
+3VALW_PCH 10K_0402_5% SDIO_D3/GPIO69
10 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
RP34 1 8 PCH_GPIO10 @
2 7 PCH_GPIO11
PCH_GPIO11 7
3 6 PCH_GPIO57
4 5 PCH_GPIO13
10K_0804_8P4R_5%
RP35 1 8 USB_OC1#
USB_OC1# 10
2 7 PCH_GPIO8
3 6 PCH_GPIO73
PCH_GPIO73 7
4 5 SUSWARN#
SUSWARN# 8
10K_0804_8P4R_5%
RP37 1 8 PCH_GPIO46
2 7 PCH_GPIO14
3 6 PCH_GPIO42 PCH_GPIO42 10 +3VALW_PCH +3VS
4 5 PCH_GPIO60 PCH_GPIO60 7
10K_0804_8P4R_5% R269 1 @ 2 1K_0402_5% PCH_SPKR
RP38 1 8 PCH_GPIO28 R247 1 @ 2 10K_0402_5% EC_LID_OUT#
2 7 PCH_GPIO47
3 6 PCH_GPIO45
4 5 PCH_GPIO24 GPIO15 : TLS Confidentiality SPKR / GPIO81 : NO REBOOT
10K_0804_8P4R_5%
RP39 1 8 PCH_GPIO43
PCH_GPIO43 10
B 2 7 PCH_GPIO59 1: Intel ME TLS with confidentiality 1: ENABLED B
3 6 PCH_GPIO25
4 5 PCH_GPIO58 0: Intel ME TLS with no confidentiality 0: DISABLED (Have internal PD)
RP40 1 8
10K_0804_8P4R_5%
USB_OC0#
USB_OC0# 10,26
* (Have internal PD)
*
2 7 PCH_GPIO56
3 6 PCH_GPIO44
4 5 PCH_GPIO9
10K_0804_8P4R_5%

+3VS
PCH_GPIO66 R270 1 @ 2 1K_0402_5%
PCH_GPIO86 R272 1 @ 2 1K_0402_5%
+3VS R273 1 2 1K_0402_5%
1

R306 GSPI0_MOSI / GPIO86 : Boot BIOS Strap SDIO_D0 / GPIO66 : Top-Block Swap Override
10K_0402_5%

1: ENABLED 1: ENABLED
2

DGPU_PRSNT#
GPIO49 0: SPI ROM (Have internal PD) 0: DISABLED (Have internal PD)
DGPU_PRSNT# * *
2

R219
10K_0402_5%
DIS,Optimus 0
@
UMA 1
1

+3VALW_PCH +3VALW_PCH
A A
1

R311 R312
10K_0402_5% 10K_0402_5%
BW@
2

PCH_GPIO26
GPIO26 CPU_IDEN
GPIO27
VGA INFO CPU INFO Security Classification Compal Secret Data Compal Electronics, Inc.
2

R220 R221 2013/10/30 2014/10/30


10K_0402_5%
N15V-GL 0 10K_0402_5%
Haswell 0 Issued Date Deciphered Date Title
BDW MCP(6/11) GPIO,LPIO
@ HW@
N15V-GM 1 Boradwell 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1

Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 9 of 44
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E
U1K

F10 AN8 USB20_N0


E10 PERN5_L0
PERP5_L0
USB2N0
USB2P0
AM8 USB20_P0
USB20_N0
USB20_P0
26
26
USB2 Port 0 (USB3.0 P0)
C23 AR7 USB20_N1
C22 PETN5_L0
PETP5_L0
USB2N1
USB2P1
AT7 USB20_P1
USB20_N1
USB20_P1
26
26
USB2 Port 1
F8 AR8 USB20_N2
E8 PERN5_L1
PERP5_L1
USB2N2
USB2P2
AP8 USB20_P2
USB20_N2
USB20_P2
26
26
USB2 Port 2
B23 AR10
A23 PETN5_L1 USB2N3 AT10
PETP5_L1 USB2P3
H10 AM15 USB20_N4
G10 PERN5_L2
PERP5_L2
USB2N4
USB2P4
AL15 USB20_P4
USB20_N4
USB20_P4
24
24
Mini Card(WLAN+BT)
B21 AM13 USB20_N5
C21 PETN5_L2
PETP5_L2
USB2N5
USB2P5
AN13 USB20_P5
USB20_N5
USB20_P5
18
18
Touch Screen
E6 AP11 USB20_N6
F6 PERN5_L3
PERP5_L3
USB2N6
USB2P6
AN11 USB20_P6
USB20_N6
USB20_P6
18
18
Camera
B22 AR13 USB20_N7
A21 PETN5_L3
PETP5_L3
USB2N7
USB2P7
AP13 USB20_P7
USB20_N7
USB20_P7
26
26
Finger Print
22 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_N3 G11
C PCIE_PRX_DTX_P3 F11 PERN3 G20 C
22 PCIE_PRX_DTX_P3 PERP3 USB3RN1 PCH_USB3_RX0_N 26
H20
PCIE LAN C155 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3.0 P1 USB3RP1 PCH_USB3_RX0_P 26
22
22
PCIE_PTX_C_DRX_N3
PCIE_PTX_C_DRX_P3
C160 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3
PETP3
PCIe USB
USB3TN1
C33
PCH_USB3_TX0_N 26
USB3 Port 0
B34
USB3TP1 PCH_USB3_TX0_P 26
24 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_N4 F13
PCIE_PRX_DTX_P4 G13 PERN4 E18
24 PCIE_PRX_DTX_P4 PERP4 USB3RN2 F18
WLAN 24 PCIE_PTX_C_DRX_N4
C156 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N4 B29
PETN4
USB3.0 P2 USB3RP2
C157 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P4 A29 B33
24 PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 A33
G17 USB3TP2
F17 PERN1/USB3RN3
PERP1/USB3RP3
C30 USB3.0 P3 / PCIE P1
C31 PETN1/USB3TN3 AJ10 USBRBIAS R154 1 2 22.6_0402_1%
PETP1/USB3TP3 USBRBIAS CAD note:
AJ11
F15 USBRBIAS AN10 @ T35 Route single-end 50-ohms and max 450-mils length.
G15 PERN2/USB3RN4 RSVD AM10 @ T36 Recommended minimum spacing to other signal traces is 15 mils
PERP2/USB3RP4 USB3.0 P4 / PCIE P2 RSVD
B31
A31 PETN2/USB3TN4
PETP2/USB3TP4 AL3 USB_OC0#
OC0/GPIO40 USB_OC0# 26,9
AT1 USB_OC1#
+1.05VS_AUSB3PLL OC1/GPIO41 USB_OC1# 9
AH2 PCH_GPIO42
OC2/GPIO42 PCH_GPIO42 9
T33 @ E15 AV3 PCH_GPIO43
RSVD OC3/GPIO43 PCH_GPIO43 9
T34 @ E13
R232 1 2 3.01K_0402_1% PCIE_RCOMP A27 RSVD
R155 1 @ 2 0_0603_5% PCIE_IREF B27 PCIE_RCOMP
PCIE_IREF
Trace width=12~15 mil, Spcing=12 mils
Max trace length= 500 mil 11 OF 19 Rev1p2
B HASWELL-MCP-E-ULT_BGA1168 B
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(7/11) PCIE,USB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 10 of 44
5 4 3 2 1
5 4 3 2 1

+1.35V +1.35V_CPU

@ J6
1 2
D
+CPU_CORE D
HASWELL_MCP_E
JUMP_43X118 U1L

Shark Bay ULT have internal gate for VDDQ T37 @ L59 C36
+1.35V_CPU T38 @ J58 RSVD VCC C40
RSVD VCC C44
AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
AJ37 VDDQ VCC E23
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
+3VS AR48 VDDQ VCC E29
+1.05VS_VTT AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
1

+3VALW_PCH AY44 VDDQ VCC E35


VDDQ VCC

1
R422 +CPU_CORE AY50 E37
100K_0402_5% U16 R309 VDDQ VCC E39
@ 1 5 10K_0402_5% F59 VCC E41
NC VCC R166 T39 @ N58 VCC VCC E43
2

2 0_0402_5% +VCCIO_OUT T40 @ AC58 RSVD VCC E45


27,8 VCCST_PG_EC

2
A 4 VCCST_PG_EC_R 1 @ 2 +1.05VS_VTT RSVD VCC E47
Y VCCST_PWRGD 27,37 VCC
3 VCC_SENSE_R E63 E49
GND T41 @ AB23 VCC_SENSE VCC E51
74AUP1G07GW_TSSOP5 2 R164 1 A59 RSVD VCC E53
@ 0_0603_5% E20 VCCIO_OUT VCC E55
+VCCIOA_OUT VCCIOA_OUT VCC
T42 @ AD23 E57
T43 @ AA23 RSVD VCC F24
T44 @ AE59 RSVD VCC F28
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
0_0402_5% 1 @ 2 R165 H_CPU_SVIDCLK N63 VIDALERT VCC F40
39 VR_SVID_CLK VIDSCLK VCC
VIDSOUT L63 F44
+1.05VS_VTT VCCST_PG_EC_R B59 VIDSOUT HSW ULT POWER VCC F48
C 0_0402_5% 1 @ 2 R167 PCH_VR_EN F60 VCCST_PWRGD VCC F52 C
39 VR_ON VR_EN VCC
39,8 VGATE 0_0402_5% 1 @ 2 R168 VR_READY C59 F56
@ C167 VR_READY VCC G23

2
1 2 0.1U_0402_16V4Z D63 VCC G25
R169 CPU_PWR_DEBUG H59 VSS VCC G27
SVID ALERT 150_0402_1% Reserved Only P62 PWR_DEBUG
VSS
VCC
VCC
G29
@ T45 @ P60 G31
1 T46 @ P61 RSVD_TP VCC G33
+1.05VS_VTT T47 @ N59 RSVD_TP VCC G35
Place the CPU RSVD_TP VCC
CPU_PWR_DEBUG T48 @ N61 G37
resistors close to CPU T98 @ T59 RSVD_TP VCC G39
1

T142 @ AD60 RSVD VCC G41


RSVD VCC
2

R171 T143 @ AD59 G43


R170 T144 @ AA59 RSVD VCC G45
75_0402_1%
T141 @ AE60 RSVD VCC G47
10K_0402_5%
R172 T140 @ AC59 RSVD VCC G49
@
2

43_0402_1% T147 @ AG58 RSVD VCC G51


1

2 1 H_CPU_SVIDALRT# +1.05VS_VTT T145 @ U59 RSVD VCC G53


39 VR_ALERT# RSVD VCC
T146 @ V59 G55
RSVD VCC G57
AC22 VCC H23
+CPU_CORE AE22 VCCST VCC J23
AE23 VCCST VCC K23
SVID DATA VCCST VCC
VCC
K57
AB57 L22
+1.05VS_VTT AD57 VCC VCC M23
AG57 VCC VCC M57
Place the CPU VCC VCC
C24 P57
resistors close to CPU C28 VCC VCC U57
VCC VCC
1

C32 W57
R173 VCC VCC
130_0402_1% 12 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
B R174 @ B
2

0_0402_5%
2 @ 1 VIDSOUT +1.05VS_VTT
39 VR_SVID_DATA
+1.35V_CPU

+CPU_CORE
VDDQ DECOUPLING
1U_0402_6.3V6K

@
22U_0805_6.3V6M

1 1
1

C7

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
EMC@ EMC@ 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
C6

R177 1 1 1 1 1 1 1 1 1 1

C8

C9

C10

C11
100_0402_1% Note: 0 ohm PLACED CLOSE TO CPU @ @ + C18
2 2

C12

C13

C14

C15

C16

C17
330U_2.5V_M
2

VCC_SENSE_R 2 @ 1 R178 2 2 2 2 2 2 2 2 2 2 2
VCC_SENSE 39
0_0402_5%

13 VSS_SENSE_R 2 @ 1 R235
VSS_SENSE 39
0_0402_5%
1

+1.35V : 470UF/2V/7343 *2
R233
100_0402_1%
10UF/6.3V/0603 * 6
2.2UF/6.3V/0402 * 4
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(8/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 11 of 44
5 4 3 2 1
5 4 3 2 1

D D

+1.05VS_VTT
+1.05VS_VTT HASWELL_MCP_E
U1M

K9 +3VALW_PCH +RTCVCC
L10 VCCHSIO

1U_0402_6.3V6K
1 VCCHSIO
M9 C30 1 2 1U_0402_6.3V6K

1U_0402_6.3V6K
C408 + C31 N8 VCCHSIO mPHY AH11
P9 VCC1_05 RTC VCCSUS3_3 AG10

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 VCC1_05 VCCRTC +RTCVCC
220U_6.3V_M +1.05VS_AUSB3PLL B18 AE7 +VCCRTCEXT 1 2 1 1 1
2 VCCUSB3PLL DCPRTC

C21

C20
+1.05VS_ASATA3PLL B11 C54 0.1U_0402_16V4Z @ @
VCCSATA3PLL +3V_SPI

C52

C51

C50
1U_0402_6.3V6K
2 2 2
EMC@ 2 2 2
Y20 SPI Y8 C58 2 1 0.1U_0402_16V4Z
AA21 RSVD OPI VCCSPI @
Near PJ601 +1.05VS_APLLOPI VCCAPLL
Near K9 Near L10 Near M9 W21
VCCAPLL AG14
VCCASW +1.05VS_VTT
AG13
+3VALW_PCH VCCASW
+1.05VS_VTT +1.05VS_AUSB3PLL USB3
+1.05VS_VTT
HDA --> 3.3V or 1.5V T105 @ J13 @
Near B18 I2C --> 1.8V DCPSUS3 J11 C27 1 2 10U_0603_6.3V6M C2567 0.47U_0402_6.3V6K
C42 1 2 1U_0402_6.3V6K VCC1_05 H11 C33 1 2 1U_0402_6.3V6K 1 2
AXALIA/HDA VCC1_05 +3VALW_PCH
L1 1 2 C32 1 2 100U_1206_6.3V6M 2 1 C38 AH14 H15 C40 1 2 10U_0603_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% 1U_0402_6.3V6K VCCHDA VCC1_05 AE8 EMC@
VCC1_05 Broadwell only
Idc 1.2A Rdc 0.11ohm +/-30% AF22 1U_0402_6.3V6K
T116 @ AH13 VRM/USB2/AZALIA VCC1_05 AG19 +PCH_VCCDSW 1 @ 2+PCH_VCCDSW_R C41 1 2 Intel recommends a 0.47uF boot strap
+1.05VS_ASATA3PLL DCPSUS2 CORE DCPSUSBYP AG20 R209 0_0402_5% capacitor to be placed between V3.3DSW
C +3VALW_PCH DCPSUSBYP AE9 C
VCCASW +1.05VS_VTT and DcpSUSByp power rail
Near B11 C28 AF9 C36 1 2 22U_0805_6.3V6M
C46 1 2 1U_0402_6.3V6K Near AC9 2 1 22U_0805_6.3V6M AC9 VCCASW AG8 C37 1 2 1U_0402_6.3V6K to support in-rush current.
L2 1 2 C61 1 2 100U_1206_6.3V6M C59 @ AA9 VCCSUS3_3 VCCASW AD10 C43 @1 2 1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% Near AH10 2 1 0.1U_0402_16V4Z AH10 VCCSUS3_3 DCPSUS1 AD8
Idc 1.2A Rdc 0.11ohm +/-30% C29 V8 VCCDSW3_3 GPIO/LCC DCPSUS1
Near V8 2 1 22U_0805_6.3V6M W9 VCC3_3
+1.05VS_APLLOPI VCC3_3 J15
+3VS VCCTS1_5 +1.5VS
THERMAL SENSOR K14 +3VS
Near AA21 VCC3_3 K16 C55 1 2 0.1U_0402_16V4Z
C47 1 2 1U_0402_6.3V6K VCC3_3
L3 1 2 C22 1 2 100U_1206_6.3V6M
2.2UH_LQM2MPN2R2NG0L_30% +1.05VS_AXCK_DCB J18
Idc 1.2A Rdc 0.11ohm +/-30% K19 VCCCLK SDIO/PLSS U8
VCCCLK VCCSDIO +3VS
+1.05VS_AXCK_LCPLL A20 T9 C44 1 2 1U_0402_6.3V6K
J17 VCCACLKPLL VCCSDIO
+1.05VS_VTT VCCCLK
C57 R21
+1.05VS_VTT +1.05VS_AXCK_DCB Near J17 2 1 1U_0402_6.3V6K T21 VCCCLK LPT LP POWER C53 @1 2 1U_0402_6.3V6K
C56 T100 @ K18 VCCCLK SUS OSCILLATOR AB8 C25 @1 2 100U_1206_6.3V6M
Near J18 Near R21 2 1 1U_0402_6.3V6K T101 @ M20 RSVD DCPSUS4
C48 1 2 1U_0402_6.3V6K T102 @ V21 RSVD
L4 1 2 C23 1 2 100U_1206_6.3V6M AE20 RSVD AC20 @ T103
+3VALW_PCH VCCSUS3_3 RSVD
2.2UH_LQM2MPN2R2NG0L_30% AE21 AG16 +1.05VS_VTT
Idc 1.2A Rdc 0.11ohm +/-30% VCCSUS3_3 USB2 VCC1_05 AG17
VCC1_05 C45 1 2 1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
Near A20
C49 1 2 1U_0402_6.3V6K 13 OF 19 Rev1p2
L5 1 2 C24 1 2 100U_1206_6.3V6M HASWELL-MCP-E-ULT_BGA1168
2.2UH_LQM2MPN2R2NG0L_30% @
Idc 1.2A Rdc 0.11ohm +/-30%

B B

+3VALW TO +3VALW(PCH AUX Power)


Short J8 for PCH VCCSUS3.3
+3VALW J8 @ +3VALW_PCH
JUMP_43X39
1 2
1 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(9/11) Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 12 of 44
5 4 3 2 1
5 4 3 2 1

D D

HASWELL_MCP_E HASWELL_MCP_E
U1N U1O U1P HASWELL_MCP_E
H17
A11 AJ35 AP22 AV59 D33 VSS H57
A14 VSS VSS AJ39 AP23 VSS VSS AV8 D34 VSS VSS J10
A18 VSS VSS AJ41 AP26 VSS VSS AW16 D35 VSS VSS J22
A24 VSS VSS AJ43 AP29 VSS VSS AW24 D37 VSS VSS J59
A28 VSS VSS AJ45 AP3 VSS VSS AW33 D38 VSS VSS J63
A32 VSS VSS AJ47 AP31 VSS VSS AW35 D39 VSS VSS K1
A36 VSS VSS AJ50 AP38 VSS VSS AW37 D41 VSS VSS K12
A40 VSS VSS AJ52 AP39 VSS VSS AW4 D42 VSS VSS L13
A44 VSS VSS AJ54 AP48 VSS VSS AW40 D43 VSS VSS L15
A48 VSS VSS AJ56 AP52 VSS VSS AW42 D45 VSS VSS L17
A52 VSS VSS AJ58 AP54 VSS VSS AW44 D46 VSS VSS L18
A56 VSS VSS AJ60 AP57 VSS VSS AW47 D47 VSS VSS L20
AA1 VSS VSS AJ63 AR11 VSS VSS AW50 D49 VSS VSS L58
AA58 VSS VSS AK23 AR15 VSS VSS AW51 D5 VSS VSS L61
AB10 VSS VSS AK3 AR17 VSS VSS AW59 D50 VSS VSS L7
AB20 VSS VSS AK52 AR23 VSS VSS AW60 D51 VSS VSS M22
AB22 VSS VSS AL10 AR31 VSS VSS AY11 D53 VSS VSS N10
AB7 VSS VSS AL13 AR33 VSS VSS AY16 D54 VSS VSS N3
AC61 VSS VSS AL17 AR39 VSS VSS AY18 D55 VSS VSS P59
AD21 VSS VSS AL20 AR43 VSS VSS AY22 D57 VSS VSS P63
AD3 VSS VSS AL22 AR49 VSS VSS AY24 D59 VSS VSS R10
C AD63 VSS VSS AL23 AR5 VSS VSS AY26 D62 VSS VSS R22 C
AE10 VSS VSS AL26 AR52 VSS VSS AY30 D8 VSS VSS R8
AE5 VSS VSS AL29 AT13 VSS VSS AY33 E11 VSS VSS T1
AE58 VSS VSS AL31 AT35 VSS VSS AY4 E17 VSS VSS T58
AF11 VSS VSS AL33 AT37 VSS VSS AY51 F20 VSS VSS U20
AF12 VSS VSS AL36 AT40 VSS VSS AY53 F26 VSS VSS U22
AF14 VSS VSS AL39 AT42 VSS VSS AY57 F30 VSS VSS U61
AF15 VSS VSS AL40 AT43 VSS VSS AY59 F34 VSS VSS U9
AF17 VSS VSS AL45 AT46 VSS VSS AY6 F38 VSS VSS V10
AF18 VSS VSS AL46 AT49 VSS VSS B20 F42 VSS VSS V3
AG1 VSS VSS AL51 AT61 VSS VSS B24 F46 VSS VSS V7
AG11 VSS VSS AL52 AT62 VSS VSS B26 F50 VSS VSS W20
AG21 VSS VSS AL54 AT63 VSS VSS B28 F54 VSS VSS W22
AG23 VSS VSS AL57 AU1 VSS VSS B32 F58 VSS VSS Y10
AG60 VSS VSS AL60 AU16 VSS VSS B36 F61 VSS VSS Y59
AG61 VSS VSS AL61 AU18 VSS VSS B4 G18 VSS VSS Y63
AG62 VSS VSS AM1 AU20 VSS VSS B40 G22 VSS VSS
AG63 VSS VSS AM17 AU22 VSS VSS B44 G3 VSS
AH17 VSS VSS AM23 AU24 VSS VSS B48 G5 VSS V58
AH19 VSS VSS AM31 AU26 VSS VSS B52 G6 VSS VSS AH46
AH20 VSS VSS AM52 AU28 VSS VSS B56 G8 VSS VSS V23
AH22 VSS VSS AN17 AU30 VSS VSS B60 H13 VSS VSS E62
VSS VSS VSS VSS VSS VSS_SENSE VSS_SENSE_R 11
AH24 AN23 AU33 C11 AH16
AH28 VSS VSS AN31 AU51 VSS VSS C14 16 OF 19 Rev1p2 VSS
AH30 VSS VSS AN32 AU53 VSS VSS C18 HASWELL-MCP-E-ULT_BGA1168
AH32 VSS VSS AN35 AU55 VSS VSS C20
VSS VSS VSS VSS @
AH34 AN36 AU57 C25
AH36 VSS VSS AN39 AU59 VSS VSS C27
AH38 VSS VSS AN40 AV14 VSS VSS C38
AH40 VSS VSS AN42 AV16 VSS VSS C39
AH42 VSS VSS AN43 AV20 VSS VSS C57
AH44 VSS VSS AN45 AV24 VSS VSS D12
AH49 VSS VSS AN46 AV28 VSS VSS D14
B AH51 VSS VSS AN48 AV33 VSS VSS D18 B
AH53 VSS VSS AN49 AV34 VSS VSS D2
AH55 VSS VSS AN51 AV36 VSS VSS D21
AH57 VSS VSS AN52 AV39 VSS VSS D23
AJ13 VSS VSS AN60 AV41 VSS VSS D25
AJ14 VSS VSS AN63 AV43 VSS VSS D26
AJ23 VSS VSS AN7 AV46 VSS VSS D27
AJ25 VSS VSS AP10 AV49 VSS VSS D29
AJ27 VSS VSS AP17 AV51 VSS VSS D30
AJ29 VSS VSS AP20 AV55 VSS VSS D31
VSS VSS VSS 15 OF 19 Rev1p2 VSS
HASWELL-MCP-E-ULT_BGA1168
@
14 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date HSW MCP(10/11) GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 13 of 44
5 4 3 2 1
5 4 3 2 1

D D
HASWELL_MCP_E
U1R
HASWELL_MCP_E
U1Q
T51 @ AT2 N23 @ T64
T52 @ AU44 RSVD RSVD R23 @ T65
DC_TEST_AY2_AW2 AY2 A3 DC_TEST_A3_B3 T53 @ AV44 RSVD RSVD T23 @ T66
DC_TEST_AY3_AW3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 @ T58 T54 @ D15 RSVD RSVD U10 @ T67
T49 @ AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 RSVD RSVD
DC_TEST_AY61_AW61 AY61 DAISY_CHAIN_NCTF_AY60 A60 @ T59
DC_TEST_AY62_AW62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61 T55 @ F22 AL1 @ T68
T50 @ B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62 @ T60 T56 @ H22 RSVD RSVD AM11 @ T69
DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1 @ T61 T57 @ J21 RSVD RSVD AP7 @ T70
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1 @ T62 RSVD RSVD AU10 @ T71
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW2 RSVD AU15 @ T72
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW3 RSVD AW14 @ T73
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61 DC_TEST_AY61_AW61 RSVD AY14 @ T74
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62 DC_TEST_AY62_AW62 RSVD
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63 @ T63
17 OF 19 Rev1p2DAISY_CHAIN_NCTF_AW63 18 OF 19 Rev1p2
HASWELL-MCP-E-ULT_BGA1168 HASWELL-MCP-E-ULT_BGA1168
@ @

U1S HASWELL_MCP_E

C C
T104 @ CFG0 AC60 AV63 @ T75
T107 @ CFG1 AC62 CFG0
CFG1
RSVD_TP
RSVD_TP
AU63 @ T76 CFG Straps for Processor
T108 @ CFG2 AC63
T166 @ CFG3 AA63 CFG2
T167 @ CFG4 AA60 CFG3 C63 @ T77
T168 @ CFG5 Y62 CFG4 RSVD_TP C62 @ T78
T169 @ CFG6 Y61 CFG5 RSVD_TP B43 @ T79 CFG3
T170 @ CFG7 Y60 CFG6 RSVD
CFG7

1
T171 @ CFG8 V62 A51 @ T80
T172 @ CFG9 V61 CFG8 RSVD_TP B51 @ T81 R224
T182 @ CFG10 V60 CFG9 RSVD_TP 1K_0402_5%
T181 @ CFG11 U60 CFG10 L60 @ T82 @
T180 @ CFG12 T63 CFG11 RESERVED RSVD_TP

2
T179 @ CFG13 T62 CFG12 N60 @ T83
T178 @ CFG14 T61 CFG13 RSVD
T177 @ CFG15 T60 CFG14 W23 @ T84
CFG15 RSVD Y22 @ T85
T176 @ CFG16 AA62 RSVD AY15 OPI_COMP
T175 @ CFG18 U63 CFG16 PROC_OPI_RCOMP
T174 @ CFG17 AA61 CFG18 AV62 @ T86
CFG17 RSVD Physical Debug Enable (DFX Privacy)
T173 @ CFG19 U62 D58 @ T87
CFG19 RSVD
CFG_RCOMP V63 P22 1: DISABLED
CFG_RCOMP VSS N21
VSS CFG3
T90 @ A5 0: ENABLED; SET DFX ENABLED BIT
RSVD P20 @ T88
T91 @ E1 RSVD R20 @ T89 IN DEBUG INTERFACE MSR
T92 @ D1 RSVD RSVD
T93 @ J20 RSVD
T94 @ H18 RSVD CFG4
TD_IREF B12 RSVD
TD_IREF

1
B 19 OF 19 Rev1p2 R225 B
HASWELL-MCP-E-ULT_BGA1168 1K_0402_5%
@

2
2 1 CFG_RCOMP
R222 49.9_0402_1%
2 1 OPI_COMP
R223 49.9_0402_1% Display Port Presence Strap
2 1 TD_IREF
R226 8.2K_0402_5%
1 : Disabled; No Physical Display Port
CFG4 attached to Embedded Display Port

0 : Enabled; An external Display Port device is


connected to the Embedded Display Port

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


2013/10/30 2014/10/30 Title
Issued Date Deciphered Date BDW MCP(11/11) RSVD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 14 of 44
5 4 3 2 1
A B C D E

+1.35V
+1.35V +1.35V +1.35V
JDIMM1

1
+V_DDR_REFA 1 2
VREF_DQ VSS1 +5VALW +5VS

0.1U_0402_16V4Z
3 4 DDR_A_D9
VSS2 DQ4

C34
R54 DDR_A_D13 5 6 DDR_A_D12 1
R293 1.8K_0402_1% DDR_A_D8 7 DQ0 DQ5 8 @
2_0402_1% 9 DQ1 VSS3 10 DDR_A_DQS#1 R187 1 2 SA_ODT0

2
1 2 11 VSS4 DQS#0 12 DDR_A_DQS1 66.5_0402_1%
5 SA_DIMM_VREFDQ DM0 DQS0 2

2.2U_0402_6.3V6M
1 13 14

2
@ DDR_A_D14 15 VSS5 VSS6 16 DDR_A_D15
1 1 DQ2 DQ6 +1.35V

C105

0.1U_0402_16V4Z
C106
C158 @ DDR_A_D10 17 18 DDR_A_D11 R186 R191 R188 1 2 SA_ODT1
0.022U_0402_25V7K R185 19 DQ3 DQ7 20 U45 66.5_0402_1%
VSS7 VSS8 100K_0402_5% 100K_0402_5%
2 1.8K_0402_1% DDR_A_D29 21 22 DDR_A_D25 1 5 Q18
DQ8 DQ12 NC VCC @

1
2 2 DDR_A_D28 23 24 DDR_A_D24 LBSS138LT1G_SOT-23-3

1
25 DQ9 DQ13 26 2 D R189 1 2 SB_ODT0
1 VSS9 VSS10 4 DDR_PG_CTRL A SB_ODT0 16 1
R176 DDR_A_DQS#3 27 28 4 2 66.5_0402_1%
24.9_0402_1% DDR_A_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST# 3 Y G
DQS1 RESET# DIMM_DRAMRST# 16,4 GND
@ 31 32 S
2

3
DDR_A_D30 33 VSS11 VSS12 34 DDR_A_D27 74AUP1G07GW_TSSOP5 M_A_B_DIMM_ODT R190 1 2 SB_ODT1
DQ10 DQ14 SB_ODT1 16
DDR_A_D31 35 36 DDR_A_D26 66.5_0402_1%
37 DQ11 DQ15 38
DDR_A_D44 39 VSS13 VSS14 40 DDR_A_D45
DQ16 DQ20 DDR_VTT_PG_CTRL 36
DDR_A_D41 41 42 DDR_A_D40
43 DQ17 DQ21 44
VSS15 VSS16 DDR_A_DQS#[0..7] 5
DDR_A_DQS#5 45 46 1 1
DDR_A_DQS5 47 DQS#2 DM2 48 EMC@ XEMC@
DQS2 VSS17 DDR_A_DQS[0..7] 5

100P_0402_50V8J
C35

100P_0402_50V8J
C68
49 50 DDR_A_D42
DDR_A_D43 51 VSS18 DQ22 52 DDR_A_D46
DQ18 DQ23 DDR_A_D[0..63] 5 2 2
DDR_A_D47 53 54
55 DQ19 VSS19 56 DDR_A_D52
All VREF traces should DDR_A_D51 57 VSS20 DQ28 58 DDR_A_D53
DDR_A_MA[0..15] 5
Layout Note: have 10 mil trace width DDR_A_D50 59 DQ24 DQ29 60
Place near JDIMM1 61 DQ25 VSS21 62 DDR_A_DQS#6
+1.35V 63 VSS22 DQS#3 64 DDR_A_DQS6
65 DM3 DQS3 66 U45 side Pr511 side
DDR_A_D49 67 VSS23 VSS24 68 DDR_A_D54 for PVT 1/13 modify
DDR_A_D48 69 DQ26 DQ30 70 DDR_A_D55
DQ27 DQ31
1U_0402_6.3V6K
C107

1U_0402_6.3V6K
C108

1U_0402_6.3V6K
C109

1U_0402_6.3V6K
C110

71 72
VSS25 VSS26
1 1 1 1
@ @

5 DDRA_CKE0_DIMMA DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA DDRA_CKE1_DIMMA 5


2 2 2 2 75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
5 DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
2 87 A9 A7 88 2
+1.35V DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
A3 A2
10U_0603_6.3V6M
C111

10U_0603_6.3V6M
C112

10U_0603_6.3V6M
C113

10U_0603_6.3V6M
C114

DDR_A_MA1 97 98 DDR_A_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SA_CLK_DDR0 SA_CLK_DDR0 101 102 SA_CLK_DDR1 SA_CLK_DDR1 5
SA_CLK_DDR#0 103 CK0 CK1 104 SA_CLK_DDR#1
5 SA_CLK_DDR#0 CK0# CK1# SA_CLK_DDR#1 5
105 106
2 2 2 2 DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 5 +1.35V
5 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# DDR_A_RAS# 5
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
5 DDR_A_WE# WE# S0# DDRA_CS0_DIMMA# 5

1
5 DDR_A_CAS# DDR_A_CAS# 115 116 SA_ODT0
117 CAS# ODT0 118 R56
DDR_A_MA13 119 VDD15 VDD16 120 SA_ODT1 1.8K_0402_1%
DDRA_CS1_DIMMA# 121 A13 ODT1 122
+1.35V 5 DDRA_CS1_DIMMA# S1# NC2
123 124 R296

2
125 VDD17 VDD18 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA 5
127 128 2_0402_1% 1

1
EMC@ EMC@ DDR_A_D0 129 VSS27 VSS28 130 DDR_A_D5 @
DQ32 DQ36
10U_0603_6.3V6M
C115

10U_0603_6.3V6M
C116

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C161

2.2U_0402_6.3V6M

0.1U_0402_16V4Z
1 DDR_A_D1 131 132 DDR_A_D4 C162
@ 133 DQ33 DQ37 134 R295 0.022U_0402_25V7K
1 1 1 1 VSS29 VSS30 1 1
2

C119

C120
+ C118 DDR_A_DQS#0 135 136 @ 1.8K_0402_1%
DQS#4 DM4

1
330U_2.5V_M DDR_A_DQS0 137 138

2
139 DQS4 VSS31 140 DDR_A_D3
2 2 2 2 2 DDR_A_D2 141 VSS32 DQ38 142 DDR_A_D7 2 2 @ R294
SF000002Z00 DDR_A_D6 143 DQ34 DQ39 144 24.9_0402_1%
330U 2.5V H4.2 145 DQ35 VSS33 146 DDR_A_D18

2
DDR_A_D21 147 VSS34 DQ44 148 DDR_A_D19
17mohm OSCON DDR_A_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#2
3 153 VSS36 DQS#5 154 DDR_A_DQS2 3
155 DM5 DQS5 156
DDR_A_D17 157 VSS37 VSS38 158 DDR_A_D22
DDR_A_D16 159 DQ42 DQ46 160 DDR_A_D23
+0.675VS DQ43 DQ47 +VREF_CA 16
161 162
DDR_A_D36 163 VSS39 VSS40 164 DDR_A_D37
DDR_A_D33 165 DQ48 DQ52 166 DDR_A_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C121

1U_0402_6.3V6K
C122

1U_0402_6.3V6K
C123

1U_0402_6.3V6K
C124

DDR_A_DQS#4 169 170


DDR_A_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43
@ @ 173 174 DDR_A_D35
DDR_A_D34 175 VSS44 DQ54 176 DDR_A_D39
DDR_A_D38 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_A_D63
DDR_A_D62 181 VSS46 DQ60 182 DDR_A_D59
DDR_A_D58 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS#7 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D60 191 VSS49 VSS50 192 DDR_A_D56
DDR_A_D61 193 DQ58 DQ62 194 DDR_A_D57
Layout Note: 195 DQ59 DQ63 196
Place near JDIMM1.203,204 197 VSS51 VSS52 198
199 SA0 EVENT# 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 16,30,7
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 16,30,7
+0.675VS 203 204 +0.675VS
VTT1 VTT2
2.2U_0402_6.3V6M

205 206
2

G1 G2
1 1
Channel A
0.1U_0402_16V4Z
C125

C126

0_0402_5%
R211

0_0402_5%
R212

@ FOX_AS0A621-U4R6-7H
@ @ CONN@
2 2
SP07000J510
1

4 4

<Address: SA1:SA0=00>

DIMM_1 H:4mm
DIS for Standard type Security Classification
2013/10/30
Compal Secret Data
2014/10/30 Title
Compal Electronics, Inc.
UMA for Reverse type
Issued Date Deciphered Date DDRIII DIMMA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 15 of 44
A B C D E
A B C D E

+1.35V
+1.35V +1.35V
JDIMM2
DDR_B_DQS#[0..7] 5

1
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDR_B_D12
VSS2 DQ4 DDR_B_DQS[0..7] 5
R57 DDR_B_D8 5 6 DDR_B_D9
R297 1.8K_0402_1% DDR_B_D14 7 DQ0 DQ5 8
DQ1 VSS3 DDR_B_D[0..63] 5
2_0402_1% 9 10 DDR_B_DQS#1

2
1 2 11 VSS4 DQS#0 12 DDR_B_DQS1
5 SB_DIMM_VREFDQ DM0 DQS0 DDR_B_MA[0..15] 5

2.2U_0402_6.3V6M
1 13 14

1
@ DDR_B_D10 15 VSS5 VSS6 16 DDR_B_D13
1 1 DQ2 DQ6

C127

0.1U_0402_16V4Z
C128
C159 @ DDR_B_D11 17 18 DDR_B_D15
0.022U_0402_25V7K R213 19 DQ3 DQ7 20
2 1.8K_0402_1% DDR_B_D28 21 VSS7 VSS8 22 DDR_B_D25
DQ8 DQ12

1
2 2 DDR_B_D29 23 24 DDR_B_D24

2
25 DQ9 DQ13 26
1 VSS9 VSS10 1
R179 DDR_B_DQS#3 27 28
24.9_0402_1% DDR_B_DQS3 29 DQS#1 DM1 30 DIMM_DRAMRST#
DQS1 RESET# DIMM_DRAMRST# 15,4
@ 31 32
2

DDR_B_D26 33 VSS11 VSS12 34 DDR_B_D30


DDR_B_D27 35 DQ10 DQ14 36 DDR_B_D31
37 DQ11 DQ15 38
DDR_B_D40 39 VSS13 VSS14 40 DDR_B_D45
DDR_B_D41 41 DQ16 DQ20 42 DDR_B_D44
43 DQ17 DQ21 44
DDR_B_DQS#5 45 VSS15 VSS16 46
DDR_B_DQS5 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D47
DDR_B_D46 51 VSS18 DQ22 52 DDR_B_D43
DDR_B_D42 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D61
All VREF traces should DDR_B_D56 57 VSS20 DQ28 58 DDR_B_D60
Layout Note: have 10 mil trace width DDR_B_D57 59 DQ24 DQ29 60
Place near JDIMM2 61 DQ25 VSS21 62 DDR_B_DQS#7
+1.35V 63 VSS22 DQS#3 64 DDR_B_DQS7
65 DM3 DQS3 66
DDR_B_D59 67 VSS23 VSS24 68 DDR_B_D63
DDR_B_D58 69 DQ26 DQ30 70 DDR_B_D62
DQ27 DQ31
1U_0402_6.3V6K
C129

1U_0402_6.3V6K
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

71 72
VSS25 VSS26
1 1 1 1
@ @

5 DDRB_CKE0_DIMMB DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB DDRB_CKE1_DIMMB 5


2 2 2 2 75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
5 DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
2 87 A9 A7 88 2
+1.35V DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
A3 A2
10U_0603_6.3V6M
C133

10U_0603_6.3V6M
C134

10U_0603_6.3V6M
C135

10U_0603_6.3V6M
C136

DDR_B_MA1 97 98 DDR_B_MA0
99 A1 A0 100
1 1 1 1 VDD9 VDD10
5 SB_CLK_DDR0 SB_CLK_DDR0 101 102 SB_CLK_DDR1 SB_CLK_DDR1 5
SB_CLK_DDR#0 103 CK0 CK1 104 SB_CLK_DDR#1
5 SB_CLK_DDR#0 CK0# CK1# SB_CLK_DDR#1 5
105 106
2 2 2 2 DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 5
5 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS# DDR_B_RAS# 5
111 BA0 RAS# 112
DDR_B_WE# 113 VDD13 VDD14 114 DDRB_CS0_DIMMB#
5 DDR_B_WE# WE# S0# DDRB_CS0_DIMMB# 5
5 DDR_B_CAS# DDR_B_CAS# 115 116 SB_ODT0 SB_ODT0 15
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 SB_ODT1
A13 ODT1 SB_ODT1 15
5 DDRB_CS1_DIMMB# DDRB_CS1_DIMMB# 121 122
+1.35V 123 S1# NC2 124
125 VDD17 VDD18 126 +VREF_CA
NCTEST VREF_CA +VREF_CA 15
127 128
DDR_B_D4 129 VSS27 VSS28 130 DDR_B_D5
DQ32 DQ36
10U_0603_6.3V6M
C137

10U_0603_6.3V6M
C138

10U_0603_6.3V6M
C139

2.2U_0402_6.3V6M
DDR_B_D1 131 132 DDR_B_D0
133 DQ33 DQ37 134
1 1 1 VSS29 VSS30 1 1

C141

0.1U_0402_16V4Z
C142
DDR_B_DQS#0 135 136 @
DDR_B_DQS0 137 DQS#4 DM4 138
@ 139 DQS4 VSS31 140 DDR_B_D2
2 2 2 DDR_B_D3 141 VSS32 DQ38 142 DDR_B_D6 2 2
DDR_B_D7 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D16
DDR_B_D21 147 VSS34 DQ44 148 DDR_B_D17
DDR_B_D20 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#2
3 153 VSS36 DQS#5 154 DDR_B_DQS2 3
155 DM5 DQS5 156
DDR_B_D22 157 VSS37 VSS38 158 DDR_B_D19
DDR_B_D23 159 DQ42 DQ46 160 DDR_B_D18
+0.675VS 161 DQ43 DQ47 162
DDR_B_D36 163 VSS39 VSS40 164 DDR_B_D37
DDR_B_D33 165 DQ48 DQ52 166 DDR_B_D32
167 DQ49 DQ53 168
VSS41 VSS42
1U_0402_6.3V6K
C143

1U_0402_6.3V6K
C144

1U_0402_6.3V6K
C145

1U_0402_6.3V6K
C146

DDR_B_DQS#4 169 170


DDR_B_DQS4 171 DQS#6 DM6 172
1 1 1 1 DQS6 VSS43
@ @ 173 174 DDR_B_D34
DDR_B_D35 175 VSS44 DQ54 176 DDR_B_D38
DDR_B_D39 177 DQ50 DQ55 178
2 2 2 2 179 DQ51 VSS45 180 DDR_B_D51
DDR_B_D52 181 VSS46 DQ60 182 DDR_B_D55
+3VS DDR_B_D49 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#6
187 VSS48 DQS#7 188 DDR_B_DQS6
2

189 DM7 DQS7 190


R229 DDR_B_D48 191 VSS49 VSS50 192 DDR_B_D54
10K_0402_5% DDR_B_D53 193 DQ58 DQ62 194 DDR_B_D50
Layout Note: 195 DQ59 DQ63 196
Place near JDIMM2.203,204 197 VSS51 VSS52 198
1

199 SA0 EVENT# 200 D_CK_SDATA


+3VS VDDSPD SDA D_CK_SDATA 15,30,7
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 15,30,7
+0.675VS 203 204 +0.675VS
VTT1 VTT2
2.2U_0402_6.3V6M

205 206
2

G1 G2
1 1
Channel B
0.1U_0402_16V4Z
C147

C148

0_0402_5%
R231

@ FOX_AS0A621-U4R6-7H
@ CONN@
2 2
SP07000J510
1

4 4

<Address: SA1:SA0=10>

DIMM_2 H:4mm
DIS for Standard type Security Classification
2013/10/30
Compal Secret Data
2014/10/30 Title
Compal Electronics, Inc.
UMA for Reverse type
Issued Date Deciphered Date DDRIII DIMMB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 16 of 44
A B C D E
5 4 3 2 1

LVDS Translator - RTD2132R

D D

+3VS_TL
+3VS +3VS_TL U50 LVDS@
LVDS@ 19 TXOUT_CLK+ TXOUT_CLK+ 18
L63 2 1 DP_V33 TXEC+
30mil 30mil 40mil 3 DP_V33 TXEC-
20 TXOUT_CLK- TXOUT_CLK- 18
2 1 HCB2012KF-221T30_0805
R928 LVDS@ 0_0603_5% LVDS@ 60mil13 SWR_VDD TXE2+
21 TXOUT2+ TXOUT2+ 18
+1.2V_TL

Power
L73 2 1 SWR_VDD 18 22 TXOUT2-

LVDS
+3VS PVCC TXE2- TXOUT2- 18
HCB2012KF-221T30_0805
LVDS@ L6 1 2 +1.2V_TL_OUT 60mil12 23 TXOUT1+ TXOUT1+ 18
4.7UH_PG031B-4R7MS_1.1A_20% 11 SWR_LX TXE1+ 24 TXOUT1-
60mil 27 SWR_VCCK TXE1- TXOUT1- 18
+1.2V_TL VCCK
7 25 TXOUT0+ TXOUT0+ 18
DP_V12 TXE0+ 26 TXOUT0-
60mil TXE0- TXOUT0- 18

Close to Pin3
DP_V33 RTD2132S
2
18 EDP_AUXP_C_TL AUX_P
10U_0603_6.3V6M
C1016

0.1U_0402_16V4Z
C1015

0.1U_0402_16V4Z
C983

DP-IN
1 14

GPIO
18 EDP_AUXN_C_TL AUX_N GPIO(PWM OUT) TL_INVT_PWM 18
1 1 1 15
GPIO(Panel_VCC) TL_ENVDD 18
5 16 R934 1 LVDS@ 2 0_0402_5%
18 EDP_TXP0_C_TL LANE0P GPIO(PWM IN) PCH_INV_PWM 18,8
6 17
18 EDP_TXN0_C_TL LANE0N GPIO(BL_EN) TL_BKOFF# 18
LVDS@

LVDS@

LVDS@

2 2 2
CSCL 9 LVDS 29 I2CC_SCL I2CC_SCL 18
CSDA 10 CIICSCL1 MIICSCL1 28 I2CC_SDA
C CIICSDA1 EDID MIICDA1 I2CC_SDA 18 C

Other
18 EDP_HPD 1 2 TL_HPD 32 ROM 31 MODE_CFG1
HPD MIICSCL0 30 MODE_CFG0
R936 8 MIICSDA0
1K_0402_5% 4 DP_REXT 33

2
LVDS@ DP_GND GND
Close to L64 Close to Pin13 Close to P18
LVDS@
SWR_VDD R938 RTD2132N-CGT_QFN32_5X5
12K_0402_1% Part Number = SA00007A300 LVDS@ +3VS_TL
10U_0603_6.3V6M
C984

0.1U_0402_16V4Z
C1020

22U_0805_6.3V6M
C986

0.1U_0402_16V4Z
C1019

0.1U_0402_16V4Z
C1018

RP41

1
1 1 1 1 1 I2CC_SDA 1 8
use 2132S symbol I2CC_SCL 2 7
CSCL 3 6
LVDS@

LVDS@

LVDS@

LVDS@

LVDS@

CSDA 4 5
2 2 2 2 2
4.7K_8P4R_5%
+3VS_TL

2
@
R943 R944
Close to L6 Close to Pin27 Close to Pin7
4.7K_0402_5% 4.7K_0402_5%
+1.2V_TL LVDS@ +3VS_TL
10U_0603_6.3V6M
C1014

1
0.1U_0402_16V4Z
C1022

0.1U_0402_16V4Z
C1017

0.1U_0402_16V4Z
C1021

1
1 1 1 MODE_CFG0
MODE_CFG1
LVDS@

2
2
LVDS@

LVDS@

LVDS@

@
2 2 2 R945 R946 @

2
B 4.7K_0402_5% 4.7K_0402_5% Q53A B
LVDS@
CSDA 1 6
EC_I2C_TPDAT 27,28
1

DMN66D0LDW-7_SOT363-6 @

5
Q53B

CSCL 4 3
MODE_CFG0(PIN30) EC_I2C_TPCLK 27,28
DMN66D0LDW-7_SOT363-6
0 1
0 X EP MODE
MODE_CFG1(PIN31)
1 ROM ONLY MODE* EEPROM MODE

A A

Security Classification Compal Secret Data


Issued Date 2013/10/30 Deciphered Date 2014/10/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Translator - RTD2132R
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 17 of 44
5 4 3 2 1
A B C D E

EDP / LVDS conn.


Place closed to JLVDS1
+LCDVDD
+3VS
+INVPWR_B+ B+
W=60mils
L11
W=60mils 1
C375 @
1
C419
HCB2012KF-221T30_0805
2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 2 1
XEMC@ EMC@

1000P_0402_50V7K
C364
1 1 XEMC@
LCD POWER CIRCUIT C365 SM01000EJ00 3000ma
68P_0402_50V8J
220ohm@100mhz
2 2 DCR 0.04
+3VS +LCDVDD
U8 W=60mils
1
5 OUT
IN
1 1 LCD/ LED PANEL Conn.
2 C368
GND
1U_0402_6.3V6K
C140

4 0.1U_0402_16V4Z
IN @ +3VS @
1
3 C367 2 2 XEMC@ 1 R959 2
EN

5
4.7U_0603_6.3V6K INVTPWM C549 1 2 220P_0402_50V7K 100K_0402_5%
G5243T11U_SOT23-5 BKOFF# 2 XEMC@

P
2 27 BKOFF# B 4 DISPOFF# C528 1 2 220P_0402_50V7K W=60mils JLVDS1
TL_BKOFF# 1 Y 1
17 TL_BKOFF# A +INVPWR_B+

G
R947 1 EDP@ 2 0_0402_5% 2 1 41
8 PCH_ENVDD 2 G1
U22 LVDS@ 3 42

1
R950 1 LVDS@ 2 0_0402_5% MC74VHC1G08DFT2G_SC70-5 4 3 G2 43
17 TL_ENVDD
R951
W=60mils 5 4 G3 44
INVTPWM 6 5 G4 45
100K_0402_5%
R949 1 EDP@ 2 0_0402_5% DISPOFF# 7 6 G5 46
LVDS@ 7 G6
EDP_HPD 8

2
R280 1 @ 2 10K_0402_5% 9 8
+LCDVDD 9
10
TS_EN_1 11 10
TXOUT_CLK+ 12 11
17 TXOUT_CLK+ 12
TXOUT_CLK- 13
+3VS +3VS 17 TXOUT_CLK- 13
U20 @ TXOUT2+ 14
17 TXOUT2+ 14
M74VHC1GT125DF2G_SC70-5 TXOUT2- 15
2 17 TXOUT2- 15 2
1 @ 2 1 5 TS_RST# 16
27 TS_RST#
1

R362 OE Vcc TXOUT1+ 17 16


17 TXOUT1+ 17
100K_0402_5% R401 TXOUT1- 18
17 TXOUT1- 18
2 1K_0402_5% TXOUT0+ 19
IN A 17 TXOUT0+ 19
@ TXOUT0- 20
17 TXOUT0- 20
EDID_I2C_SDA 21
2

3 4 INVTPWM R438 1 EDP@ 2 0_0402_5% EDID_I2C_SDA EDID_I2C_SCL 22 21


GND OUT Y 9 PCH_I2C0_SDA EDP Touch/LVDS EDID 22
Touch Screen R439 1 EDP@ 2 0_0402_5% EDID_I2C_SCL EDP Touch/LVDS EDID +3VS 23
9 PCH_I2C0_SCL 23
24
EDP_AUXN_C 25 24
R363 1 EDP@ 2 0_0402_5% R415 1 LVDS@ 2 0_0402_5% EDP_AUXP_C 26 25
17,8 PCH_INV_PWM 17 I2CC_SDA 26
LVDS EDID R433 1 LVDS@ 2 0_0402_5% 27
17 I2CC_SCL 27
2

R404 1 @ 2 0_0402_5% EDP_TXP0_C 28


4 EDP_DISP_UTIL 28
R393 EDP_TXN0_C 29
R405 1 LVDS@ 2 0_0402_5% @ 100K_0402_5% 30 29
17 TL_INVT_PWM 30
EDP_TXP1_C 31
EDP_TXN1_C 32 31
1

TS_INT# 33 32
9 TS_INT# 33
+TS_PWR 34
USB20_P5 35 34
10 USB20_P5 35
Touch Screen USB20_N5 36
10 USB20_N5 36
37
eDP +3VS
USB20_P6_CAMERA 38 37
38
For Camera USB20_N6_CAMERA 39
40 39
C372 1 2 EDP@ 0.1U_0402_16V7K EDP_TXN0_C 40
4 EDP_TXN0
C371 1 2 EDP@ 0.1U_0402_16V7K EDP_TXP0_C E-T_0871K-F40N-00L
4 EDP_TXP0
C377 1 2 LVDS@0.1U_0402_16V7K EDP_TXN0_C_TL EDP_TXN0_C_TL 17 CONN@
C376 1 2 LVDS@0.1U_0402_16V7K EDP_TXP0_C_TL EDP_TXP0_C_TL 17
SP010011Z00
C374 1 2 0.1U_0402_16V7K EDP_TXN1_C
4 EDP_TXN1
C373 1 2 0.1U_0402_16V7K EDP_TXP1_C
4 EDP_TXP1
3 3

+3VS
Touch Screen Camera
EDP@ 0217 for pre-MP
4 EDP_AUXN C369 1 2 0.1U_0402_16V7K EDP_AUXN_C R613 2 @ 1 100K_0402_5%
C370 1 2 0.1U_0402_16V7K EDP_AUXP_C R614 2 @ 1 100K_0402_5% +3VS +TS_PWR
4 EDP_AUXP
EDP@
C388 1 2 LVDS@0.1U_0402_16V7K EDP_AUXN_C_TL 17 R82
C389 1 2 LVDS@0.1U_0402_16V7K EDP_AUXP_C_TL 17 0_0603_5%
1 @ 2
R427 1 2 0_0402_5%
+5VS R428 1 2 0_0402_5%
R81
0_0603_5%
10 USB20_N6
USB20_N6 3
3
L27
4
4 USB20_N6_CAMERA pin define, conn need to confirm
1 TS@ 2

USB20_P6 2 1 USB20_P6_CAMERA +3VS


10 USB20_P6 2DLW21HN900HQ2L_4P
1
+3VS R615 1 TS@ 2 100K_0402_5% TS_INT# XEMC@

8 CPU_EDP_HPD 1 @ 2 EDP_HPD EDP_HPD 17


R406 R616 1 @ 2 100K_0402_5% TS_RST#
0_0402_5% JCAM1
1
1
1

USB20_P6_EXCA 2
R431 1 @ 2 0_0402_5% USB20_N6_EXCA 3 2 5
R364 R430 1 @ 2 0_0402_5% 4 3 G1 6
100K_0402_5% R414 1 TS@ 2 0_0402_5% TS_EN_1 4 G2
27 TS_EN
USB20_P6 3 L28 4 USB20_P6_EXCA ACES_88266-04001
2

3 4 CONN@

USB20_N6 2 1 USB20_N6_EXCA
SP02000K200
2DLW21HN900HQ2L_4P
1
4 XEMC@ 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/10/30 Deciphered Date 2014/10/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, March 04, 2014 Sheet 18 of 44
A B C D E
A B C D E

HDMI conn.

1 1

RP15
2.2K_0804_8P4R_5%
1 8 HDMI_SCLK
+HDMI_5V_OUT 2 7 HDMI_SDATA
3 6 DDI2_CTRL_CK
4 5 DDI2_CTRL_DATA
+3VS
HDMI connector
JHDMI1
+3VS HDMI_HPD 19
18 HP_DET
+HDMI_5V_OUT +5V
17
+HDMI_5V_OUT Q15A HDMI_SDATA 16 DDC/CEC_GND
SDA

2
+5VS U3 DMN66D0LDW-7_SOT363-6 HDMI_SCLK 15
14 SCL
3
W=40mils 1 6 HDMI_SCLK 13 Reserved
OUT 8 DDI2_CTRL_CK CEC
1 HDMI_R_CK- 12
1 4 3 HDMI_SDATA 11 CK-
2 IN 8 DDI2_CTRL_DATA CK_shield 2
1 1 C378 Q15B HDMI_R_CK+ 10
2 0.1U_0402_16V4Z DMN66D0LDW-7_SOT363-6 HDMI_R_D0- 9 CK+
C398 C396 GND 2 EMC@ 8 D0-

5
0.1U_0402_16V4Z 0.1U_0402_16V4Z HDMI_R_D0+ 7 D0_shield
2 2 +3VS D0+
EMC@ EMC@ AP2330W-7_SC59-3 Place closed to JHDMI1 HDMI_R_D1- 6
5 D1-
HDMI_R_D1+ 4 D1_shield 20
HDMI_R_D2- 3 D1+ GND 21
2 D2- GND 22
HDMI_R_D2+ 1 D2_shield GND 23
D2+ GND

SUYIN_100042GR019M23MZR
+3VS

CONN@
1 SM070001310 400ma 90ohm@100mhz DCR 0.3
C413 +3VS HDMI_CLK- R368 1 @ 2 0_0402_5% HDMI_R_CK-
DC232001I00
0.1U_0402_16V4Z
EMC@ 2 +3VS HDMI_CLK+ R369 1 @ 2 0_0402_5% HDMI_R_CK+
1

R376
1M_0402_5% Q14A
2

DMN66D0LDW-7_SOT363-6 HDMI_TX0- R370 1 @ 2 0_0402_5% HDMI_R_D0-


RP17
2

8 CPU_HDMI_HPD 1 6 HDMI_HPD HDMI_TX0+ R371 1 @ 2 0_0402_5% HDMI_R_D0+ 470_8P4R_5%


4 CPU_DP2_N1 C381 2 1 0.1U_0402_16V7K HDMI_TX1- 4 5
1

1 4 CPU_DP2_P1 C382 2 1 0.1U_0402_16V7K HDMI_TX1+ 3 6


4 CPU_DP2_N0 C379 2 1 0.1U_0402_16V7K HDMI_TX2- 2 7
R121 C387 HDMI_TX1- R372 1 @ 2 0_0402_5% HDMI_R_D1- 4 CPU_DP2_P0 C380 2 1 0.1U_0402_16V7K HDMI_TX2+ 1 8
100K_0402_5% 220P_0402_50V7K

HDMI_GND
2 EMC@ HDMI_TX1+ R373 1 @ 2 0_0402_5% HDMI_R_D1+ C383 2 1 0.1U_0402_16V7K HDMI_TX0- 4 5
4 CPU_DP2_N2
2

4 CPU_DP2_P2 C384 2 1 0.1U_0402_16V7K HDMI_TX0+ 3 6


3
4 CPU_DP2_N3 C385 2 1 0.1U_0402_16V7K HDMI_CLK- 2 7 3

4 CPU_DP2_P3 C386 2 1 0.1U_0402_16V7K HDMI_CLK+ 1 8


HDMI_TX2- R374 1 @ 2 0_0402_5% HDMI_R_D2-
RP18
HDMI_TX2+ R375 1 @ 2 0_0402_5% HDMI_R_D2+ 470_8P4R_5%

3
Q14B
DMN66D0LDW-7_SOT363-6
+3VS 5

4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/10/30 Deciphered Date 2014/10/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 19 of 44
A B C D E
5 4 3 2 1

DP to VGA-IT6513
+3VS_6513
+3VS +HDMI_5V_OUT

+1.8V_VDDO +1.8V_RX_VCC +1.8V_VDDO +1.8V_RX_VDD +1.8V_VDDO +1.8V_DAC_VDD


L2500 L2501 L2502 +3VS

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

1
+3VS +3VS_6513 @ 1 @ 2 1 @ 2 1 @ 2

1U_0402_6.3V6K
R2502 R2503 R2504 R2505

1U_0402_6.3V6K
1 1 1 1 1
0_0603_5% 0_0603_5% 0_0603_5% 4.7K_0402_5% 2.2K_0402_5%

1U_0402_6.3V6K
1 4.7K_0402_5% 2.2K_0402_5%

C2500

C2501

C2502

C2505
D
R929 2 @ 1 1 D

C2503

2
2
2 2 2 2 2

C2504
0_0603_5%
2

C2506
2 CRT_DATA_1 1 6 CRT_DATA
CRT_DATA 21

Q2501A

5
Place near Pin 35,36 Place near Pin 13,48
DMN66D0LDW-7_SOT363-6
CRT_CLK_1 4 3 CRT_CLK CRT_CLK 21

Q2501B
DMN66D0LDW-7_SOT363-6

DVT modify 11/25


+1.8V_VDDO add level shift

@
1
10U_0603_6.3V6M

C2507
+3VS_6513 +1.8V_RX_VDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R2501 1 @ 2 0_0402_5% DP_HPD 2
8 CPU_DP_HPD
1 1 1

1
ISPSDA

C2508

C2509

C2510
R2506 ISPSCL
4.7K_0402_5%
2 2 2

13
48

35
36

38
39

12
14
44
46
2
U2500

1
2

<BOM Structure>
IVDDO
IVDDO
DDCSCL

IVDD33
IVDD33
DDCSDA

OVDD
OVDD

IVDD
IVDD
IVDD
IVDD
DP_HPD 40 +3VS_6513
C HPD C
45 +3VS_6513
C2511 2 1 0.1U_0402_16V7K CPU_DP1_C_P0 26 270mA 270mA MCUVDDH
4 CPU_DP1_P0 RX0P
C2512 2 1 0.1U_0402_16V7K CPU_DP1_C_N0 27
4 CPU_DP1_N0 RX0N
C2513 2 1 0.1U_0402_16V7K CPU_DP1_C_P1 29 47 @ T2501
4 CPU_DP1_P1 RX1P MCURSTN
C2514 2 1 0.1U_0402_16V7K CPU_DP1_C_N1 30
4 CPU_DP1_N1 RX1N
28 @ T2502
R2508 2 @ 1 1M_0402_5% URDBG
+3VS
C2515 15 ISPSCL 1 2 R2510 22_0402_5%
0.1U_0402_16V7K ISPSCL 16 ISPSDA 1 2 R2511 22_0402_5%
2 1 DDI1_AUX_C_DP 20 ISPSDA
8 DDI1_AUX_DP RXAUXP
2 1 DDI1_AUX_C_DN 19 23 R2514 2 1 22_0402_5% CRT_CLK_1
8 DDI1_AUX_DN RXAUXN VGADDCCLK
C2516 21 R2515 2 1 22_0402_5% CRT_DATA_1
0.1U_0402_16V7K VGADDCSDA
18 3
DCAUXP VSYNC VSYNC 21
R2516 2 @ 1 1M_0402_5% 17 4
DCAUXN HSYNC HSYNC 21

+1.8V_DAC_VDD

C2517

C2519
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1
+1.8V_RX_VCC 25 10
31 AVCC VDDC
0.1U_0402_16V4Z

0.1U_0402_16V4Z

2 1 AVCC
C2518

C2520

1 2 22
PVCC
IT6513FN 2 2

11 CRT_R
IORP CRT_R 21

Place near Pin 22 9 CRT_G


IOGP CRT_G 21
B B

+1.8V_RX_VDD 2 24
DVDD18 8 CRT_B
IOBP CRT_B 21
C2521

1
0.1U_0402_16V4Z 41
1 NC/VGADETECT
5 R2517 1 2 100_0402_1%
32 RSET
+1.8V_RX_VCC 2 ASPVCC

75_0402_1% 2

75_0402_1% 2

75_0402_1% 2
C2522

7 +1.8V_DAC_VDD
0.1U_0402_16V4Z VDDA
1
6 C2523 1 2
COMP

R2518

R2519

R2520
1 R2521 2 2.2K_0402_5% 43 0.1U_0402_16V4Z
1 R2522 2 2.2K_0402_5% 42 PCSDA
+3VS_6513 PCSCL 34 XTALIN_6513
XTALIN 33 XTALOUT_6513
XTALOUT
PWDNB

Note: need external PU to 2K ~ 10K R2523


PAD

1M_0402_5%
XTALOUT_6513 @ XTALIN_6513
IT6513FN_QFN48_6X6
37

49

X2500
27MHZ_10PF_X3G027000BA1H-U
Crystal
3 4
R2549 OUT GND
+3VS_6513 1 2 PWDNB 2 1
@1 GND IN

18P_0402_50V8J
1@

18P_0402_50V8J
10K_0402_5%
C2524 @
DVT modify 11/25 2 C2525
A add pull high 10K 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/10/30 Deciphered Date 2014/10/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ITE IT6513FN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 20 of 44
5 4 3 2 1
A B C D E

CRT conn.

W=40mils
+HDMI_5V_OUT
1 CRB1.0 use 47ohm@100Mhz Bead 1

CRT Connector
L2503 EMC@
BLM15BB470SN1D_2P
1 2 CRT_R_2 JCRT1
20 CRT_R
L2505 EMC@ 6
BLM15BB470SN1D_2P T97 @ 11
1 2 CRT_G_2 1
20 CRT_G
L2504 EMC@ 7
BLM15BB470SN1D_2P 12
1 2 CRT_B_2 2
20 CRT_B
8

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
13
1 1 1 1 1 1 3
9

C2529

C2530

C2531

C2532

C2533

C2534
14
T99 @ 4
2 2 2 2 2 2 10 16
G
15 G 17
5

CCM_070546HR015M25FZR
CONN@

R2524
DC060005810
+HDMI_5V_OUT 1 @ 2 0_0603_5% CRT_HSYNC_2
U2502 @
1 5 0.1U_0402_16V4Z 2 1 C2535 R2525 CRT_CLK 20
R2526 OE Vcc 1 @ 2 0_0603_5% CRT_VSYNC_2
CRT_DATA 20
0_0402_5% 1 1
2 @ 1 CRT_HSYNC 2 @ @
2 20 HSYNC IN A 2
C2536 C2537
10P_0402_50V8J 10P_0402_50V8J
3 4 CRT_HSYNC_1 2 2
GND OUT Y

M74VHC1GT125DF2G_SC70-5

R2528 +HDMI_5V_OUT
0_0402_5% U2503
2 @ 1 1 5
OE Vcc

2 @ 1 CRT_VSYNC 2
20 VSYNC IN A
R2529
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y

M74VHC1GT125DF2G_SC70-5

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2013/10/30 Deciphered Date 2014/10/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAH M/B LA-B161P
Date: Tuesday, February 25, 2014 Sheet 21 of 44
A B C D E
5 4 3 2 1

LAN-RTL8411B
+3VALW PVT modify 12/31 +3V_LAN
reserve 0 ohm

2 1
@ 0_0603_5% W=60mil W=60mil
R2551 IDC=1200mA +LAN_VDD +3V_LAN
W=60mil
60mil U2504
60mil L2506
300mA 1.4A
D D
1 +REGOUT 1 2
5 OUT 2.2UH_NLC252018T-2R2J-N_5%
IN

4.7U_0603_6.3V6K
C2538

0.1U_0402_16V7K
C2539

0.1U_0402_16V7K
C2540

0.1U_0402_16V7K
C2541

0.1U_0402_16V7K
C2542

0.1U_0402_16V7K
C2543

0.1U_0402_16V7K
C2544

1U_0402_6.3V6K
C2545

0.1U_0402_16V7K
C2546

4.7U_0603_6.3V6K
C2547

0.1U_0402_16V7K
C2548

0.1U_0402_16V7K
C2549

0.1U_0402_16V7K
C2550
2 1 1 1 1 1 1 1 1 1 1 1 1 1
4 GND
IN
2
3 LAN_PWR_EN LAN_PWR_EN 27
C2551 EN 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K G5243T11U_SOT23-5
1
Part Number = SA000028Y10

Using for Switch mode


Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
The trace length from Lx to
From EC PIN48 (REGOUT) and from C to Lx The trace length
must < 200mils. from C to
High active. EC_PME# pull high 10K to +3VALW
PIN46,47(VDDREG)
EN threshold voltage min:1.2V typ:1.6V max:2.0V
must < 200mils.
Current limit threshold 1.5~2.8A +3V_LAN
+3V_LAN Rising time must >0.5ms and <100ms R2550
1 2
10K_0402_5%

U2505
8 PCH_PCIE_WAKE# R2532 1 @ 2 0_0402_5% Power Manahement/Isolation
ISOLATEB 31
R2533 1 @ 2 0_0402_5% LAN_PME# 39 ISOLATEBPIN
27 EC_PME# LANWAKEB Card Reader
15 SD_D0 R2534 1 @ 2 0_0402_5% SD_D0_R
SD_D0/MS_D1 SD_D0_R 23
PCI-Express 14 SD_D1 R2537 1 @ 2 0_0402_5% SD_D1_R
C SD_D1 SD_D1_R 23 C
7 CLK_PCIE_LAN CLK_PCIE_LAN 23 16 SD_CLK R2538 1 2 10_0402_5% SD_CLK_R SD_CLK_R 23
CLK_PCIE_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD R2539 1 @ 2 0_0402_5% SD_CMD_R
7 CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_CMD_R 23
18 SD_D3 R2535 1 @ 2 0_0402_5% SD_D3_R 2
SD_D3/MS_D3 SD_D3_R 23
PLT_RST_BUF# 30 19 SD_D2 R2536 1 @ 2 0_0402_5% SD_D2_R
24,8 PLT_RST_BUF# PERSTBPIN SD_D2/MS_CLK SD_D2_R 23
PU at PCH side LAN_CLKREQ# 29 28 SD_WP C2554
7 LAN_CLKREQ# CLKREQBPIN MS_BS/SD_WP# SD_WP 23
5P_0402_50V8C
C2552 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P3 25 1
C788,C791 10 PCIE_PRX_DTX_P3