NLSF595

Serial (SPI) Tri-Color

LED Driver
The NLSF595 is advanced CMOS shift register with open drain
outputs fabricated with 0.6 mm silicon gate CMOS technology. This
device is used in conjunction with a microcontroller, with only one
dedicated line. All pins have Overvoltage Protection that allows http://onsemi.com
voltages above VCC up to 7.0 V to be present on the pins without
damage or disruption of operation of the part, regardless of the MARKING
operating voltage. This device may be used between 2.0 and 5.5 volts, DIAGRAMS
the output driver level may be independent of supply voltage:
07.0 volts. SF
1
595
Features QFN16 ALYWG
MN SUFFIX G
Parallel Outputs are Open Drain Capable of Sinking > 12 mA CASE 485G
Output Withstands up to +7.0 Regardless of VCC
Standard Serial (SPI) Interface, Data, Clock, Enable (Low)
All Inputs CMOS Level Compatible 16
16
Frees up I/O around a Microcontroller NLSF
1 595
Only One Pin Dedicated to this Device (Latch Enable)
ALYWG
TSSOP16
Output Enable may be Permanently Pulled Low DT SUFFIX G
High Speed Clocking, Fmax > 25 MHz (Shift Clock) CASE 948F 1
Eight Bits Parallel Output
Double Buffered Outputs, so Register may Fill without Affecting A = Assembly Location
L = Wafer Lot
Output Y = Year
STD CMOS Serial Output, may be used to Cascade more than W = Work Week
One Device G = PbFree Package
Each Part Controls Two TriColor LEDs (Note: Microdot may be in either location)
Two Devices can Control 5 TriColor LEDs
Low Leakage: ICC = 2.0 mA (Max) at TA = 25C ORDERING INFORMATION
Latchup Performance Exceeds 100 mA See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
QFN16/TSSOP16 Packages
ESD Performance:
Human Body Model; > 2000 V
Machine Model; > 200 V
Functionally Similar to the Popular 74VHC595
These Devices are PbFree and are RoHS Compliant

Semiconductor Components Industries, LLC, 2011 1 Publication Order Number:

June, 2011 Rev. 9 NLSF595/D
 NLSF595

OE EN3
RSK C2
SRG8
SCLR R
SCK C/1
QB 1 16 VCC
SI 1D 2D 3 QA
QC 2 15 QA
QB
QD 3 14 SI
QC
QE 4 13 OE QD
QF 5 12 RCK QE
QF
QG 6 11 SCK
QG
QH 7 10 SCLR 2D 3 QH
GND 8 9 SQH SQH

Figure 1. Pin Assignment Figure 2. IEC Logic Symbol

(TSSOP16)

VCC
QC

QB

QA

16 15 14 13

QD 1 12 SI
(Serial Data Input)

QE 2 NLSF595 11 OE
MN Package

QF 3 (Top View) 10 RCK

(Register Clock)

QG 4 9 SCK
(Shift Clock)

5 6 7 8
QH

GND

SQH

(reset)
SCLR

Figure 3. Pin Assignment (QFN16)

http://onsemi.com
2
 NLSF595

OE

RCK
OVT
QA

SI D Q D Q
SRA STRA
R OVT
QB

D Q D Q
SRB STRB
R OVT
QC

D Q D Q
SRC STRC
R OVT
QD
PARALLEL
D Q D Q DATA
OUTPUTS
SRD STRD
R OVT
QE

D Q D Q
SRE STRE
R OVT
QF

D Q D Q
SRF STRF
OVT
R
QG

D Q D Q
SRG STRG
OVT
R
QH

D Q D Q

SCK SRH STRH

R

SCLR
SQH

Figure 4. Expanded Logic Diagram

http://onsemi.com
3
 NLSF595

MAXIMUM RATINGS
Symbol Parameter Value Units
VCC Positive DC Supply Voltage 0.5 to +7.0 V
VIN Digital Input Voltage 0.5 to +7.0 V
VOUT DC Output Voltage 0.5 to VCC +7.0 V
IIK Input Diode Current 20 mA
IOK Output Diode Current 50 mA
IOUT DC Output Current, per Pin +50 mA
ICC DC Supply Current, VCC and GND Pins 75 mA
PD Power Dissipation in Still Air 450 mW
TSTG Storage Temperature Range 65 to +150 C
ILATCHUP Latchup Performance mA
Above VCC and Below GND at 125C (Note 1) 300

qJA Thermal Resistance, JunctiontoAmbient 128 C/W

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD78

RECOMMENDED OPERATING CONDITIONS

Symbol Characteristics Min Max Units
VCC DC Supply Voltage 2.0 5.5 V
VIN DC Input Voltage 0 5.5 V
VOUT DC Output Voltage 0 VCC V
TA Operating Temperature Range, all Package Types 55 125 C
tr, tf Input Rise or Fall Time ns/V
VCC = 3.3 V 0.3 V 0 50
VCC = 5.0 V 0.5 V 15

FUNCTION TABLE
Inputs Resulting Function
Serial Shift Reg Output Shift Storage Serial Parallel
Reset Input Clock Clock Enable Register Register Output Outputs
Operation (SCLR) (SI) (SCK) (RCK) (OE) Contents Contents (SQH) (QA QH)
Clear shift register L X X L, H, L L U L U
Shift data into shift H D L, H, L DSRA; U SRGSRH U
register SRNSRN+1
Registers remains H X L, H, X L U ** U **
unchanged
Transfer shift register H X L, H, L U SRNSTRN * SRN
contents to storage
register
Storage register remains X X X L, H, L * U * U
unchanged
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high X X X X H * ** * Z
impedance state

SR = shift register contents D = data (L, H) logic level = HightoLow * = depends on Reset and Shift Clock inputs
STR = storage register contents U = remains unchanged = LowtoHigh ** = depends on Register Clock input

http://onsemi.com
4
 NLSF595

DC ELECTRICAL CHARACTERISTICS

TA = 25C TA 3 85C TA 3 125C
VCC

Symbol Parameter Test Conditions (V) Min Typ Max Min Max Min Max Units

VIH Minimum HighLevel Input 2.0 1.5 1.5 1.5 V

Voltage 3.0 2.1 2.1 2.1

4.5 3.15 3.15 3.15

5.5 3.85 3.85 3.85

VIL Maximum LowLevel Input 2.0 0.59 0.59 0.59 V

Voltage 3.0 0.9 0.9 0.9

4.5 1.35 1.35 1.35

5.5 1.65 1.65 1.65

VOH

Minimum HighLevel
Serial Output Only

VIN = VIH or VIL

Output Voltage
IOH = 50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V

VIN = VIH or VIL

VIN = VIH or VIL

IOH = 4 mA 3.0 2.58 2.48 2.34

IOH = 8 mA 4.5 3.94 3.80 3.66

VOL Maximum LowLevel Output IOL = 50 mA 2.0 0.0 0.1 0.1 0.1 V

Voltage 3.0 0.0 0.1 0.1 0.1

VIN = VIH or VIL 4.5 0.0 0.1 0.1 0.1

IOL = 4 mA 3.0 0.36 0.44 0.52

IOL = 8 mA 4.5 0.36 0.44 0.52

VOL2 Maximum LowLevel Output IOL = 20 mA 3.0 0.8 1.0 1.1 1.25 V
Voltage with Max. Load IOL = 25 mA 4.5 0.5 0.6 0.7 0.8

VIN = VIH or VIL

IIN Maximum Input Leakage VIN = 5.5 V or 0 to 5.5 0.1 1.0 1.0 mA
Current GND

ICC Maximum Quiescent Supply VIN = VCC or GND 5.5 4.0 40.0 40.0 mA

Current

IOZ ThreeState Output OffState VIN = VIH or VIL 5.5 0.25 2.5 2.5 mA
Current VOUT = VCC or

QAQH GND

ILKG Active (2) State Off Output VIN = VIH or VIL 5.5 0.25 2.5 2.5 mA
Leakage Current VOUT = VCC or

QAQH GND

IOFF Power Off VIN = 0 or 5.5 V 0 0.25 2.5 2.5 mA

Output Leakage VOUT = 5.5 V

All Outputs

http://onsemi.com
5
 NLSF595

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

TA = 25C TA 3 85C TA 3 125C

Symbol Parameter Test Conditions Min Typ Max Min Max Min Max Units

fmax Maximum Clock Frequency VCC = 3.3 0.3 V 80 150 70 70 MHz
(50% Duty Cycle)

VCC = 5.0 0.5 V 135 185 115 115

tPLH, Propagation Delay, SCK to VCC = 3.3 0.3 V CL = 15 pF 8.8 13.0 1.0 15.0 1.0 15.0 ns

tPHL

SQH

VCC = 5.0 0.5 V
CL = 50 pF
CL = 15 pF
11.3
6.2
16.5
8.2
1.0
1.0
18.5
9.4
1.0
1.0
18.5
9.4

CL = 50 pF 7.7 10.2 1.0 11.4 1.0 11.4

tPHL Propagation Delay, VCC = 3.3 0.3 V CL = 15 pF 8.4 12.8 1.0 13.7 1.0 13.7 ns
SCLR to SQH CL = 50 pF 10.9 16.3 1.0 17.2 1.0 17.2

VCC = 5.0 0.5 V CL = 15 pF 5.9 8.0 1.0 9.1 1.0 9.1

CL = 50 pF 7.4 10.0 1.0 11.1 1.0 11.1

tPLZ Output Disable Time VCC = 3.3 0.3 V CL = 15 pF 7.7 11.9 1.0 13.5 1.0 13.5 ns
RCK to QAQH CL = 50 pF 10.2 15.4 1.0 17.0 1.0 17.0

Output Enable Time VCC = 5.0 0.5 V CL = 15 pF 5.4 7.4 1.0 8.5 1.0 8.5

RCK to QAQH CL = 50 pF 6.9 9.4 1.0 10.5 1.0 10.5

tPZL Output Disable Time VCC = 3.3 0.3 V CL = 15 pF 7.7 11.9 1.0 13.5 1.0 13.5 ns
RCK to QAQH CL = 50 pF 10.2 15.4 1.0 17.0 1.0 17.0

Output Enable Time VCC = 5.0 0.5 V CL = 15 pF 5.4 7.4 1.0 8.5 1.0 8.5
RCK to QAQH CL = 50 pF 6.9 9.4 1.0 10.5 1.0 10.5

tPZL Output Enable Time, VCC = 3.3 0.3 V CL = 15 pF 7.5 11.5 1.0 13.5 1.0 13.5 ns

OE to QAQH RL = 1 kW CL = 50 pF 9.0 15.0 1.0 17.0 1.0 17.0

VCC = 5.0 0.5 V CL = 15 pF 4.8 8.6 1.0 10.0 1.0 10.0

RL = 1 kW CL = 50 pF 8.3 10.6 1.0 12.0 1.0 12.0

tPLZ Output Disable Time, VCC = 3.3 0.3 V CL = 50 pF 12.1 15.7 1.0 16.2 1.0 16.2 ns

OE to QAQH RL = 1 kW

VCC = 5.0 0.5 V CL = 50 pF 7.6 10.3 1.0 11.0 1.0 11.0

RL = 1 kW

CIN Input Capacitance 4 10 10 10 pF

COUT ThreeState Output 6 10 10 pF

Capacitance (Output in

HighImpedance State),
QAQH

Typical @ 25C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Note 2) 87 pF

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the noload dynamic
power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)

TA = 25C

Symbol Characteristic Typ Max Units

VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V
VOLV Quiet Output Minimum Dynamic VOL 0.8 1.0 V
VIHD Minimum High Level Dynamic Input Voltage 3.5 V
VILD Maximum Low Level Dynamic Input Voltage 1.5 V

http://onsemi.com
6
 NLSF595

TIMING REQUIREMENTS (Input tr = tf = 3.0ns)

VCC
TA = 25C TA = 40 to 85C TA = 55 to 125C

Symbol

Parameter

tsu Setup Time, SI to SCK

V

3.3
Typ Limit

3.5
Limit

3.5
Limit

3.5
Units
ns

5.0 3.0 3.0 3.0

tsu(H) Setup Time, SCK to RCK 3.3 8.0 8.5 8.5 ns

5.0 5.0 5.0 5.0

tsu(L) Setup Time, SCLR to RCK 3.3 8.0 9.0 9.0 ns

5.0 5.0 5.0 5.0

th Hold Time, SI to SCK 3.3 1.5 1.5 1.5 ns

5.0 2.0 2.0 2.0

th(L) Hold Time, SCLR to RCK 3.3 0 0 1.0 ns

5.0 0 0 1.0

trec Recovery Time, SCLR to SCK 3.3 3.0 3.0 3.0 ns

5.0 2.5 2.5 2.5

tw Pulse Width, SCK or RCK 3.3 5.0 5.0 5.0 ns
5.0 5.0 5.0 5.0

tw(L) Pulse Width, SCLR 3.3 5.0 5.0 5.0 ns

5.0 5.0 5.0 5.0

http://onsemi.com
7
 NLSF595

2.7 V

+5.0 V

SCLR 220 W
Red
OE
2.7 V Green
NLSF595
Blue
Data
I/O or SPI SI
(MISO) Clock
SCK
EN 5 Additional Outputs
RCK

SQH
Serial
Data Out
MCU

NLSF595 8 Additional Outputs

Total of 5
3Color Displays

QB 1 16 VCC

QC 2 15 QA

QD 3
NLSF595DTR2

14 SI

QE 4 13 OE
QF 5 12 RCK
QG 6 11 SCK
QH 7 10 SCLR

GND 8 9 SQH

Figure 5. NLSF595 Shown Driving 5 3Color LEDs

http://onsemi.com
8
 NLSF595

SWITCHING WAVEFORMS

tw
VCC VCC
SCLR 50%
SCK 50%
GND GND
tw tPHL

1/fmax 50% VCC

tPLH tPHL SQH
trec
SQH 50% VCC VCC
SCK 50%
GND

Figure 6. Figure 7.

VCC
RCK VCC OE 50% 50%
50% GND
GND tPZL tPLZ
HIGH
50% VCC VOL +0.3 V IMPEDANCE
tPLZ tPZL QA-QH
VOL +0.3V
QA-QH
VOL +0.3 V 50% VCC

Figure 8. Figure 9.

VCC
SCLR 50%
VCC
GND
VALID SCK 50%
VCC GND
SI 50% tsu(H)
GND VCC
tsu th 50%
RCK
VCC
50% GND
SCK or RCK tw
GND

Figure 10. Figure 11.

TEST CIRCUITS
TEST POINT TEST POINT
CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kW
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

*Includes all probe and jig capacitance *Includes all probe and jig capacitance
Figure 12. Figure 13.

http://onsemi.com
9
 NLSF595

SCK

SI

SCLR

RCK

OE

QA

QB

QC

QD

QE

QF

QG

QH

SQH

NOTE: output is in a highimpedance state.

Figure 14. Timing Diagram

INPUT

Figure 15. Input Equivalent Circuit

http://onsemi.com
10
 NLSF595

QA QB QC QD QE QF QG QH
ON OFF OFF OFF ON ON OFF ON
LED
0 1 1 1 0 0 1 0
DATA
Data must be valid at the time
of the positive edge.
Data

Duty Cycle Not Important

Clock
250 ns

See Data Sheet for Pinout

+2.5 V

QA
QB

For Cascading SQH QC

Devices QD +5.0 V
QE
Data SI
Clock SCK QF
EN RCK
QG
OE QH

Figure 16. NLSF595 Example

http://onsemi.com
11
 NLSF595

ORDERING INFORMATION
Device Nomenclature

Device Order Circuit Device Package Tape & Reel

Number Indicator Technology Function Suffix Suffix Package Shipping
NLSF595MNR2G NL SF 595 MN R2 QFN 13inch/3000 Unit
(PbFree)

NLSF595DTR2G NL SF 595 DT R2 TSSOP* 13inch/2500 Unit

(PbFree)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.

http://onsemi.com
12
 NLSF595

PACKAGE DIMENSIONS

QFN16 3x3, 0.5P

CASE 485G01
ISSUE F

D A L L NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.
PIN 1 L1 3. DIMENSION b APPLIES TO PLATED

LOCATION TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
DETAIL A

4. COPLANARITY APPLIES TO THE EXPOSED
ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS
E MILLIMETERS
DIM MIN NOM MAX

A 0.80 0.90 1.00
2X 0.10 C A3 A1 0.00 0.03 0.05

EXPOSED Cu MOLD CMPD A3 0.20 REF
b 0.18 0.24 0.30
2X 0.10 C
TOP VIEW D 3.00 BSC
D2 1.65 1.75 1.85
E 3.00 BSC
0.05 C
DETAIL B (A3) A1 E2 1.65 1.75 1.85
DETAIL B e 0.50 BSC
K 0.18 TYP
0.05 C A ALTERNATE
CONSTRUCTIONS L 0.30 0.40 0.50
L1 0.00 0.08 0.15
NOTE 4
A1 SEATING GENERIC
SIDE VIEW C PLANE
MARKING DIAGRAM*
0.10 C A B XXXXX
DETAIL A D2 XXXXX
16X L
8 ALYWG
G
4 9 XXXXX = Specific Device Code
E2 A = Assembly Location
16X K L = Wafer Lot
1 Y = Year
W = Work Week
16 G = PbFree Package
16X b (Note: Microdot may be in either loca-
e 0.10 C A B tion)information is generic. Please refer to
*This
e/2
0.05 C NOTE 3 device data sheet for actual part marking.
BOTTOM VIEW
PbFree indicator, G or microdot G,
RECOMMENDED may or may not be present.
SOLDERING FOOTPRINT*
16X
0.58
PACKAGE
OUTLINE

2X 2X
1.84 3.30

16X
0.30

0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
13
 NLSF595

PACKAGE DIMENSIONS

TSSOP16
CASE 948F01
ISSUE B
16X K REF
NOTES:
0.10 (0.004) M T U S V S 1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.15 (0.006) T U S K 2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
K1 FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT

16 9 EXCEED 0.15 (0.006) PER SIDE.
2X L/2 J1 4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
B SECTION NN NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
L U J DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
PIN 1
(0.003) TOTAL IN EXCESS OF THE K
IDENT. N DIMENSION AT MAXIMUM MATERIAL
1 8 0.25 (0.010) CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M 7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
0.15 (0.006) T U S MILLIMETERS INCHES
A
N DIM MIN MAX MIN MAX
V A 4.90 5.10 0.193 0.200
F B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
DETAIL E F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
C W J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
T SEATING H DETAIL E L 6.40 BSC 0.252 BSC
PLANE D G M 0_ 8_ 0_ 8_

SOLDERING FOOTPRINT

7.06

0.65
PITCH

16X 16X
0.36
1.26 DIMENSIONS: MILLIMETERS

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com
N. American Technical Support: 8002829855 Toll Free ON Semiconductor Website: www.onsemi.com
USA/Canada
Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 421 33 790 2910
Japan Customer Focus Center For additional information, please contact your local
Phone: 81357733850 Sales Representative

http://onsemi.com NLSF595/D
14