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E=0 yes
DACP
3/2Vcm1/2Vip
Introduction: Digital-to-analogue converter (DAC) switching energy is Vip Vip Vcm Vcm
the dominant portion of the total energy consumption in the new gener- C3,2=C C3,1=C C2=C C1=C E=0 C C C C
B2 = 0 or 1?
ation of the successive approximation register analogue-to-digital con- Vcm Vcm
Vip>Vin?
verters (ADCs). Recently, several methods have been introduced to Vcm Vcm
C3,2=C C3,1=C C2=C C1=C C
C C C
reduce the DAC power consumption [16]. The conventional binary Vin Vin Vcm Vcm
weighted DAC offers a simple switching procedure, however, it is not 3/2Vcm1/2Vin
DACN
energy efcient, since it consumes a large amount of energy during E = 0 no
and after the sampling phase (especially during the ADC rst bit deter-
Vcm1/2Vip
mination) [1]. As a remedy, the capacitor-splitting method was intro-
duced to reduce the energy consumption of some switching steps [1]. C C C C
B1 = 0 or 1?
Using the capacitor-splitting DAC, the average switching energy was Vcm V V > 1/2V ?
ip in ref
(Vcm). The methods reported in [5, 6] are proposed to mitigate the effect Vcm Vcm
C C C C C C C C
of the Vcm voltage precision on the DAC INL/DNL, although the Vcm Vcm Vcm Vcm Vcm
dependency remains to some extent. In the proposed switching
7/4Vcm1/2Vin 5/4Vcm1/2Vin
method, Vcm is used as the only reference voltage along with a new
sampling method. As a result, the average switching energy reduces sig-
nicantly while the precision of Vcm do not affect the precision of the Fig. 2 Proposed switching scheme of 3-bit SAR ADC
DAC (since only one reference voltage is used). Moreover, the proposed
switching method offers a simple control circuit which results in a low In this step, the output voltages of DACP and DACN are (3/2Vcm1/
power consumption in comparison to those methods which use more 2Vip) and (3/2Vcm1/2Vin), respectively. The comparator determines
than one reference voltage. whether B2 = 1 or B2 = 0. If Vip > Vin then, B2 is 1, otherwise B2
is 0. In this step, the switching energy is zero as proven in the follow-
ing derivations.
Proposed switching method: Fig. 1 presents the implementation of the
proposed DAC for a 10-bit ADC during the sampling phase. The binary E = EDACP + EDACN
splitted MSB capacitors are shown in the shaded region. In the
E = 2C Vcm VCP,MSP2 VCP,MSP1 + 2C Vcm (VCN,MSP2 VCN,MSP1 )
sampling-phase, the top-plates of all the capacitors are connected to
Vcm ( = 1/2Vref ) while the bottom-plates of the MSB capacitors are con- (1)
nected to the input signals. The bottom-plates of other capacitors are
Vin + Vip
connected to GND to be charged to Vcm. E = 2C Vcm Vcm , Vin = Vref Vip (2)
2
Vref
DACP
E = 2C Vcm Vcm =0 (3)
Vip
Vcm
2
7
2C 2C C C
7
2C 2C C C EDACN and EDACP are the switching energy of DACN and DACP. The
voltage of the MSB capacitors before and after the rst switching step is
Vcm SAR
Vcm logic shown in Fig. 3.
7 7
2C 2C C C 2C 2C C C
3/2Vcm1/2Vip
VCP,MSP1 = VipVcm VCP,MSP2 = 1/2Vip1/2Vcm
Vin Vcm
Vip Vip Vcm Vcm
+ C
VCP,MSP1 C C C VCP,MSP2+ C C C C
DACN
Vcm E=0 Vcm
Vcm Vcm
Fig. 1 Proposed 10-bit SAR ADC at the sampling phase VCN,MSP1
+ C C C C
VCN,MSP2
+ C C C C
Vin Vin Vcm Vcm
VCN,MSP1 = VinVcm VCN,MSP2 = 1/2Vin1/2Vcm
Fig. 2 presents an example of a 3-bit DAC using the proposed switch- 3/2Vcm1/2Vin
ing method. In each step, the switching energy and the output voltage of
DACN and DACP are shown in red and blue colours. In the sampling Fig. 3 Proposed energy-efcient switching sequence after sampling phase
phase, the input signals are sampled on the bottom-plates of the MSB
capacitors (C3,2, C3,1). Then, the sampling switches are disconnected In the second step of the switching procedure, if Vip > Vin the bottom-
and the bottom-plates of the MSB capacitors are connected to Vcm. plates of the MSB capacitor in DACN are connected to GND, then the
250 References
1 Ginsburg, B.P., and Chandrakasan, A.P.: 500-MS/s 5-bit ADC in 65-nm
200
CMOS with split capacitor array DAC, IEEE J. Solid-State Circuits,
switching energy, CV 2ref
Vcm-based [4]
Rahimi and Yavari [5]
2007, 42, (4), pp. 739747
150
Xie et al. [6] 2 Yuan, C., and Lam, Y.: Low-energy and area-efcient tri level switching
proposed
scheme for SAR ADC, Electron. Lett., 2012, 48, (9), pp. 482483
100
3 Zhu, Z., Xiao, Y., and Song, X.: Vcm-based monotonic capacitor switch-
50
ing scheme for SAR ADC, Electron. Lett., 2013, 49, (5), pp. 327329
4 Zhu, Y., Chan, C.-H., Chiu, U.-F., Sin, C.-W., U., S.-P., Martins, R.P.,
0
and Maloberti, F.: A 10-bit 100-MS/s reference-free SAR ADC in
0 200 400 600 800 1000 90 nm CMOS, IEEE J. Solid-State Circuits, 2010, 45, (6),
output code
pp. 11111121
5 Rahimi, E., and Yavari, M.: Energy-efcient high-accuracy switching
Fig. 4 Switching energy against output code method for SAR ADCs, Electron. Lett., 2014, 50, (7), pp. 499501
6 Xie, L., Su, J., Liu, J., and Wen, G.: Low-power high precision
The comparison between the proposed and other switching pro- capacitor-splitting DAC for SAR ADCs, Electron. Lett., 2015, 51, (6),
cedures are presented in Table 1. The average switching energy of the pp. 460462
2
proposed switching procedure is 21.20CVref . The energy reduction is
98.44% compared with the conventional binary weighted DAC. In
fact, in the rst two steps of the proposed DAC there is no switching
energy and in other steps in only one bank (DACP or DACN) there is
switching with the magnitude of Vcm. The average switching energy
of the proposed DAC is calculated using the following equation.
1
Eavg (2N 3 0.625) (4)
6