332:479 Concepts in VLSI

Design

Lecture 6
CMOS Transistor Theory
David Harris and Michael Bushnell

Harvey Mudd College and Rutgers University

Spring 2004
 Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
Adjustments for non-ideal 2nd-order effects
Small-signal MOSFET model
Material from: CMOS VLSI Design,
Design,
by Weste and Harris, Addison-
Addison-Wesley, 2005

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 2

 Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Also explore what a degraded level really means

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 3

 MOS Characteristics
MOS majority carrier device
Carriers: e-- in nMOS, holes in pMOS
Vt channel threshold voltage (cuts off for
voltages < Vt)

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 nMOS Enhancement
Transistor
Moderately doped p type Si substrate
2 Heavily doped n+ regions

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 5

 I vs. V Plots
Enhancement and
depletion
transistors
CMOS uses
only
enhancement
transistors
nMOS uses
both

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 6

 Materials and Dopants

SiO2 low loss, high dielectric strength

High gate fields are possible
n type impurities: P, As, Sb
p type impurities: B, Al, Ga, In

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 7

 Bipolar vs. MOS
Bipolar p-n junction metallurgical
MOS
Inversion layer / substrate junction field-induced
Voltage-controlled switch, conducts when Vgs Vt
e-- swept along channel when Vds > 0 by horizontal component of
E
Pinch-off conduction by e- drift mechanism caused by positive
drain voltage
Pinched-off channel voltage: Vgs Vt (saturated)
Reverse-biased p-n junction insulates from the substrate

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 8

 JFET vs. FET Transistors
Junction FET (JFET) channel is deep in
semiconductor
MOSFET For given Vds & Vgs, Ids controlled by:
Distance between source & drain L
Channel width W
Vt
Gate oxide thickness tox
gate oxide
Carrier mobility

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 JFET Transistor

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 MOS Capacitor
Gate and body form MOS capacitor
Operating modes Vg < 0
polysilicon gate
silicon dioxide insulator
+
Accumulation - p-type body

Depletion (a)

Inversion 0 < Vg < Vt

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

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 Terminal Voltages
Mode of operation depends on Vg, Vd, Vs Vg

Vgs = Vg Vs + +
Vgs Vgd
Vgd = Vg Vd - -

Vds = Vd Vs = Vgs - Vgd Vs Vd

- +
Vds
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 12

 nMOS Cutoff
No channel
Ids = 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 13

 nMOS Linear
Channel forms
Current flows from d to
Vgs > Vt
s + g +
Vgd = Vgs

- -
e- from s to d s d
n+ n+ Vds = 0
Ids increases with Vds
p-type body
Similar to linear resistor b

At drain end of channel, Vgs > Vt

Vgs > Vgd > Vt
+ g +
only difference between - - Ids
s d
gate & drain voltages n+ n+
0 < Vds < Vgs-Vt
effective for channel p-type body
creation b

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 nMOS Saturation
Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

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 I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?

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 Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel =

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

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 Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
C=

gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

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 Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL Cox = ox / tox
V=
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 19

 Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL Cox = ox / tox
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
tox
channel
n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 20

 Carrier velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v=

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 Carrier Velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E=

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 Carrier Velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = Vds/L
Time for carrier to cross channel:
t=

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 Carrier Velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field
between source and drain
v = E called mobility
E = Vds/L
Time for carrier to cross channel:
t=L/v

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 nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross

I ds

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 nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds
t

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 nMOS Linear I-V
Now we know
How much charge Qchannel is in the channel
How much time t each carrier takes to cross
Qchannel
I ds
t
W V V Vds V
Cox gs ds
L
t 2
V W
Vgs Vt ds Vds = Cox
2 L

12/4/2009 Concepts in VLSI Des. Lec. 6 Slide 27

 nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

I ds

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 nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

V
I ds Vgs Vt dsat V
dsat
2

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 nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

V
I ds Vgs Vt dsat V
dsat
2
2
Vgs Vt
2

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 nMOS I-V Summary
Shockley 1st order transistor models

0 Vgs Vt cutoff

Vds V V V
I ds Vgs Vt ds linear
2
ds dsat

2
2
Vgs Vt Vds Vdsat saturation

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 Example
We will be using a 0.6 m process for your project
From AMI Semiconductor
tox = 100 2.5
V =5 gs
2
= 350 cm /V*s 2
Vt = 0.7 V 1.5 V =4

Ids (mA)
gs

Plot Ids vs. Vds 1

V =3
Vgs = 0, 1, 2, 3, 4, 5 0.5
gs

V =2
Use W/L = 4/2 V =1 gs
gs

0
0 1 2 3 4 5
W 3.9 8.85 1014 W W Vds
Cox 350 8 L 120 A /V 2
L 100 10 L

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 pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in AMI 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume n / p = 2

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 Summary
Current Characteristics of MOSFET
Calculation of Vt and Important 2nd-Order Effects
Small-Signal MOSFET Model
Models in this lecture
For pedagogical purposes only
Obsolete for deep-submicron technology
Real transistor parameter differences:
Much higher transistor current leakage
Body effect less significant than predicted
Vt is lower than predicted

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