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AbstractIn this paper, the authors propose a mathematical with a wide output frequency range compared with the standard
model for a new topology called stacked multicell converter flying-capacitor multicell inverter while decreasing the energy
(SMC). Each phase of the SMC n m multilevel inverter is stored in the converter. The first part of this paper presents a
formed by a stack of m flying-capacitor multilevel inverters, and
each stack or stage is realized by connecting in series n control- novel generalized analytical model description of the output
lable commutation cells. An original multicarrier subharmonic voltage of three-phase stacked multilevel inverter (SMC nm).
pulsewidth modulation (PWM), called disposition band carrier In the second part, a new subharmonic pulsewidth mod-
and phase-shifted carrier PWM (DBC-PSC-PWM), method is ulation (PWM), called disposition band carrier and phase-
developed to produce (n m + 1) output voltage levels and shifted carrier PWM (PSC-PWM) (DBC-PSC-PWM), method
to improve the output voltage harmonic spectrum with a wide
output frequency range. A diagram state machine is then used to is developed by combining two modulation techniques, namely,
decode the DBC-PSC-PWM modulator and distribute the com- the disposition band carrier PWM method [10] and PSC-PWM
mutations evenly to each inverter cell in a cyclical fashion. To [16] method, to control the three-phase flying-capacitor stacked
carry out, in practice, the SMC n m modulation technique, multilevel converter. In the third part, a diagram state machine
the implementation of the modulation control strategy has been is used to describe the control of SMC n m by assigning the
done in a field-programmable gate array circuit XC4010E+ of
XILINX to control a three-phase SMC 3 2 seven-level inverter, switching events to the converter cells in a cyclical manner,
and the experimental results are carried out to confirm the high over a complete fundamental load frequency cycle. This state
performance of this inverter. machine switching event allocation balances the switching tran-
Index TermsMulticarrier modulation, multilevel inverter, sitions between the inverter cells, will avoid the generation of
stacked multicell converter (SMC) n m, state machine. narrow unwanted switching pulses, and also preserves the nat-
ural capacitor voltage balancing property of the flying-capacitor
I. I NTRODUCTION converters [19][24]. The last part of this paper concerns the
experimental realization of a three-phase SMC 3 2 inverter,
T HE multilevel inverters have become an important tech-
nology in a high-power conversion system [1][7]. The
crucial advantage of multilevel inverters is the increasing of the
and the experimental results are carried out to confirm the high
performance of this topology.
number of levels and, consequently, the improvement of har-
monic contents in the output voltage and using devices of low II. n m S TACKED M ULTILEVEL I NVERTER
voltage rating with lesser switching frequency. The topologies, (SMC n m) M ODELING
such as single and three-phase neutral-point-clamped inverters A. Topology of SMC n m Inverter
[8][11], cascaded H-bridge inverter [12][15], and flying-
capacitor inverter [16], are well established in medium voltage Each phase of three-phase SMC n m inverter is composed
drives and power system applications. However, if the num- by a stack of m individual flying-capacitor multilevel inverters,
ber of cells is increased to more than five cells, the amount and each stack or stage is realized by connecting in series
of energy to be stored in the capacitor strongly impacts the n controllable commutation cells. To describe the topology,
converters sizing and price. Today, in the field of high power, the main notations are i [1, 2, 3] for the three phases and
we consider that this topology is cost effective for up to four j [1, . . . , n] for the number of cells in each stack. Considering
or five cells in series. A new topology called stacked multicell the case when m is odd and the voltage of the central point O of
converter [(SMC) n m] [17], [18] allows the increase of the the dc link as the reference, we obtain k [1, . . . , m] different
number of configurations and, consequently, the voltage levels voltage stages: k [1, . . . , m/2] different voltage stages for the
output positive voltages and k [m/2, . . . , m] for the output
Manuscript received March 6, 2009; revised June 29, 2009; accepted negative voltages (with j = 1 as the first cell being the one
July 23, 2009. Date of publication August 28, 2009; date of current version connected to the load).
June 11, 2010. Each phase of the new multilevel voltage source inverter
The authors are with the Institut National des Sciences Appliques et de
Technologie, Tunis 1080, Tunisia, and also with the Laboratoire des Systmes is composed of (2 n m) turn-on and turnoff controlled
lectriques, Ecole Nationale dIngnieurs de Tunis, Tunis 1002, Tunisia semiconductor devices T (i, j, k) and T (i, j, k) [insulated-gate
(e-mail: Moncef.bensmida@yahoo.fr; Faouzi.benamar@insat.rnu.tn). bipolar transistor (IGBT) switch with an antiparallel diode].
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. The n m commutation cells are connected with a set of
Digital Object Identifier 10.1109/TIE.2009.2030764 m (n 1) flying-capacitor voltage sources V c(i, j, k), and
each flying capacitor C(i, j, k) is connected between two com- Fig. 2. Three-phase schema of stacked multilevel inverter SMC 3 2.
plementary switches T (i, j, k) and T (i, j, k). The dc bus E
of SMC (n m + 1)_level inverter is composed by a stack of TABLE I
m individual dc sources connected in series; for a symmetrical S WITCHING S TATES FOR AN SMC 3 1 F OUR -L EVEL
inverter, the magnitude of each source is equal to E/m. F LYING -C APACITOR I NVERTER
The stacked multilevel inverter (SMC n m) can generate
Nlevel voltage outputs by connecting the flying voltage sources
to the ac sources by Nconfig combinations of the switches.
The number of configurations of the switches per phase is
equal to
TABLE II
S WITCHING S TATES FOR AN SMC 3 2 I NVERTER
With N = m.n, N is the number of strictly positive line-to- number of vectors is (n m + 1)3 = 343. The number of
line voltage levels of the inverter nil vectors at the origin is given as (n m + 1) = 7. The
number of distinct vectors is equal to [(n m + 1)3 (n
Vs 2 1 12 12
= m)3 ] = 127. The six concentric regular hexagons H2, H3, H4,
Vs 3 0 3
23
n m 2 H5, H6, and H7 represent the levels attained by the output
LL
voltages. These hexagons are composed by 36, 60, 72, 72, 60,
j=1 L=1 V c(1, j, L) S(1, j, k)
k=1
and 36 vectors, respectively.
n m
V c(2, j, L)
S(2, j, k)
. (12)
j=1 L=1 k=1
n m III. C ONTROL S TRATEGY W ITH M ULTICARRIER
L
V c(3, j, L) S(3, j, k) P ULSEWIDTH M ODULATION T ECHNIQUE
j=1 L=1 k=1
The principle of driving the power semiconductors of SMC
In fact, if the flying-capacitor voltages are balanced, the n m inverter is based on a subharmonic DBC-PSC-PWM
relation (12) is replaced by the relation method. If (n m + 1) levels are required, n m carrier
signals of fixed frequency will be needed. As shown in Fig. 5,
Vs 2.E 1 12 12
= the carriers have the same peak-to-peak amplitude Ac = E/m
Vs 3.n.m 0 3
3
n 2m LL2 and are disposed in continuous bands around the zero reference.
S(1, j, k) For each kth stage, n triangular carrier signals are generated,
j=1 L=1
k=1
each to be added with the offset band Ak and the phase shifts
n m
S(2, j, k) of j between the adjoining cells. The triangular carrier signal
. (13)
j=1 L=1 k=1 is simulated by the following:
n m L
S(3, j, k) Ac Ac
j=1 L=1 k=1 Tri(i, j, k) = Ak + +
2
As shown by the space vector representation of the output
arcsin sin 2.f c.t + i.i + j.j + k.k (14)
voltage of the SMC 3 2 (n = 3, m = 2) (Fig. 4), the total 2
BEN SMIDA AND BEN AMMAR: MODELING AND DBC-PSC-PWM CONTROL OF A VOLTAGE SOURCE INVERTER 2235
two stacks) connected to a 10-kVA power (R, L) load. The Figs. 1214 show the experimental output voltage between
dc bus E = 300 V; the modulation frequency is fixed to phase A and the middle point O of the dc input source with
10 kHz. The modulation strategy DBC-PSC-PWM is im- modulation index M = 30%, 50%, and 95%, respectively. It is
plemented in logic arrays by the development board XS40 clearly shown in Fig. 15 that the peak to peak of the phase-
based on XILINX XC4010E field-programmable gate array to-phase output voltage VAB has 13 voltage output levels.
(FPGA). According to the experimental results shown in Fig. 16(a),
The XC4010 has around 10 000 logic gates, 400 configurable the DBC-PSC-PWM modulator guarantees the natural bal-
logic blocks, and 160 input/output blocks. Some important ancing property of all 12 flying-capacitor voltages (four per
specifications of the XC4010E+ are listed in Table III. phase and two per stack) V c(i, 1, 1) = V c(i, 1, 2) = 50 V and
The generated DBC-PSC-PWM binary file .BIT is loaded in V c(i, 2, 1) = V c(i, 2, 2) = 100 V. Fig. 16(b) shows the VAO
electrically erasable programmable read-only memory circuit output voltage for various modulation indexes of three-phase
AT17LV256 (256 b) of the XS40 card by using XSloads tool SMC 3 2 inverter. The maximum voltages across the IGBT
of XILINX XSTOOLS software and a parallel link between the switches are limited to E/6 = 50 V. In fact, the SMC n m
XS4010E card and the computer. At every start of the inverter, has two advantages: The first one is the reduction of semicon-
the .Bit file is restored in the FPGA. ductor switch voltage constraints [25], and the second is the
The control system is connected to a personal computer and considerable reduction of flying-capacitor total storage energy
interfaced to the IGBT IXYS IXSN80N60A U1 (600 V/60 A) [17] and, therefore, the reduction of the size of these capacitors.
via optical links. Three FPGA control cards (one per phase)
guarantee the generation of the control signals. Each card
V. C ONCLUSION
produces the control signals of the IGBTs of the concerned
phase. With the SMC 3 2 three-phase inverter, six carrier In this paper, the authors have proposed a general mathe-
(3 2) signals of fixed frequency (10 kHz) are generated in matical model for a new topology called SMC dedicated to
each phase. Every triangular carrier is realized by means of a high-power voltage applications. It has been shown that the
recharged counter/discounter (C/D), every C/D counts from 1 to disposition band carrier modulation and phase-shifted carrier
N 1 and then deducts until zero. To have a phase shift of 120 modulation can be combined to give a new DBC-PSC-PWM. A
between the three triangular carriers, the number [2(N 1)] diagram state machine is used to decode the DBC-PSC-PWM
must be divisible by three. It also includes the generation of modulator and to allocate the transitions evenly to each cell
dead time (T m = 5 s). over a complete fundamental load frequency cycle, avoiding
2238 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Fig. 13. VAO output voltage three-phase SMC 3 2 with modulation index
M = 50%.
Fig. 11. Three-phase SMC 3 2 panel (three cells and two stages) IGBT
inverter (seven levels). Fig. 15. Phase-to-phase VAB output voltage three-phase SMC 3 2 with
M = 95%.
TABLE III
S PECIFICATION OF THE FPGA XC4010
Fig. 16. (a) Flying-capacitor voltages [V c(i, 1, 1) and V c(i, 2, 1)]. (b) VAO
output voltage for various modulation indexes.
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management solutions based on isolated and nonisolated configurations April 15, 1966. He received the Engineer degree
of multilevel modular capacitor-clamped converter, IEEE Trans. Ind. in electrical engineering and the D.E.A. and Ph.D.
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combination of hexagonal and 12-sided polygonal voltage space vector From 1991 to 2000, he was an Engineer with
PWM control for IM drives using cascaded two-level inverters, IEEE the Society Tunisia Engineering and Construction
Trans. Ind. Electron., vol. 56, no. 5, pp. 16571664, May 2009. Industrial, working on the electrical and instrument
[13] P. Lezana, J. Rodriguez, M. A. Perez, and J. Espinoza, Input current conception and development of industrial process.
harmonics in a regenerative multicell inverter with single-phase PWM From 2000 to 2007, he was a Chief Engineer with the
rectifiers, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 408417, National Case of Security Social. Since 2007, he has
Feb. 2009. been an Assistant Professor with the Institut National des Sciences Appliques
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error input-current controller for regenerative multilevel converters based machine modeling, control induction motor drives, pulsewidth modulation,
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modulation of flying capacitor and stacked multicell converters using a Institute of Toulouse, Toulouse, France, in 1989 and
state machine decoder, in Proc. 36th IEEE Power Electronics Specialists 1993, respectively.
Conf., 2005, pp. 16711677. From 1993 to 1998, he was an Engineer with
[19] X. Yuan, H. Stemmler, and I. Barbi, Self-balancing of the clamping- Alstom (Cegelec) Company, Belfort, France, working on the development of
capacitor-voltages in the multi-level capacitor-clamping-inverter under control drive systems. In 1998, he joined the Institut National des Sciences
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no. 2, pp. 256263, Mar. 2001. been a Habilitation la Direction de la Recherche and a Professor of power
[20] B. P. McGrath and D. G. Holmes, Analytical modelling of voltage bal- electronics since 2004. His research interests include power electronics and
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Power Electron., vol. 23, no. 2, pp. 543550, Mar. 2008. multilevel inverter, active filter, reliability, and RMAS analysis.