MIPS Microprocessor

MIPS 32 1
Computer Architecture
CISC
Complex Instruction Set Computer
Intels x86.
RISC
Reduced Instruction Set Computer
Any computer architecture defined after 1984
MIPS
Microcomputer without Interlocked Pipeline Stages
Millions of Instructions Per Second
Strongly pipelined architecture
DECs Alpha, HPs Precision

MIPS 32 2
MIPS Architecture
Microprocessor without Interlocked Pipeline Stages
Developed at Stanford 1985
Reduced Instruction Set Computer (RISC)
Load-Store Architecture i.e. Memory reference only in
Load or Store instruction
ALU instructions are (3, 0)
64-bit version came in 1999 called MIPS64
Memory byte addressable with 64 bit address
Instruction length 32 bit fixed
Opcode length fixed 6 bit

MIPS 32 3
Registers
32-bit registers
32 general-purpose registers (GPR) named R0, R1, ... R31
32 floating-point registers (FPR) named F0, F1, ..., F31
with single precision(32 bits) and double precision (64 bits)
R0 always holds zero
Data sizes for Integers 8-bit, 16-bit (half word),
32-bit (word).
Data sizes for Floating-point 32-bit (single
precision) and 64-bit( double precision).
Operations on integers of all sizes are 32-bit
operations (adding zeros or the sign bit on left).
MIPS 32 4
Registers
32 in Number are 32-bit (word) registers
$a0 - $a3: argument registers
$v0 - $v1: return values
$ra: return address register
$sp: stack pointer
$fp: frame pointer
$gp: global pointer
$zero: always equals 0
$s0 - $s7: preserved on a procedural call
$t0 - $t9: not preserved by callee on a procedural call

MIPS 32 5
Arithmetic Operations
e.g. add a, b, c # a = b + c
add $t0, $s1, $s2
e.g. sub a, b, c # a = b c
sub $s0, $t0, $t1

Arithmetic operations occur only on registers

MIPS 32 6
Data Transfer
lw $t0, 8($s3) # load $t0 with data from memory
# base address in $s3, offset 8
sw $t0, 48($s3) # store word

MIPS 32 7
Branch Instruction
j 32000 # PCPC+[sign extend to 32 bits (32000)]

MIPS Fields for J-Type

6 bits 26 bits

J-type op address

MIPS 32 8
MIPS Fields for R and I-Type
R-type op rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

I-type op rs rt address

op: basic operation, also called opcode

rs: the first register source operand
rt:
R-type: the second register source operand
I-type: destination register
rd: the register destination operand
shamt: shift amount in shift instructions
funct: selects the specific variant of the operation in op field, also
called function code
address: offset of memory address in data transfer instructions

MIPS 32 9
Examples of Machine Code
op rs rt rd shamt funct

0 18 19 17 0 32 add $s1, $s2, $s3

0 18 19 17 0 34 sub $s1, $s2, $s3

op rs rt address

35 18 17 100 lw $s1, 100($s2)

43 18 17 100 sw $s1, 100($s2)

MIPS 32 10
Some Examples of Other Instructions

beq $s3, $s4, L1 # go to branch L1, if equal

bne $s3, $s4, L1 # go to branch L1, if not equal
j L1 # jump to branch L1
jr $t0 # jump based on $t0
slt $t0, $s1, $s2 # set value of $t0 to 1, if less than
sll $t2, $s0, 8 # reg $t2 = reg $s0 << 8 bits
srl $t2, $s0, 8 # reg $t2 = reg $s0 >> 8 bits
addi $sp, $sp, 4 # $sp = $sp + 4
nop # do nothing

MIPS 32 11
MIPS Addressing Mode
Register addressing: the operand is a register
Base or displacement addressing: the
operand is at the memory whose address is
the sum of a register and a constant
Immediate addressing: the operand is a
constant
PC (Program Counter)-relative addressing:
address is the sum of PC and a constant in
the instruction

MIPS 32 12
Steps for MIPS Instructions
1. Fetch instruction from memory
2. Read registers while decoding the instruction
3. Execute the operation or calculate an address
4. Access an operand in data memory (for lw and sw)
5. Write the result into a register

MIPS 32 13
Implement Instruction Fetch

Add

PC Read
address
Instruction
Instruction
memory

MIPS 32 14
Datapath for R-type Instructions
5 Read Control
register 1 Read 32
data 1
5 Read
register 2
Instruction
Registers
ALU
5 Result 32
Write
register
Read 32
Write data 2
data

Reg_write

MIPS 32 15
Instruction Set of MIPS

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MIPS 32 26
 Thank You

MIPS 32 27