DE

Government Engineering College, Rajkot
Electronics & Communication Engineering Department
Digital Electronics [2131004]
Laboratory Manual
For
Semester III (EC)

Enrolment No. :
Electronics & Communication Engineering Department

Digital Electronics [2131004]
Semester: 3rd EC
List of Experiments
Sr. Page
Experiment Title Date GSignature
No. No. r
Realization of basic logic gates using diodes a
1.
and transistors d
Verification of logic gates using digital ICs e
2. and configuring NAND and NOR gates as
universal logic gates
Configuration of binary adders and
3.
subtractors
Configuration of 4-bit Binary-to-Gray and
4.
Gray-to-Binary code convertors
Configuration of Octal-to-Binary encoder and
5.
BCD-to-Seven Segment decoder
6. Configuration of multiplexer & demultiplexer
Configuration of JK-flip-flop, RS-flip-flop, D-
7.
flip-flop and T-flip-flop using digital ICs
Configuration of universal shift registers
8.
using digital IC
Configuration of modulo-N ripple counter
9.
using T-flip-flops
Implementation of 8-bit ALU using
10.
FPGA/CPLD boards
11. Presentation
GECR/BE-EC/Sem3/DE/LAB
Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Realization of Logic Gates using Diodes and Transistors
EC Sem. III EXPERIMENT NO. : 01 DATE :
AIM:
To study realization of logic gates (AND, OR, NOT gates) using diode and transistor.
Apparatus:
1. Diodes: 1N4007 2
2. Transistors: 2N2222 3
3. Registers: 10 k 3, 4.7 k 3
4. +5 V DC Source 2
5. Connecting wires
THEORY:
Logic gates are the fundamental building blocks of digital systems. The name logic gates is
derived from the ability of such a device to make decisions, in the sense that it produces one
output level when some combinations of input levels are present, and a different output
level when other combinations of input levels are present.
There are just three basic types of gates AND, OR, and NOT. The computers are
able to perform very complex logic operations with the interconnections of these
elementary logic gates.
Inputs and outputs of logic gates can occur only in two levels. These two levels are
termed as HIGH and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0.
A table which lists all the possible combinations of input variables and the
corresponding outputs is called truth tables. It shows how logic circuits output responds to
various combinations of logic levels at the inputs.
A logic in which the voltage levels represent logic 1 and logic 0 is called level logic. It
may be of two types: Positive Logic, or Negative Logic. A positive logic system is the one in
which the higher of the two voltage levels represents the logic 1 and the lower of the two
voltage levels represents the logic 0. A negative logic system is the one in which the higher
of the two voltage levels represents the logic 0 and the lower of the two voltage levels
represents the logic 1. In transistor-transistor logic (TTL, the most widely used logic family),
the voltage levels are +5 V and 0 V.
All elementary logic gates can be realized using diode and transistor circuitry.
[1] Realization of AND gate

AND gates may be realized by using diodes (called Diode Logic DL) or transistors
(called Resistor Transistor Logic RTL) as shown in Fig.1(a) and Fig.1(b) respectively.
The inputs A and B to the gates may be either 0 V or 5 V.

1
To Study Realization of Logic Gates using Diode and Transistor Experiment : 01
In the diode AND gate, when A = 5 V and B = 5 V, both the diodes D1 and D2 are
OFF. So, no current flows through R and, therefore, no voltage drop occurs across R.
Hence, the output X 5 V.
When A = 0 V or B = 0 V or when both A and B are equal to 0 V, the corresponding
diode D1 or D2 is ON or both diodes are ON and act as short-circuits (ideal case), and
therefore, the output X 0 V. In practical circuits, X = 0.6 V or 0.7 V which is treated
as logic 0.
Fig.1 Realization of AND gate
In the transistor AND gate, when A = 0 V and B = 0 V or when A = 0 V and B = 5 V or

when A = 5 V and B = 0 V, both the transistors T1 and T2 are OFF. Transistor T3 gets
enough base drive from the supply through R and so, T3 will be ON. Hence, the
output voltage X = Vce(sat) 0 V.
When both A abd B are equal to 5 V, both the transistors T1 and T2 will be ON and,
therefore, the voltage at the collector of transistor T1 will drop. So, T3 does not get
enough base drive and, therefore, remains OFF. Hence no current flows through the
collector resister of T3 and, therefore, no voltage drop occurs across it. Hence output
voltage, X 5 V.
The truth table for the above gate circuits is as shown below.
Inputs Output
A B X
0V 0V 0V
0V 5V 0V
5V 0V 0V
5V 5V 5V

2
[2] Realization of OR gate

OR gates may be realized by using diodes or transistors as shown in Fig.2(a) and
Fig.1(b) respectively. The inputs A and B to the gates may be either 0 V or 5 V.
Fig.2 Realization of OR gate
In the diode OR gate, when A = 0 V and B = 0 V, both the diodes D1 and D2 are OFF.
No current flows through R, and so, no voltage drop occurs across R. Hence, the
output voltage X = 0 V.
When either A = 5 V or B = 5 V or when both A and B are equal to 5 V, the
corresponding diode D1 or D2 is ON or both D1 and D2 are ON and act as short-
circuits (ideal case) and, therefore, output X 5 V. In practice, X = 5 V diode drop =
5 V 0.7 V = 4.3 V, which is regarded as logic 1.
In the transistor OR gate, when A = 0 V and B = 0 V, both the transistors T1 and T2
are OFF. Transistor T3 gets enough base drive from 5 V through R and, therefore, it
will be ON. The output voltage, X = Vce(sat) 0 V.
When either A = 5 V or B = 5 V or when both A and B are equal to 5 V, the
corresponding transistor T1 or T2 is ON or both T1 and T2 will be ON and, therefore,
the voltage at the collector of T1 is = Vce(sat) = 0 V. This cannot forward bias the base-
emitter Junction of T3 and, therefore, it will remain OFF. Hence, the output voltage
will be X = 5 V (logic 1 level).
The truth table for the above OR gate circuits is as shown below.
Inputs Output
A B X
0V 0V 0V
0V 5V 5V
5V 0V 5V
5V 5V 5V

3
[3] Realization of NOT gate

A NOT gate may be realized using a transistor as shown in Fig.3. The input to the
gate may be 0 V or 5 V.
Fig.3 Realization of NOT gate
When A = 0 V, the transistor T is OFF. As no current flows through R, no voltage drop

occurs across R. Hence, the output voltage X = 5 V. When the input A = 5 V, T is ON
and the output voltage X = Vce(sat) 0 V.
The truth table for the table for the NOT gate circuit is as shown below.
Input Output
A X
0V 5V
5V 0V
PROCEDURE:
1. Place all circuit components on a breadboard.
2. Prepare circuitry using connecting wires.
3. Apply different level logic combinations to the inputs and observe the corresponding
outputs.
4. Note down observed output level in corresponding observation table.
OBSERVATION TABLES:
1) AND gate realization using diode:

Inputs Output
A B X
0V 0V
0V 5V
5V 0V
5V 5V

4
2) AND gate realization using transistor:

Inputs Output
A B X
0V 0V
0V 5V
5V 0V
5V 5V
3) OR gate realization using diode:

Inputs Output
A B X
0V 0V
0V 5V
5V 0V
5V 5V
4) OR gate realization using transistor:

Inputs Output
A B X
0V 0V
0V 5V
5V 0V
5V 5V
5) NOT gate realization using transistor:

Input Output
A X
0V
5V
CONCLUSION:

5
Enrolment No. :
TITLE:
SUBJECT:
Verification of Logic Gates and Configuring NAND and
Digital Electronics
NOR Gates as Universal Logic Gates
AIM:
To verify AND, OR, NOT, NAND, NOR, and XOR gates using digital ICs and to configure NAND
and NOR gates as universal logic gates.
Apparatus:
1. Digital ICs:
a. IC 7408 Quad 2-input AND gates
b. IC 7432 Quad 2-input OR gates
c. IC 7404 Hex inverters
d. IC 7400 Quad 2-input NAND gates
e. IC 7402 Quad 2-input NOR gates
f. IC 7486 Quad XOR gates
2. Digital Logic Circuit Trainer kit
3. +5 V DC Source 2
4. Connecting wires
THEORY:
Logic gates are logical circuits that take logical decision based on one or more input logic
levels. AND, OR, and NOT gates are called basic logic gates. Logic circuits of any complexity
can be realized by using only these three basic gates.
Both NAND and NOR gates can perform all the three basic logic functions (AND, OR,
and NOT) using different configurations. Therefore, NAND and NOR gates are called
universal logic gates.
Part-A Verifying Logic Gates

[1] AND gate
The AND gate is a logical device whose output is 1, if and only if all its inputs are 1. Hence,
the AND gate is also called an all or nothing gate.
Fig.1 A two-input AND gate

6
Verification of Logic Gates & Configuring Basic Logic Gates as Universal . . . Experiment : 02
Fig.2 Quad 2-input AND gates IC 7408 pin diagram
[2] OR gate
An OR gate is defined as a device whose output is 1, even if one of its inputs is 1. Hence, an
OR gate is also called an any or all gate.
Fig.3 A two-input OR gate
Fig.4 Quad 2-input OR gates IC 7432 pin diagram

7
[3] NOT gate

A NOT gate is a device whose output is always the complement of its input. Therefore, a
NOT gate is also called an inverter gate.
Fig.5 The NOT gate
Fig.6 Hex inverters IC 7404
[4] NAND gate

A NAND gate is a device whose output is logic 0 level, only when each of the inputs assumes
a logic 1 level. NAND means NOT AND, i.e. the AND output is NOTed. So, a NAND gate is a
combination of an AND gate and a NOT gate.
Fig.7 A two-input NAND gate

8
Fig.8 Quad 2-input NAND gates IC 7400 pin diagram
[5] NOR gate

A NOR gate is a device whose output is logic 1 level, only when each of the inputs assumes a
logic 0 level. NOR means NOT OR, i.e. the OR output is NOTed. So, a NOR gate is a
combination of an OR gate and a NOT gate.
Fig.9 A two-input NOR gate
Fig.10 Quad 2-input NOR gates IC 7402 pin diagram

9
[6] XOR (Exclusive OR) gate

An XOR gate is a two input, one output logic circuit, whose output assumes a logic 1 state
when one and only one of its two inputs assumes a logic 1 state.
Fig.11 XOR gate
Fig.12 Quad XOR gates IC 7486 pin diagram
Part-B Configuring NAND and NOR gates as universal gates
[1] NAND Gate as Universal Logic Gate
NAND gate as an inverter gate
NAND gate as an AND gate

10
NAND gate as an OR gate
[2] NOR Gate as Universal Logic Gate
NOR gate as an inverter gate
NOR gate as an AND gate
NOR gate as an OR gate
PROCEDURE:
outputs.
4. Match observed output level with theoretical output given in corresponding truth
table.

11
CONCLUSION:

12
Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of Binary Adders and Subtractors
AIM:
To configure and verify binary half-adder, full-adder, half-substrator, and full-substractor
circuits using basic logic gates.
Apparatus:
1. Digital Logic ICs:
a. IC 7486 Quad XOR gates
b. IC 7408 Quad 2-input AND gates
c. IC 7432 Quad 2-input OR gates
d. IC 7483 4-bit binary parallel full-adder
2. Digital Logic IC Trainer kit
3. +5 V DC Source
4. Connecting wires
THEORY:
Digital computers perform a variety of information processing tasks. Among the basic tasks
encountered are the various arithmetic operations. The most basic arithmetic operation is
the addition and subtraction of two binary digits.
In this experiment, we will design the adder and subtractor circuits using basic logic
gates. The adder and subtractor circuits are combinational logic circuits. If the output of
logic circuit depends on its present inputs only, it is called combinational circuits.
Part-A: Adder Circuits

[1] Half-Adder
A half-adder is a combinational logic circuit which adds the two inputs (A and B) and
produces the sum (S) and the carry (C) bits. It is an arithmetic circuit used to perform
the arithmetic operation of addition of two single bit words.
The truth table and block diagram of a half-adder are shown in Fig.1.
Fig.1 Half-adder

13
Configuration of Binary Adders and Subtractors Experiment : 03
The Boolean expression for the sum (S) and the carry (C) bit are given by
= + =
=
Therefore, a half-adder can be realized by using one X-OR gate and one AND gate as
shown in Fig.2.
Fig.2 Logic diagram of Half-Adder
[2] Full-Adder
When we want to add two binary numbers, each having two or more bits, the LSBs
can be added by using a half-adder. The carry resulted from the addition of the LSBs
is carried over to the next significant column and added to the two bits in that
column. So, in the second and higher columns, the two data bits of that column and
the carry bit generated from the addition in the previous column need to be added.
The full-adder adds the bits A and B and the carry from the previous column called
the carry-in (Cin) and gives the sum bit (S) and the carry bit called the carry-out (Cout)
as outputs.
The block diagram and the truth table of a full-adder are shown in Fig.3.
Fig.3 Full-Adder
The Boolean expression for the sum (S) and the carry-out (Cout) bit are given by
=
=+=++

14
The logic diagram of the full-adder using two X-OR gates and two AND gates (i.e.
two half-adders) and one OR gate is shown in Fig.4.
Fig.4 Logic diagram of a full-adder using two half-adders
Part-B: Subtractor Circuits
[1] Half-Subtractor
A half-subtractor (shown in Fig.6) is a combinational circuit which subtract a bit B
from another bit A and gives two outputs d and b. d indicates the difference and b is
the output signal generated that informs the next stage that a 1 has been borrowed.
Fig.6 Half-Subtractor
The Boolean expression for the difference (d) and the borrow (b) bit are given by
=
=
Fig.7 shows the logic diagram of a half-subtractor using an X-OR gate, AND gates,
and NOT gate.

15
Fig.7 Logic diagram of a half-subtractor
[2] Full-Subtractor
The half-subtractor can be used only for LSB subtraction. If there is a borrow during
the subtraction of the LSBs, it affects the subtraction in the next higher column. Such
a subtraction is performed by a full-subtractor.
So a full-subtractor is a combinational circuit with three inputs (A, B, bi) and two
outputs d and b. Where bi is a borrow from the preceding column, and the two
outputs represents the difference and output borrow. The output variables are
determined from the subtraction of . The truth table and the block
diagram of a full-subtractor are shown in Fig.8.
Fig.8 Full-subtractor
The Boolean expression for the difference (d) and the borrow (b) bit are given by
=
= +
Therefore, a full-subtractor can be realized using X-OR gates and AOI gates as shown
in Fig.9.

16
Fig.9 Logic diagram of a full-subtractor
Part-C 4-Bit Binary Parallel Adder
Binary parallel adder is a digital circuit that adds two binary numbers in parallel form
and produces the arithmetic sum of those numbers in parallel form. It consists of full
adders connected in a chain, with the output carry from each full-adder connected
to the input carry of the next full- adder in the chain.
Fig.10 shows the interconnection of four full-adder (FA) circuits to provide a 4-bit
parallel adder.
Fig.10 Logic diagram of a 4-bit binary parallel adder
IC 7483 is a 4-bit binary full-adder with internal carry look-ahead. It accepts two 4-bit
binary word (A3A2A1A0 and B3B2B1B0) and a carry input (Cin), and generates the binary
sum output (S3S2S1S0) and the carry output (C4).
Fig.11 shows a pin diagram of IC 7483.

17
Fig.11 Pin diagram of the IC 7483
An n-bit parallel adder requires n-full adders. It can be constructed from 4-bit, 2-bit,
and 1-bit by cascading several full adder ICs packages.
Example of binary addition of two 4-bit binary numbers:
PROCEDURE:
outputs.
OBSERVATION TABLES:
1) Half-adder:
Input Output
A B S C
0 0
0 1
1 0
1 1

18
2) Full-adder:
Input Output
A B Cin S Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3) Half-subtractor:
Input Output
A B D b
0 0
0 1
1 0
1 1
4) Full-subtractor:
Input Output
A B bi d B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
5) 4-bit Binary Parallel Adder:
Sr.
Decimal Addition Binary Addition
No.
A B S Cin A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 Cout
1.
2.
3.
4.

19
CONCLUSION:

20
Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of 4-bit Binary Code Converters
AIM:
To configure 4-bit binary-to-gray and gray-to-binary code converters.
Apparatus:
1. Digital Logic IC: 7486 Quad XOR gates
2. +5 V DC Source
3. Connecting wires
THEORY:
The availability of a large variety of binary codes (BCD, Gray, Excess 3, etc.) for the same
discrete elements of information results in the use of different codes by different digital
systems. It is sometimes necessary to use the output of one system as the input to another.
A conversion circuit must be inserted between the two systems if each uses different codes
for the same information. Thus a code converter is a logic circuit whose inputs are bit
patterns representing numbers (or characters) in one code and whose outputs are the
corresponding representations in a different code. It makes two systems compatible even
though each uses a different binary code. Code converters are usually multiple output
circuits.
To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. A combinational circuit performs this
transformation by means of logic gales.
Part A: Design of a 4-bit Binary-to-Gray Code Converter
The input to the 4-bit binary-to-Gray code converter circuit is a 4-bit binary and the
output is a 4-bit Gray code. There are 16 possible combinations of 4-bit binary input
and all of them are valid. Hence no don't cares. The 4-bit binary and the
corresponding Gray code are shown in the conversion table (Fig.1).

21
Configuration of 4-bit Binary Code Converters Experiment : 04
Fig.1 4-bit Binary-to-Gray code converter
From the conversion table, we observe that the expressions for the outputs G4, G3,
G2 and G1 are as follows:
The K-maps G4, G3, G2 and G1 and their minimization are as follows:

22
The minimal expressions for the outputs obtained from the K-map are:
So, the conversion can be achieved by using three X-OR gates as shown in the logic
diagram in Fig.2.
Fig.2 Logic diagram of 4-bit binary-to-gray code converter
Part B: Design of a 4-bit Gray-to-Binary Code Converter
The input to the 4-bit Gray-to-binary code converter circuit is a 4-bit Gray code and
the output is a 4-bit binary. There are 16 possible combinations of 4-bit Gray input
and all of them are valid. Hence no don't cares. The 4-bit input Gray code and the
corresponding output binary numbers are shown in the conversion table of Fig.3.

23
Fig.1 4-bit Gray-to-Binary code converter
From the conversion table we observe that the expressions for the outputs B4, B3, B2
and B1 are:
Drawing the K-maps for B4, B3, B2 and B1 in terms of G4, G3, G2 and G1 as shown
below:

24
The minimal expressions for the outputs are as follows:
Based on the above expressions, a logical circuit can be drawn as shown in Fig.4.
Fig.4 Logic diagram of 4-bit gray-to-binary code converter
PROCEDURE:
25
outputs.
OBSERVATION TABLES:
1) 4-bit Binary-to-gray code converter:
4-bit Binary 4-bit Gray
B4 B3 B2 B1 G4 G3 G 2 G1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2) 4-bit Gray-to-binary code converter:

4-bit Gray 4-bit Binary
B4 B3 B2 B1 G4 G3 G 2 G1
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000

26
CONCLUSION:

27
Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of Encoder and Decoder
AIM:
To configure Octal-to-Binary encoder and BCD-to-7 Segment decoder.
Apparatus:
1. Digital IC:
a. IC 74148 Octal-to-binary priority encoder
b. IC 7447 BCD-to-seven segment decoder/drivers
2. +5 V DC Source 2
3. Connecting wires
THEORY:
Part: A Encoder
An encoder is a device whose inputs are decimal digits and/or alphabetic characters and
whose outputs are the coded representation of those inputs, i.e. an encoder is a device
which converts familiar numbers or symbols into coded format.
An encoder has a number of input lines, only one of which is activated at a given
time, and produces an N-bit output code depending on which input is activated. Fig.1 shows
the block diagram of an encoder with M inputs and N outputs. Here, the inputs are active
HIGH, which means they are normally LOW.
Fig.1 Block diagram of encoder

Octal-to-Binary Encoder
An octal-to-binary encoder (8-line to 3-line encoder) accepts 8 input lines and
produces a 3-bit output code corresponding to the activated input. Fig.2 shows the
truth table and the logic circuit for an octal-to-binary encoder with active HIGH
inputs.
28
Configuration of Encoder and Decoder Experiment : 05
Fig.2 Octal-to-binary encoder
From the truth table, we see that A2 is a 1 if any of the digits D4 or D5 or D6 or D7 is a

1. Therefore,
We see that D0 is not present in any of the expressions. So, D0 is a don't care.
Fig.3 IC 74148 pin diagram
Part: B Decoder
A decoder is a logic circuit that converts an N-bit binary input code into M output lines such
that only one output line is activated for each one of the possible combinations of inputs. In
other words, we can say that a decoder identifies or recognizes or detects a particular code.

29
Fig.4 shows the general decoder diagram with N inputs and M outputs. Since each of
the N inputs can be a 0 or a 1, there are 2N possible input combinations or codes. For each
of these input combinations, only one of the M outputs will be active (HIGH), all the other
outputs will remain inactive (LOW).
Fig.4 General block diagram of a decoder
Some decoders do not utilize all of the 2N possible input codes. For example, a BCD
to decimal decoder has a 4-bit input code and 10 output lines that correspond to the 10 BCD
code groups 0000 through 1001. Decoders of this type are often designed so that if any of
the unused codes are applied to the input, none of the outputs will be activated.
BCD-to-Seven Segment Decoder

This type of decoder accepts the BCD code and provides outputs to energize seven
segment display devices in order to produce a decimal read out. Sometimes, the hex
characters A through F may be produced. Each segment is made up of a material
that emits light when current is passed through it. The most commonly used
materials include LEDs, incandescent filaments and LCDs. The LEDs generally provide
greater illumination levels but require more power than that by LCDs.
Fig.5 shows a seven-segment display consisting of seven light emitting segments.
The segments are designated by letters a-g as shown in the figure. By illuminating
various combinations of segments as shown in Fig.5(b), the numbers 0-9 can be
displayed. Fig.5(c) and Fig.5(d) show two types of LED display the common-anode
and the common-cathode types.
Fig.5 The seven segment display

30
Fig.5 The seven segment display (continued...)
In the common-anode type, a low voltage applied to an LED cathode allows current
to flow through the diode, which causes it to emit light. In the common-cathode
type, a high voltage applied to an LED anode causes the current to flow and
produces the resulting light emission.
An 8-4-2-1 BCD-to-seven segment decoder is a logic circuit as shown in Fig.6(a). The
function table for such a decoder is shown in Fig.6(b). Since a 1 (HIGH) on any output
line activates that line, we assume that the display is of the common-cathode type.
The K-map used to simplify the logic expression for driving segment b is shown in
Fig.6(c). Entries 10-15 are don't cares as usual. Since LEDs require considerable
power, decoders often contain output drivers capable of supplying sufficient power.
Dont cares,

31
Fig.6 BCD-to-seven segment decoder
Fig.7 IC 7447 pin diagram
PROCEDURE:
outputs.

32
OBSERVATION TABLES:
1) Octal-to-binary encoder:
Activated Line Octal Binary
D7 D6 D5 D4 D3 D2 D1 D0 Digits A2 A1 A0
0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 1 0 1
2
3
4
5
6
7
2) BCD-to-seven segment decoder:

Decimal 8-4-2-1 Seven segment code
Digit A3 A2 A1 A0 a b c d e f g
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
CONCLUSION:

33
Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of multiplexer & demultiplexer
AIM:
To configure 81 multiplexer and 18 demultiplexer.
Apparatus:
1. Digital IC:
a. IC 74151A 8X1 multiplexer
b. IC 74138 1X8 demultiplexer
2. +5 V DC Source 2
3. Connecting wires
THEORY:
Part A - Multiplexers (Data Selectors)
A multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and
allows only one of them at a time to get through to the output. The routing of the desired
data input to the output is controlled by SELECT inputs (sometimes referred to as ADDRESS
inputs).
Fig.1 shows the functional diagram of a general multiplexer. In this diagram, the
inputs and outputs are drawn as large arrows to indicate that they may constitute one or
more signal lines. Normally there are 2n input lines and n select lines whose bit
combinations determine which input is selected.
Fig.1 Functional diagram of a digital multiplexer
The multiplexer acts like a digitally controlled multi-position switch. The digital code
applied to the SELECT inputs determines which data inputs will be switched to the output.

Configuration of Multiplexer and Demultiplexer Experiment : 06
For example, the output Z will equal the data input D0 for some particular input code; Z will
equal D1 for another particular code, and so on. In other words, we can say that a
multiplexer selects 1-out-of-N input data sources and transmits the selected data to a single
output channel. This is called multiplexing.
Basic 2-input Multiplexer

Fig.2 shows the logic circuitry and function table for a 2-input multiplexer with data inputs
D0 and D1, and data select input S. The logic level applied to the S input determines which
AND gate is enabled, so that its data input passes through the OR gate to the output Z.
Fig.2 2-input multiplexer
The 4-input Multiplexer

Fig.3 shows the logic circuitry for a 4-input multiplexer with data inputs D0, D1, D2, and D3,
and data select inputs S0 and S1. The logic levels applied to the S0 and S1 inputs determine
which AND gate is enabled, so that its data input passes through the OR gate to the output
Z. The function table in Fig.3 gives the output for the input select codes as

Fig.3 4-input multiplexer

The 8-input Multiplexer

The 2-4-8-16-input multiplexers are readily available in the TTL and CMOS families. These
basic ICs can be combined for multiplexing a larger number of inputs. IC 74151A contains 8-
input multiplexer with eight data inputs D0, D1, D2, D3, D4, D5, D6, and D7, and three data
select inputs S0, S1, and S2. The pin diagram of IC 74151A is shown in Fig.4.
Fig.4 Pin diagram of IC 74151A (8-input multiplexer)
Applications of Multiplexers
Multiplexers find numerous and varied applications in digital systems of all types. These
applications include data selection, data routing, operation sequencing, parallel-to-serial
conversion, waveform generation, and logic function generation.
Part-B Demultiplexer (Data Distributors)
A multiplexer takes several inputs and transmits one of them to the output. A demultiplexer
performs the reverse operation; it takes a single input and distributes it over several
outputs. So a demultiplexer can be thought of as a 'distributor', since it transmits the same
data to different destinations. Thus, whereas a multiplexer is an N-to-1 device, a
demultiplexer is a 1-to-N (or 2n) device.
Fig.5 shows the functional diagram for a demultiplexer (DEMUX). The large arrows
for inputs and outputs can represent one or more lines. The 'select' input code determines
the output line to which the input data will be transmitted. In other words, the
demultiplexer takes one input data source and selectively distributes it to 1-of-N output
channels just like a multi-position switch.

Fig.5 Functional diagram of a general demultiplexer
1-Line to 4-Line Demultiplexer

Fig.6 shows a 1-line to 4-line demultiplexer circuit. The input data line goes to all of the AND
gates. The two select lines S0 and S1 enable only one gate at a time, and the data appearing
on the input line will pass through the selected gate to the associated output line.
Fig.6 1-Line to 4-Line demultiplexer
1-Line to 8-Line Demultiplexer

Fig.7 (a) shows the logic diagram for a demultiplexer that distributes one input line to eight
output lines. The single data input line D is connected to all eight AND gates, but only one of
these gates will be enabled by the select input lines. For example, with S2S1S0 = 000, only the
AND gate O0 will be enabled, and the data input D will appear at output O0. Other select
codes cause input D to reach the other outputs. The truth table in Fig.7 (b) summarizes the
operation.

Fig.7 1-Line to 8-Line demultiplexer
The IC 74138 is a 1-line to 8-line demultiplexer IC. Its pin diagram is shown in following Fig.8.
Fig.8 Pin diagram of IC 74138 (1-line to 8-line demultiplexer)
PROCEDURE:
outputs.

OBSERVATION TABLES:
1. 8 to 1 multiplexer
Input data bits =
Select lines Output

S2 S1 S0 Z
2. 1 to 8 demultiplexer
Select Lines Output

S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
CONCLUSION:

Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of Various Flip Flops
AIM:
To study basic flip-flops: SR, D, JK & T.
Apparatus:
1. Digital IC:
a. IC 7400 2-input NAND gate
b. IC 7402 2-input NOR gate
c. IC 7404 Hex- Inverter
d. IC 7408 2-input AND gate
e. IC 7411 3-input AND gate
2. +5 V DC Source 2
3. Connecting wires
THEORY:
A Multivibrator is a regenerative circuit with two active devices designed so that one device
conducts while the other is cut off. Multivibrator can store binary numbers. So it can
perform essential functions like counting of pulses, synchronizing arithmetic Operations etc.
Such type of circuit is known as FLIP-FLOP circuits. Here we are going to study all types of
FLIP-FLOPs:
1. R-S Latch
2. R-S Flip-Flop
3. D Flip-Flop
4. J-K Flip-Flop
5. T Flip-Flop
* R-S Latch*
The circuit diagram of R-S latch is made up of two NOR gates. It has two inputs namely R and
S (R= Reset & S=Set) and has outputs namely Q andQ, whereQ bar is always the
complement of Q. The output can be changed to other state only with the help external
inputs R and S.

Configuration of Various Flip Flops Experiment : 07
The truth table of R-S latch is:
S R Q
1 0
0 0
0 1
0 0
1 1
Working:
R = 0 & S = 0. Since 0 input has no effect on its output, the flip-flop simply remains on
its previous state i.e. Q remains unchanged.
R = 0 & S = 1 forces the output to switch over to 1 i.e. at high level. Thus input at 1
level is said that the Flip-flop has SET i.e. Q = 1(Naturally Q = 0).
R=1 & S = 0 forces the output to switch over to 0 i.e. at low level. Thus input at 0
level is said that the flip-flop has RESET i.e. Q = 0 (Naturally Q = 1).
R = 1 & S = 1 forces the output of both NAND gate to low state & high state
simultaneously. In other words Q=Q, may be 0 or 1 simultaneously. This state is
known as FORBIDDEN STATE. Generally it is agreed upon never to impose this input
condition.
* CLOCKED R-S FLIP FLOP *
The clocked R-S flip flop is shown in figure below. Hence, it is necessary that the state
changes take place only during fixed interval of time, determined by some carefully
regulated pulse train or discrete inputs. These inputs are different from the S-R inputs. This
additional input is called CLOCK and the various elements in the system work in co-
ordination with it. Output changes take place only when the clock pulse (or the level)
appears.

The truth table of this Clocked R-S flip-flop is
Outputs before Outputs after

Inputs
clock pulse clock pulse
Qn S R Qn+1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
The logic symbol for RS flip flop is:
* D FLIP- FLOP *
D flip-flop is shown in figure below. This Flip-Flop is constructed from R-S Flip-Flop. The S
input of R-S Flip-Flop is kept as it is and R input is shorted with S input through a NOT gate.
D flip flop is also known as Delay flip flop since it generated the same output as input when
the clock pulse arrives. D flip flop is used in the construction of shift registers, counters and
various other applications.

The truth table of this D flip-flop is

Input
Qn D Qn+1
0 0
0 1
1 0
1 1
The logic symbol is:
Working:
When D input is 0, the output is 0.

When D input is 1, the output is 1.
Hence, D Flip-Flop gives the same output as the input and therefore D stands for DATA.
* J-K FLIP- FLOP *
J-K flip-flop can be used to build a counter that counts the number of positive or negative
clock edges driving its clock input. For the purpose of counting, the J-K flip-flop is the ideal
element to use. The circuit diagram of J-K flip-flop is as shown.

The logic symbol is:
The truth table of this J-K flip-flop is

Inputs
Qn J K Qn+1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Working:
When J & K both are at low state, both AND gate are disabled and so clock pulse has no
effect i.e. Q retains its last value.
When J=0 & K=1 upper gate is disabled so there is no way to set the flip-flop. The only
possibility is RESET. When Q is high, the power gate passes a RESET triggers as soon as the
next positive clock edge arrives. This forces Q to become low.
When J=1 & K=0, lower gate is disable so it is impossible to RESET the flip-flop. We can SET
the flip-flop, when Q is low Q is high. Therefore the upper gate passes a SET trigger on the
next positive clock edge. This drives Q in to high state i.e. Q=1.

When J=1 & K=1 then there is a forbidden state with R-S flip-flop i.e. it is impossible to SET
or RESET the flip-flop. Therefore J=1 & K=1 means the flip-flop will toggle on the next
positive clock edge. The toggle means to switch to the opposite state.
Thus by addition of clock and getting propagation delay, racing problem can be eliminated
in J-K flip-flop.
* T FLIP-FLOP *
T flip-flop is the flip-flop that satisfies only the first two and the last two condition of the JK
flip-flop. As flip-flop is called toggle flip-flop by virtue of its property that the state stored
toggles on receiving a clock pulse (when T=1) goes to the opposite state. A JK flip-flop can
easily be converted into a T flip-flop by connecting its two inputs together. T flip-flop finds
applications in digital counters.
The Truth table of T Flip-Flop is

Input
Qn T Qn+1
0 0
0 1
1 0
1 1
Working:
When CP=1, T=0 => Q(t+1) = Q
When CP=1, T=1 => Q(t+1) = Q

PROCEDURE:
outputs.
CONCLUSION:

Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of shift registers using digital IC
AIM:
Configuration of shift registers using digital IC
Apparatus:
1. Digital IC:
a. IC 74AS194 4-bit Universal Shift Register
2. +5 V DC Source 2
3. Connecting wires
THEORY:
A Flip-Flop can store only one bit of data. If we want to store a group of bits, a series of flip-
flops are inter-connected in cascade. This cascaded group of flip-flop as a whole is called a
Register. The fundamental operations, which make a register very useful, are its Shift
right and Shift left operation. There are two methods for shifting binary information into
a register.
1. Shifting the information into a register one bit at a time in a series fashion and leads to
the development of a serial shift register.
2. Shifting all the bits into the register at a same time and leads to the development of a
parallel shift register.
There are basically 4 types of shift registers:
1. Serial-in, serial-out shift register
2. Serial-in, parallel-out shift register
3. Parallel-in, serial-out shift register
4. Parallel-in, parallel-out shift register
Serial-in, serial-out shift register can be of 2 types:
(i) Serial-in, serial-out shift right register
(ii) Serial-in, serial-out shift left register
Also there are 2 shift registers available:
1. Bidirectional shift register
2. Universal shift register
Here, we have used IC74AS194. It is a 4-bit Universal Shift register. It is also known as
Bidirectional shift register with parallel load. By using this shift register we can shift the
serial data either to left or to right as well as parallel input, parallel output can also be taken.

Configuration of shift registers using digital IC Experiment : 08
The logic diagram of universal shift register is as shown below:
Figure 1: IC74AS194.
The Truth table is:
INPUT OUTPUTS
MODE S
SERIAL PARALLEL
QA QB QC QD
S1 S2 LEFT RIGHT A B C D
CLEAR CLOCK
0 X X X X X X X X X 0 0 0 0
1 X X L X X X X X X QA0 QB0 QC0 QD0
1 1 1 H X X a b c d a b c d
1 0 1 H X 1 X X X X 1 QAn QBn QCn
1 0 1 H X 0 X X X X 0 QAn QBn QCn
1 1 0 H 1 X X X X X QBn QCn QDn 1
1 1 0 H 0 X X X X X QBn QCn QDn 0
1 0 0 X X X X X X X QA0 QB0 QC0 QD0

Configuration of shift registers using digital IC Experiment : 08
This shift register has four distinct modes of operation.

1. Parallel Shift Mode:
Applying the four bits of data and taking both mode control inputs, S 0 and S1 high,
accomplish synchronous parallel loading. The data are loaded into the associated
flip-flops and appears at the outputs after the positive transition of the clock input.
During loading, serial data flow is inhibited.
2. Shift Right Mode:
Shift right is accomplished synchronously with the rising edge of the clock pulse
when S0 is high and S1 is low. Serial data for this mode is entered at the shift right
data input.
3. Shift Left Mode:
When S0 is low and S1 is high, 1 bit data shifts one position to the left synchronously
and new data is entered at the serial-left serial input at every clock pulse.
4. Inhibiting Mode:
Clocking of the flip-flops is inhibited when both mode control inputs are low.
PROCEDURE:
outputs.
CONCLUSION:

Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Configuration of 4-bit Binary Ripple Counter
AIM:
Configuration of 4-bit Binary Ripple Counter
Apparatus:
1. Digital IC:
a. IC 7476 - JK Flip flop
b. IC 7408 2-input AND gate
2. +5 V DC Source 2
3. Connecting wires
THEORY:
A counter is a register capable of counting the number of clock pulses that have arrived at
its clock input. Digital Counters are used in Digital Computers in their control Circuit and in
digital watches to represent time in hours, minutes and seconds. Counters are also used in
Industry.
Digital counters are sequential building blocks made by cascading flip-flop together. These
units count the number of pulses arriving at its clock inputs. They are constructed with the
help of JK or T flip flop.
Two types of Digital Counters:
Asynchronous counters
Synchronous counters
Also according to the output state, counters can be classified as:
(i) Up counter
(ii) Down counter
(iii) Up/Down counter
In order to design n-bit counter, we need n flip flops and we get 2n output states. So a 2-bit
counter gives 4 output states: 00, 01, 10 & 11. Similarly 3-bit counter gives 8 output states.
Hence according to the output states required, we can design counter.
Synchronous counter
The counters in which all the flip-flops are having same clock pulse are known as
synchronous counters. In this counter clock pulses drive all flip-flops in parallel. Because of
the simultaneous clocking, the correct binary word appears after one propagation delay
Configuration of 4-bit Binary Ripple Counter Experiment : 09
time. Hence, synchronous counters are faster. The least significant flip-flop has its J and K
inputs are High, so it responds to the clock pulse. But the remaining flip-flops can respond to
the clock pulse only under certain conditions.
The logic diagram of 4-bit synchronous up counter is as shown:
Figure 1: 4-bit synchronous up counter
Asynchronous counter (Ripple counter)

The counters in which the clock pulse is applied to only one flip flop are known as
asynchronous counters. The other flip flops are given clock input from the output of the
previous flip flops. They are slower as compared to synchronous counters since the output
of one flip flop reflects the output of other and so on.
The logic diagram of 4-bit asynchronous up counter is as shown below. Here, the Q output of
FF1 is connected to the clock pulse of FF2; the Q output of FF2 is connected to the clock
pulse of FF3 and so on.
Figure 2: 4-bit binary ripple up counter
Up counter can be converted to down counter by connecting output to the clock

pulse of the next flip-flops. The logic diagram is as shown below:

Figure 3: 4-bit binary ripple down counter
PROCEDURE:
outputs.
OBSERVATION TABLE:
1. 4-bit up counter
Clock Counter output State Decimal

number equivalent
Q3 Q2 Q1 Q0
Initially
1st
2nd
3rd

2. 4-bit down counter
Clock Counter output State Decimal

number equivalent
Q3 Q2 Q1 Q0
Initially
1st
2nd
3rd
CONCLUSION:

Enrolment No. :
SUBJECT: TITLE:
Digital Electronics Implementation of 8-bit ALU using FPGA/CPLD boards
AIM:
Implementation of 8-bit ALU using FPGA/CPLD Boards
APPARATUS:
1. Xilinx Spartan 3E FPGA Board

2. 12V DC Adapter
BLOCK DIAGRAM:
OPERATION:
sel Operation Function Unit

0000 y <= a Transfer a
0001 y <= a + 1 Increment a
0010 y <= a - 1 Decrement a
0011 y <= b Transfer b
Arithmetic
0100 y <= b + 1 Increment b
0101 y <= b - 1 Decrement b
0110 y <= a + b Add a and b
0111 y <= a + b + cin Add a and b with carry
1000 y <= NOT a Complement a
1001 y <= NOT b Complement b
1010 y <= a AND b AND
1011 y <= a OR b OR
Logic
1100 y <= a NAND b NAND
1101 y <= a NOR b NOR
1110 y <= a XOR b XOR
1111 y <= a XNOR b XNOR
Implementation of 8-bit ALU using FPGA/CPLD boards Experiment : 10
VHDL CODE:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY de_alu IS
PORT ( a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); b
: IN STD_LOGIC_VECTOR (7 DOWNTO 0); sel :
IN STD_LOGIC_VECTOR (3 DOWNTO 0); cin : IN
STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end de_alu;
ARCHITECTURE architecture_de_alu OF de_alu IS

SIGNAL arith, logic : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
---- Arithmetic Unit : ------- WITH
sel (2 DOWNTO 0) SELECT
arith <= a WHEN "000",

a+1 WHEN "001",
a-1 WHEN "010",
b WHEN "011",
b+1 WHEN "100",
b-1 WHEN "101",
a+b WHEN "110",
a+b+cin WHEN OTHERS;
---- Logic Unit : ------
WITH sel (2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000",

NOT b WHEN "001",
a AND b WHEN "010", a
OR b WHEN "011",
Implementation of 8-bit ALU using FPGA/CPLD boards Experiment : 10
a NAND b WHEN "100",
a NOR b WHEN "101",
a XOR b WHEN "110",
NOT (a XOR b) WHEN OTHERS;
----- Multiplexer : ------
WITH sel(3) SELECT
y <= arith WHEN '0',

logic WHEN OTHERS;
END architecture_de_alu;
SIMULATION RESULTS:
CONCLUSION:


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Government Engineering College, Rajkot

Electronics & Communication Engineering Department

Digital Electronics [2131004]

Semester III (EC)

Electronics & Communication Engineering Department

[1] Realization of AND gate

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Fig.1 Realization of AND gate

In the transistor AND gate, when A = 0 V and B = 0 V or when A = 0 V and B = 5 V or

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[2] Realization of OR gate

Fig.2 Realization of OR gate

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[3] Realization of NOT gate

Fig.3 Realization of NOT gate

When A = 0 V, the transistor T is OFF. As no current flows through R, no voltage drop

1) AND gate realization using diode:

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2) AND gate realization using transistor:

3) OR gate realization using diode:

4) OR gate realization using transistor:

5) NOT gate realization using transistor:

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Part-A Verifying Logic Gates

Fig.1 A two-input AND gate

Fig.2 Quad 2-input AND gates IC 7408 pin diagram

Fig.3 A two-input OR gate

Fig.4 Quad 2-input OR gates IC 7432 pin diagram

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[3] NOT gate

Fig.5 The NOT gate

Fig.6 Hex inverters IC 7404

[4] NAND gate

Fig.7 A two-input NAND gate

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Fig.8 Quad 2-input NAND gates IC 7400 pin diagram

[5] NOR gate

Fig.9 A two-input NOR gate

Fig.10 Quad 2-input NOR gates IC 7402 pin diagram

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[6] XOR (Exclusive OR) gate

Fig.11 XOR gate

Fig.12 Quad XOR gates IC 7486 pin diagram

Part-B Configuring NAND and NOR gates as universal gates

[1] NAND Gate as Universal Logic Gate

NAND gate as an inverter gate

NAND gate as an AND gate

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NAND gate as an OR gate

[2] NOR Gate as Universal Logic Gate

NOR gate as an inverter gate

NOR gate as an AND gate

NOR gate as an OR gate

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Part-A: Adder Circuits

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Fig.2 Logic diagram of Half-Adder

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Fig.4 Logic diagram of a full-adder using two half-adders

Part-B: Subtractor Circuits

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Fig.7 Logic diagram of a half-subtractor