Code: R7320206

R07
B.Tech III Year II Semester (R07) Supplementary Examinations May/June 2015
VLSI DESIGN
(Common to EEE, E.Con.E and ECE)

Time: 3 hours Max Marks: 80

Answer any FIVE questions
All questions carry equal marks
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1 (a) Explain in detail about p-well process for CMOS fabrication indicating the masks used.
(b) Distinguish MOS technology over BicMOS.
(c) Differentiate diffusion and ion implantation.

2 (a) Determine the pull up to pull down ratio of an nMOS inverter when driven through one or more
pass transistors.
(b) Discuss about: (i) Ids Vs Vds relationships. (ii) BicMOS inverter.

3 (a) Draw the nMOS depletion transistor using lambda based design rules.
(b) Explain and design layout for CMOS NAND gate.
(c) Briefly explain limitations of scaling.

4 (a) Discuss about: (i) Pseudo-nMOS logic. (ii) Domino logic.

(b) Explain about driving of large capacitive loads.

5 (a) Discuss about shifters.

(b) Discuss about parity generators.
(c) Discuss about memory elements using MOS technology.

6 (a) Discuss in detail semi-custom layout styles.

(b) Write about: (i) PLA. (ii) CPLDs.

7 (a) Explain in detail about circuit design flow.

(b) Discuss about design verification tools.

8 Explain the following verifications tools:

(a) Timing verifiers.
(b) Design rate checkers.
(c) Layout extraction.
(d) Test vectors.

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