RF circuit design: Basics

Akira Matsuzawa

Tokyo Institute of Technology

1
 Contents

• Building blocks in RF system and basic

performances
• Device characteristics in RF application
• Low noise amplifier design
• Mixer design
• Oscillator design

2
 Basic RF circuit block
RF systems are composed of limited circuits blocks.
LNA, Mixer, and Oscillator will be discussed in my talk.

1)
Receiver
Low
Impedance Noise
Matching Amp. 2) Mixer Filter

Transmitter 3) Oscillator

Power
Amp.

3
 Basic functions of RF building blocks
Amplifier, frequency converter (mixer +oscillator), and filer
are basic function blocks in RF system.

2) Mixer+ Oscillator
Undesired
Down conversion

3) Filter Desired 1) Amplifier

dB dB
Frequency conversion

Up conversion
Log (f) Log (f)

4
 RF Amplifier

• Gain: Amplify small signal or generate large signal.

• Noise: Smaller noise and larger SNR.
• Linearity: Smaller non-linearity.

Non-linearity generates undesired frequency components.

vout (t ) = α1vin (t ) + α 2 vin2 (t ) + α 3vin3 (t ) + .....

(cos(ω1t ) + cos(ω2t ))2 = 2 + cos(2ω1t ) + cos(2ω2t ) + cos((ω1 − ω2 )t ) + cos((ω1 + ω2 )t )

(cos(ω1t ) + cos(ω2t )) 3
= cos((2ω1 − ω2 )t ) + cos((2ω2 − ω1 )t ) + ....
1 1
2 2

5
 Input and output characteristics
Distortion and noise are important factors in RF amplifier, as well as power and gain.
Pout
OIP3 IP3

1dB
Pout
(1dB)

Fundamental IMD3

Slope=1 SFDR
Slope=3

SNR min
Noise SNR min
Floor
SFDR
BDR Pin

NoiseMDS CP1dB IIP3

Floor 6
 Dynamic range

Noise Floor = −174dBm + NF + 10 log BW

kT limitation Bandwidth

SFDR: Spurious free dynamic range

The input power range over which third order inter-modulation products
are below the minimum detectable signal level.

SFDR =
2
(IIP3 − Noise Floor ) − SNR min
3
BDR: Blocking dynamic range

BDR = P1dB − Noise Floor − SNR min

MDS: Minimum detectable signal level= Noise Floor +SNRmin

7
 Non-linearity

CP1dB: The input level at which the small signal gain has dropped by 1dB.

α1
CP1dB = 0.145 IMD3: The third order inter modulation term
α3

IP3: The metric third order intercept point. It is the point where the amplitude of
third order inter modulation is equal to the that of fundamental.

4 α1 IIP3: Input referred intercept point

AIP 3 =
3 α3 OIP3: Output referred intercept point

Pout − IMD3 = 2 ⋅ (IIP3 − Pin )

8
 MOS transistor
Intrinsic gate voltage and gm are the most important factors in RF CMOS.

Drain

rg vg’ Cgd rds D

G
Gate Body
Cgs Cds
gmvg’
Source S, B

MOS Transistor Equivalent Circuit

9
 Cutoff frequency: fT
For higher fT, increase gm and decrease Cin.

Ii Io
G fT: Frequency at which the current gain is unity.
D
Cin
Ii Vi gmVi Ii = Iio sin(ωt ) Input current
Iio
Vi = cos(ωt ) Gate voltage
S ωCin
gmIio cos(ωt )
Io = gmVi = Output current
ωCin
gm
∴ fT = Proportional to gm
2πCin Inversely proportional to Cin

10
 Amplifier gain
For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance

Ig Id
Log (G) 1 gm
ωg = ωT =
gmVg rsCin Cin
rs Cin
ro ωT r 0
Vs Vg G=gmr0 G≈ ⋅
ω rs
gmro r0
ω0 = = ωT
rsCin rs
1
For the larger gain
Log (f)
Ids
Fundamentally larger gmr0 G ≈ gmro ≈ ⋅ ro Larger Ids or ro
⎛ Veff ⎞
⎜ ⎟ Larger Q
Higher fT and lower rs ⎝ 2 ⎠
Q
Veff is difficult to reduce Qro = Qω0L =
ω0C
Æ Distortion and Cin increase
11
 Characteristics of gm (Basic)
Gm is proportional to the Ids and inversely proportional to the Veff.
Veff is proportional to square root of Ids and inversely proportional to
square root of (W/L) ratio.

Square law region Ids gm 1

gm = , =
⎛ Veff ⎞ Ids ⎛ Veff ⎞
μCOX ⎛ W ⎞ μCOX ⎛ W ⎞ ⎜ ⎟ ⎜ ⎟
Ids = ⎜ ⎟(Vgs − VT ) = ⎝ 2 ⎠ ⎝ 2 ⎠
2
⎜ ⎟Veff
2

2n ⎝ L ⎠ 2n ⎝ L ⎠
dI μCOX ⎛ W ⎞
gm ≡ ds = ⎜ ⎟Veff
dVgs n ⎝L⎠ 2n 1 L
Veff = ⋅ ⋅ ⋅ Ids
2 μCOX ⎛ W ⎞ μ Cox W
gm = ⎜ ⎟ Ids
n ⎝L⎠ Ids
Veff ∝ L = L ⋅ Jds Scaling W/L ratio
W
Veff is proportional to square root of drain current density.
12
Non-ideal effects to square low region
At larger Veff and lower Veff, two non-ideal effects are not negligible .

Low Veff Sub-threshold region 25.083

30

gm 1
= = const
⎛ Vgs ⎞ ( Weak inversion) 25 Ids nUT
Ids = Iso exp⎜⎜ ⎟⎟

Gm/Ids (S/A)
⎝ nU T ⎠ 20

Ids gm 1
gm = =
gm 2
eff( 0.4 , 10 , Veff)
=
15 Ids Veff
nU T Ids nU T eff( 0.2 , 5 , Veff)

10

High Veff Mobility degradation 5

μ0 μ
μ≈ , θ ≈ θ0 + 0 1.302 0

1 + θVeff
0.2 0 0.2 0.4 0.6 0.8
vcL 0.2 Veff
Veff (V)
1

This effect becomes larger at large Veff and short channel length.

13
 Distortion
Lower Veff gives higher gm, bur results in higher distortion.
To obtain lower distortion ( higher IIP3), we must increase Veff.
Higher gm and lower distortion means higher Ids.

1 d 3 Ids 4 a1
Ids = a1Veff + a 2Veff + a 3Veff
2 3
+ ⋅ ⋅ ⋅ ⋅ a3 ≡ IIP 3 =
6 dVeff 3 3 a3
100 10

L=0.1um
L=0.2um

gm/Ids (S/A)

IIP3 (V)
L=0.4um
IIP3 10 1

1 0.1
-0.1 0 0.1 0.2 0.3 0.4 0.5

Veff (V) Veff (V)

14
 LC resonator

LC resonator can be regarded as resistance at the resonance frequency.

C
L r0

1 Q
ω0 = ro = Qω 0 L =
Substrate
LC ω 0C

15
 Substrate effect
Substrate should be treated as resistive network.
This substrate resistance causes RF power loss and noise generation.
Shielding can reduce this effect.

Gate Shield layer

Gate

PAD PAD

D
S

S
D

D
S
S

RF power loss and noise generation 16

 Power loss in substrate
Very low resistance or high resistance realizes low power loss.

C Higher C and moderate Rsub

Gp Cp
results in higher power loss.
Rp
Equivalent
2
⎛ ω ⎞
⎜ ⎟
⎜ ϖ ⎟
G p =
1
⋅ ⎝ p ⎠
2
R p ⎛ ω ⎞
1 + ⎜ ⎟
⎜ ϖ ⎟
⎝ p ⎠
1 Gp(mS) 1
C p = C 2
⎛ ω ⎞
1 + ⎜ ⎟
⎜ ϖ ⎟ Cp(pF)
⎝ p ⎠
1 10 0.1
1 100
ϖ p = MOS: 10Ωcm
Rp(Ω） 1K 10K
R pC GaAs: 1GΩcm
17
 GHz operation by CMOS
The cutoff frequency of MOS becomes higher than that of Bipolar.
Over several GHz operations have attained in CMOS technology

0.13um fT : CMOS
gm
fT ≡
100G
0.18um fT : Bipolar (w/o SiGe)
50G
0.35um
0.25um
2πCin
fT /10 (CMOS )
Frequency (Hz)

20G
RF circuits vsat
10G fTpeak ≈
Cellular
CDMA 5GHz W-LAN fT /60 (CMOS ) 2πLeff
5G Digital circuits
Phone
2G

1G

500M IEEE 1394

D R/C for HDD
200M

100M
1995 2000 2005 Year

18
 Effect of parasitic capacitance to fT
fT of actual circuit is reduced by a parasitic capacitance.
There is an optimum gate width to obtain highest fT.
6 .10
10
60
5.786 .10
10
gm
fT ≡ Ids=5mA
2π (Cgs + Cgd + Cp ) Cp=0
L=0.2um
4 .10
4010
, W , 5 .10
3
gmVi
fti 0.2 ,0

fT (GHz)
Cp Cin Cp=0.1pF
Vi fti 0.2 , W , 5 .10
3
, 0.1 .10
12 (1)
fti 0.2 , W , 5 .10 , 0.5 .10
3 12

2 .1020
10
(2)
Cin=Cgs+Cgd
Cp=0.5pF
Region(1); Increased by increasing1.576
gm.109
00 0
Region(2); Decreased by increasing Cin 200 400 600 800 1000

1 .10
10 W 3
W(um)

19
 fT: MOS vs. Bipolar

Even if fT of MOS is the same as that of Bipolar,

fT of MOS is easily lowered by a parasitic capacitance.
Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current.
Small parasitic capacitance is a key for RF CMOS design.

MOS Bipolar
gm
Ids fT ≡ Ic
gm ≡ 2πCin gm ≡
⎛ Veff ⎞ UT
⎜ ⎟
⎝ 2 ⎠
kT
UT ≡ ≈ 26mV
Veff min = 2nU T n: 1.4 q
1 1
Veff/2: 50-100mV gmCMOS < , gmBip （Same operating current）
(actual ckt.) 2 4
1 1 （Same fT）
CinCMOS < , CinBip
2 4
20
 VT mismatch
VT mismatch degrades accuracy; ADC, OP amp, and Mixer.
Larger gate area is needed for small VT mismatch.
Scaling and proper channel structure improves mismatch.
15 Tox 0.4um Nch
ΔVT ∝
LW
ΔVT (σ:mV)

Tox Scaling
10
Larger gate area 0.13um Nch Boron w. Halo*
0.4um Pch
5 Channel engineering
0.13um Nch In w/o Halo*

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

1
( μm −1 ) * Morifuji, et al., IEDM 2000.
LW

21
 VT mismatch: Fluctuation of doping

Courtesy of Prof. Taniguchi, Osaka Univ.

ΔQdepl LWd depl N A 4 NA tox

ΔVT = = Atox = A′tox ≈ AVT
Cox LW LW LW
1
Q d depl ∝
NA AVT = 1V
-
- - - ddepl
-- - - -
- - - -
- - - - ---

基板 L = W = 0.25μ m, tox = 5nm

ΔVT = 20mV
T.Mizuno, J.Okamura and A.Toriumi, ”Experimental study o f threshold voltage
fluctuation due to statistical variation of channel dopant number in MOSFETs,”
IEEE Trans. On Electron Devices, ED-41, 2216 (1994)
22
 1/f noise
1/f noise of MOS is larger than that of bipolar.
For the lower 1/f noise, the larger gate area is needed.
Svf Δf
Vnf2 = , Svf ∝ Tox2
LW f
Nch/Pch 0.4um Nch 0.4um/1.0um
1E-13
Input referred noise voltage (V2/Hz)

1E-13

Input referred noise voltage (V2/Hz)

W/L=800/0.4 nMOS
Vdd=3V Vdd=3V
1E-14 1E-14 Id=1mA
Id=1mA

1E-15 1E-15

nMOS L=0.4um
1E-16 1E-16

pMOS 1E-17
1E-17 L=1.0um

2
1E-18 1E-18
Bipolar Bipolar

1E-19 1E-19
1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+02 1E+03 1E+04 1E+05 1E+06 1E+07

Frequency (Hz) Frequency (Hz)

23
 Noise figure: General

The lower Rnv and Gni realizes the better for a lower noise figure.

Zs Vn,rs Vng

Noiseless
Circuit
Vs Ing

Zs = Rs + jXs

Vng 2 = 4kTRnv , Ing 2 = 4kTGni

Vn2,rs + (Vng + ZsIng )

2 2
Rnv Zs Gni Rnv
F= = 1+ + ≈ 1+ + RsGni
Vn2,rs Rs Rs Rs

Vng Rnv
Rsopt = = F min ≈ 1 + 2 RnvGni
Ing Gni
24
 Noise figure: MOS transistor

Rnv
F ≈ 1+ + RsGni
Rs
gm ⎛ ω 0 ⎞
2
W 1 1
Rnv = Rg + Rgs Rg = Rsr tot Rgs ≈ Gni ≈ ⎜ ⎟
L 3N 2 5 gm 5 ⎝ ωT ⎠

gm ⎛ ω 0 ⎞
2

F ≈ 1+
1
+ Rs 1 ⎛ ωT ⎞ 1
⎜ ⎟ Rsopt ≈ ⎜ ⎟ =
Rs5 gm 5 ⎝ ωT ⎠ gm ⎝ ω 0 ⎠ Cgsω 0

ω0
F min ≈ 1+ 2
ωT

25
 Low noise amplifier design

Narrowband LNA uses inductor degeneration for impedance matching.

Impedance matching

⎛ gm ⎞
Zin ≈ s(Ls + Lg ) +
1
+⎜ ⎟ L s ≈ ωT L s
sCgs ⎝ Cgs ⎠
1
ω0 =
Cgs (Ls + Lg ) M2
Z0
Lg rg
M1
Cpi

Cgs rgs
Rsub Ls

26
 Low NF design

rgs + rg ⎛ ω0 ⎞ rgs + rg
2

F ≈ 1+ + 4γgmZ 0⎜ ⎟ ≈ 1 + rgs ≈
1
Z0 ⎝ ωT ⎠ Z0 5 gm
Low noise figure Wtot 1
rg = Rsr
L 3N 2
1) Lower the gate resistance
Wtot
Dived the gate or lower the gate sheet resistance rg = Rsr
L
2) Reduce substrate loss Rsr: Sheet resistance
N：The # of division
Reduce parasitic capacitance Divide the gate

Use shield technique to the input bonding PAD. S

D D
Use high resistive substrate, if possible.
S
S
3) Increase drain current
rgs ≈
1
≈
(Veff ) D
S
4) Increase Z0, if possible. 5 gm 10 Ids
27
 Ids and Veff optimization
Adjust the Ids and Veff for optimization of gain, noise and distortion.
Dynamic range of LNA is proportional to Ids.

IIP3LNA
DRLNA ∝ ∝ gmZ 0Veff ≈ IdsZ 0 IIP3 ∝ Veff
F −1
Higher Ids
Lower Ids
NF
dB

Gain

3rd distortion

Ids
Veff ∝
W
Veff
28
 NF progress in MOS LNA
NF of MOS LNA is reaching 1dB.
8.0

7.0

6.0

5.0

4.0
NF (dB)

3.0

2.0

1.0

0.0
1 0.5 0.35 0.25 0.1
Gate length (μm)
29
 Mixer
Mixer converts frequency, but image signal is converted to the same frequency.

Vs
Vs = As cos(ωst )
Vo
cos((ωs ± ωLO )t )
2
Vo = As
π
If VLO>>4Veff (Full swing)
VLO
VLO = ALO cos(ωLOt )
RF spectrum
IF spectrum
FLO
dB dB
Fimage
Fdes

Freq Freq
FIF FIF FIF
30
 Image-reject mixers
The quadrature mixing realizes image-suppression.
Gain and phase matching is needed.

LPF 45°

Vin (t) cos(ωLOt ) Vout(t)

+
sin (ωLOt )

LPF − 45°

Vin (t ) = Ades cos(ωdest ) + Aim cos(ωimt )

Vout (t ) = AdesAc cos(ωIFt ) + AimAcIR cos(ωIFt )
Ac: Conversion gain, IR: Image rejection
IR=0 if I/Q phase difference is 90° and Channel conversion gains are equal.

31
Gain mismatch and phase error

Pspur 1 + γ 2 − 2γ cos φ γ : Gain ratio

=
Pdesired 1 + γ 2 + 2γ cos φ
φ :Phase error

A. Rofougaran, et al.,
IEEE J.S.C. Vol.33, No.4,
April 1998. PP. 515-534.

32
 Passive FET mixer
MOS can realize a passive mixer easily.
Ultimately low power, but take care of isolation.

Passive FET mixer

Vin
Low power
High linearity
Lo No 1/F noise
Lo
Vo No conversion gain
Vo
No isolation, Bi-directional
Lo Lo

Vin
33
 Active mixers

Single balanced mixer Double balanced mixer

Very small direct feed through and even order distortion

ZL ZL ZL ZL
Vo Vo Vo
Vo
Lo Lo
M2 M3
M2 M3 M2’ M3’
Lo Lo Lo
Vin
M1 Vin Vin
M1 M1’
Zs
Zs Zs

34
 Active mixer design
The larger Ids is needed for high dynamic range
and shorter switching time for low 1/f noise.
2 2 ZL
Mixer gain Gmix = gm1ZL , or = when Zs is used
π π Zs
R : Resistive component in ZL
Thermal noise v = 8kTRL⎛⎜1 + 2γIRL + γgm1RL ⎞⎟ ≈ 8kTR 2γgm1
L
2

⎝ πALO
on L
⎠
v on2 γ Veff
SSBvin =
2
2
≈ 2π 2
kT ≅ π 2
kTγ
⎛2 ⎞ gm1 Ids
⎜ gm 1 R L ⎟
⎝π ⎠
A larger dynamic range needs larger current
IIP3 ≈ Veff
1/F noise
4Ts
1) Switch transistor (M2, M3) vn , o = vn , sw Ts
TLO
TLO
1 1
vn2 , sw ≈ WL ∝
Cgs
Phase modulation

Shorter switching time or larger Ts/TLo ratio

2) Load transistors Directly produces
35
 Oscillator
There is an optimum Ids for low phase noise.
Vdd

Vo L L Vo Q C
L
r0
-1/gm -1/gm
C C
Vc Q
ro = Qω 0 L =
1) Amplitude condition ω 0C
M2 M3
4 Iro
Oscillation Vosc = Headroom 2Vdd
Vb
amplitude π limit

I M1 πVdd πVddωoC
Iopt = =
2 ro Q
(a)
2) Oscillation condition
2 ωoCVeff , 2,3
gm 2,3 > , I>
ro Q
36
 Phase noise of oscillator
Phase-frequency relation and resonator characteristics determine phase noise.

v(t ) = A cos[ω 0t + φ (t )]
1 2QL
=
Bw ω 0
dφ
R ωm = = jωφ ωm : Offset angular frequency
dt
Z ( jω )
Sω (ωm) = ωm2 Sφ (ωm )
0.7R Bw
Sω (ωm) :Noise spectrum density
on offset angular frequency

ωm 2QL Sφ (ωm ) :Noise spectrum density

on phase
Δθ = = ωm
ω Bw ω0 Δθ Phase error between in and out

SΔθ (ωm )
:Noise spectrum density
2QL
φ dφ =
ω0
dω 2
on phase error
⎛ ω0 ⎞
Sω (ωm) = ⎜⎜ ⎟⎟ SΔθ (ωm ) ωm < Bw
ω ⎝ 2QL ⎠
ω0 ⎛ ω0 ⎞ 1
2
⎛ ω0 ⎞
2

Sφ (ωm) = ⎜⎜ ⎟⎟ 2 SΔθ (ωm ) = ⎜⎜ ⎟⎟ SΔθ (ωm )

⎝ 2QL ⎠ ωm ⎝ 2QLωm ⎠

37
 Phase noise of oscillator

ω0L ωm << ω 0
Z (ω 0 + ωm ) ≈ j
Q C ωm
L 2
-1/gm -1/gm
r0
r0 ω0 (Filter action)
Q=
ω0L
r 0ω 0
Z (ω 0 + ωm ) ≈
2Qωm
1 2Q
=
Bw ω 0
2
vn2 in2 ⎛ ω0 ⎞
= ⋅ Z = 4kTro⎜⎜ ⎟⎟
2
R
Δf Δf ⎝ 2Qωm ⎠
Z ( jω ) 0.7R Bw
Noise spectrum density

⎡ 2kT ⎛ ω0 ⎞
2
⎤
L{ωm} = 10 log ⎢ ⋅ ⎜⎜ ⎟⎟ ⎥
ω ⎢⎣ Psig ⎝ 2Qωm ⎠ ⎥⎦
Phase noise
38
Frequency characteristics of Phase noise in oscillator

1/f noise and thermal noise is converted to 1/f3 and1/f2, respectively.

Sφ (ωm )
2 2
⎛ ω0 ⎞ ⎛ 1 ω0 ⎞
SΔθ (ωm ) =
1 a
⎜⎜ ⎟⎟ a 3 Sφ (ωm) = ⎜⎜ ⎟⎟ SΔθ (ωm )
⎝ 2QL ⎠ ωm ωm ⎝ 2QL ω m ⎠
Phase noise spectrum

-9dB/oct 2
SΔθ (ωm ) =
⎛ ω 0 ⎞ 2 FkT 1 2 FkT
(Slope =-3) ⎜⎜ ⎟⎟
⎠ Ps ωm Ps
2
⎝ 2QL

2 FkT
-6dB/oct
Ps
(Slope=-2)
1/f noise Thermal Thermal

ωco Bw =
2QL
ωm
ω0

39
 Up and down converted noise

Noises around N*fo are up and down converted to fo.

Vnoise (V / Hz )

ω
ωo 2ωo 3ωo
Noise
shaping

Up-conv. Down-conv.
P (dBm)

40
 FoM and minimum phase noise

FoM is basically proportional to Q2.

2
⎛ f 0⎞ 1 Fm: Offset frequency
FoM = ⎜⎜ ⎟⎟ L(fm): Phase noise at offset freq.
⎝ fm ⎠ L( fm)VddI
2 2
1 1 ⎛ fo ⎞ FkT 1 1 ⎛ fo ⎞ FkT F: Noise factor
L ( fm ) = ⋅ 2 ⋅ ⎜⎜ ⎟⎟ ⋅ = ⋅ 2 ⋅ ⎜⎜ ⎟⎟ ⋅
⎝ fm ⎠ PRF 2 Q ⎝ fm ⎠ ⎛⎜ Vo ⎞⎟
2
2 Q
⎜ 2ro ⎟
⎝ ⎠
8γroI 8 πVdd πVddωoC πVdd
F = 2+ + γ ro ⋅ gm1 Iopt = = =
πVo 9 2 ro Q 2QωoLind

4 Q2 1
FoM = ∝ Q2 at Iopt
π kT 2 + 4γ + 32 γπ Vdd
9 Veff ,1
41
 Oscillator design
Careful optimization reduces the oscillator phase noise.
2
γ ωoLind ⎛ 1
2 ⎞⎛ fo ⎞
L min( fm) = kT ⋅ ⋅ ⋅⎜ + ⎟⎜⎜ ⎟⎟
Vdd 2Q ⎝ Vdd Veff ,1 ⎠⎝ fm ⎠ Phase noise Oscillation
amplitude
2
γ 1 ⎛ 1 2 ⎞⎛ fo ⎞ 2Vdd
L min( fm) = kT ⋅ ⋅ 2 ⋅⎜ + ⎟⎜⎜ ⎟⎟
2 Iopt 2Q ⎝ Vdd Veff ,1 ⎠⎝ fm ⎠
πVdd πVddωoC πVdd
Iopt = = =
Vo L L Vo 2 ro Q 2QωoLind
Iopt Bias current
Vc
C C Larger Vdd
Large Veff1, but take care of Vo reduction
Large L1, W1 to reduce 1/f noise
M2 M3
Enough W/L for M2, M3
Higher Q
Vb
I M1
Larger QLind for Lower Iopt

42
 CMOS oscillator circuits

E. Hegazi, ISSCC 2001

Basic Low power (gm is higher) Low noise by filtering

Vo L L Vo
Vo Vo
Vo L L Vo
L L C C
Vc
C C C C
Vc Vc

Hi-Z at 2fo
Cs Lx
Vb Vb
Vb
Cx
(a) (b)
(c)
43
 Filtering of 2fo component in OSC.

Noise filtering of 2fo component reduces the OSC phase noise to -10dB.

E. Hegazi, ISSCC 2001

44
 Oscillator phase noise progress

Phase noise in CMOS oscillator becomes lower than that of bipolar.

◆CMOS

-90.0 ■Si-bipolar/BiCMOS
▲SiGe-BiCMOS
[dBc/Hz](@１GHz,10mW,600kHz)

-100.0
SSB Phase Noise

-110.0

-120.0

-130.0

-140.0

-150.0
1994 1995 1996 1997 1998 1999 2000 2001 2002
Year
45
 Acknowledgment and references
• Acknowledgment
I would like to thank Prof. Asad Abidi in UCLA for his advices.

• References
– Asad A. Abidi, “Power-Conscious design of Wireless circuits and
systems,” pp.665-695, “Trade-offs in Analog Circuit Design,” Kluwer
Academic Publishers, 2002. (Edited by Chris Toumanzou, George
Moschytz, and Barrie Gilbert)
– Thomas. H. Lee, “The design of CMOS RF ICs,” Cambridge University
Press, Jan. 1998.
– Bezad, Razavi, “RF micro-electronics,” Prentice Hall, Nov. 1999.
– Domine Leenaerts, Johan van der Tang, and Ciero Vaucher, “Circuit
Design for RF Transceivers,” Kluwer Academic Publishers, 2001.
– Charles Chien, “Digital Radio Systems on A chip,” Kluwer Academic
Publishers, 2001.
– E. Hegazi, et. Al., ”A Filtering Technique to Lower Oscillator Phase
Noise,” ISSCC 2001, 23.4, Feb. 2001.

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