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It all started with the Basic Audio Amplifier. This is roughly the minimum number of
components that represents the classic audio amplifier topology. You can clearly see the three
stages found in many audio amps (and op amps today). However, looking at actual audio
designs, you'll find the basic topology has been tweaked and enhanced in a few key locations.
We've already covered many of the modifications to each stage individually. But, this is where
we put it all together into the advanced audio amplifier.
THE IMPROVEMENTS
Here's a quick tour of design improvements of the audio amplifier. There's an enhancement for
each of the three stages: Differential, Voltage Gain, Output Buffer. Why bother messing with
the design? Higher gain and better output drive lead to a lower distortion performance. Click on
the links below to find out more.
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Current Mirror The Current Mirror (Q8,Q9) doubles the gain of your differential
amplifier. It also balances the current in each transistor (Q1, Q2)
nicely. Both high gain and balancing helps lower the overall
distortion.
Active Load Replacing the collector resistor of the gain stage (Q3) with an
Active Load (Q10) raises the voltage gain and provides better
current drive to the positive half of the output buffer.
Darlington Output Driving a low impedance like 8 ohms demands a lot of current
Buffer from the output buffer. A Darlington Output Buffer helps deliver
the current and minimize the load on the gain stage. This keeps
the overall gain high and the distortion low.
AMPLIFIER ANALYSIS
Let's step through a simple audio amp with a signal gain of 10 V/V (20 dB). We'll run it from a
+/- 15V supply.
DC BIAS
First, what is the bias current of Q1 and Q2? The current through RE splits into Q1 and Q2,
so we calculate
CLOSED-LOOP GAIN
The feedback resistors (RF1, RF2) determine the close-loop signal gain from input (V2) to
output (V20).
AC SMALL-SIGNAL BANDWIDTH
The unity gain bandwidth of the open-loop amplifier is determined by gm1 and CC.
The low frequency bandwidth is set by one of two high pass filter cutoff frequencies, which
ever is higher
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SLEW-RATE
Finally, for big input signals, how fast can the output change? It's determined by the max
current available Ibias in the differential amplifier and CC.
Slew = Ibias / CC
= { (VCC - VbeQ1) / RE } / CC
= { (15 - 0.7) / 14.3k } / 500 pF = 2 V / us
Excel Spreadsheet Here's a handy file that performs the above calculations:
Advanced_Amplifier.xls.
Let's start with the basics. Feed a 1V @ 1kHz signal into the input and check the amplifier's
gain of 10.
CIRCUIT INSIGHT Run a Transient Analysis. Plot the input V(1) and output V(20). Does the
output swing +/-10V as expected?
CIRCUIT INSIGHT Let's check the bandwidth. Does it meet the 600kHz calculated above?
Run an AC Analysis and plot the output V(20). What happened to the bandwidth? It seems to
have fallen dismally short of 600 kHz!!! Turns out, the problem lies in the output stage. Because
it's biased class B, the output transistors are essentially OFF when the output is near 0V.
What's the remedy? I've snuck in a voltage source VOFF at the base of Q2. A small voltage here
will offset the output by the same voltage. Hopefully, a few tenths of a volt will turn ON the
output stage. Temporarily set VOFF to 0.5V and rerun the AC analysis. How high is the
bandwidth now? Set VOFF back to 0V when finished!
DISTORTION
With a 10V output at 1kHz, the transient output V(20) looks undistorted. But let's give it a
closer look at a lower amplitude and higher frequency.
CIRCUIT INSIGHT Set VS to 0.1V at 10 kHz and shorten the transient analysis to 0.2 ms.
Rerun the Transient Analysis and check out the output V(20). What happened to our pretty sine
wave? You can see the output struggles to swing through 0V. That's because the voltage across
R10, D1 and D2 is smaller than the four Vbe junctions output transistors creating a dead-band
when the output transitions from one polarity to another. For more on this cross-over distortion
see the Output Stage.
HANDS-ON DESIGN Try increasing R10 from 100 ohms to 200 ohms. This increases the bias
voltage across the 4 output stage transistors. Rerun the simulation and check the distortion.
Keep increasing R10 until the visible output distortion is minimized.
SLEW-RATE
Why care about slew rate at all? Suppose you need to amplify a 20 kHz sine wave at 10V, this
requires a minimum slew rate of 10V*2*pi*10kHz = 1.25 V/us if you want to faithfully pass the
signal. Otherwise, distortion occurs because the output cannot rise as fast as the sine wave's
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leading edge.
Let's see how fast the output can swing. To do this, raise the gain from 10 to 100. This should
drive the output from one rail to the other. You can then measure the rate at which the output
rises and falls.
CIRCUIT INSIGHT Set VS to 0.1V at 10 kHz with transient analysis time of 0.2 ms. Then
raise the gain to 100 by increasing RF2 to 99k. Run a Transient Analysis and plot the output V
(20). For the negative slew rate, find the time it takes Vo to fall from +5V to -5V. It's
approximately 5.1 us for a negative slew rate of Slew- = -10V/5.1us = -1.96 V/us. How fast
does Vo rise from -5V to +5V? We measure 6.1 us for Slew+ = +1.64 V / us. The equations did
a reasonable, but not perfect, job of predicting slew rate. Overall, looks like we've got sufficient
speed to pass the 10V sine wave at 20kHz.
HANDS-ON DESIGN How could you raise the slew rate is needed? From the equation
Slew = Ibias / CC
you could either raise Ibias (by decreasing RE) or decrease CC. Try either and rerun the
simulation. Did you get a higher slew rate as expected?
AUDIO TOPICS
Here's a round up of the audio topics spanning the audio amplifier. The subject of audio design
is lovely, dark and deep with many more topics (noise, heat, etc) than covered here. But this
should build a decent foundation of audio amplifiers.
Output Stage
SPICE FILE
Download the file or copy this netlist into a text file with the *.cir extension.
* POWER SUPPLIES
VCC 100 0 DC +15V
VEE 101 0 DC -15V
*
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VS 1 0 AC 1 SIN(0 1V 1KHZ)
CIN 1 2 20UF
RIN1 2 50 1K
VOFF 50 0 DC 0.0V
*
* FEEDBACK
RF2 20 3 9K
RF1 3 24 1K
CF1 24 0 20UF
*
* DIFF AMP
RE 100 6 14.3K
Q1 4 2 6 QMPSA56
Q2 5 3 6 QMPSA56
*
* CURRENT MIRROR
Q8 4 5 101 QMPSA06
Q9 5 5 101 QMPSA06
*
* GAIN STAGE AND COMPENSATION
Q3 14 4 101 QMPSA06
CC 14 4 500PF
*
* BIAS DIODES
D1 100 7 D1N4148
D2 7 8 D1N4148
RB10 8 0 15K
* BIAS RESISTOR AND PNP ACTIVE LOAD
RE10 100 9 650
Q10 10 8 9 QMPSA56
*
* OUTPUT STAGE BIAS
RB11 10 11 100
D11 11 12 D1N4148
D12 12 14 D1N4148
*
* OUTPUT STAGE
Q4 100 10 22 QMJE340
Q6 100 22 20 QTIP31
Q5 101 14 23 QMJE350
Q7 101 23 20 QTIP32
RE4 22 20 500
RE5 23 20 500
*
* LOAD
RL 20 0 8
*
*
* DEVICE MODELS
.model Q2N3904 NPN(Is=100.9f Xti=3 Eg=1.11 Vaf=115.7 Bf=278 Ne=1.894
+ Ise=14.35p Ikf=.1594 Xtb=1.5 Br=.118 Nc=2 Isc=0 Ikr=0 Rc=.6
+ Cjc=4.929p Vjc=.75 Mjc=.3333 Fc=.5 Cje=7.707p Vje=.75
+ Mje=.3333 Tr=290.3n Tf=296.5p Itf=.2 Vtf=10 Xtf=2 Rb=10)
* DEVICE MODELS
.model D1N4148 D(Is=0.1p Rs=16 CJO=2p Tt=12n Bv=100 Ibv=0.1p)
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.PROBE
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.END
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