Sei sulla pagina 1di 1
ppwl:[0,1,0.0001m,1,8.3329m,1,8.333m,0,16.6659m,0,16.666m,1] c_ppwl mult + in1 Control to Voltage - var2v in
ppwl:[0,1,0.0001m,1,8.3329m,1,8.333m,0,16.6659m,0,16.666m,1]
c_ppwl
mult
+
in1
Control
to
Voltage
-
var2v
in
out
c_sin
in2
Sample-Hold
gate
gnd
+ Voltage
to
Control
- Interface
comp_l4
v_ppwl
v2var
amplitude:170
frequency:60
ppwl:[0,0,9.9999u,2.7,10.00u,0]
enbl
c_constant
enbl
in1
out
Σ
in1
out
comp_l4
Σ
+1
+1
in2
integ
-1
v_ppwl
v_ppwl
in2
mult
mult
k:0.5
1
in1
out
in1
k
in1
Σ
+
s
+1
ppwl:[0,1,5u,0,10u,1]
Control
ppwl:[0,0.95,5u,-0.05,10u,0.95]
to
Voltage
-
in2
in2
k:1
in2
-1
var2v
lag
+
in
out
+ Voltage
in1
Control
K
Sample-Hold
to
to
Control
Voltage
(s/w) + 1
-
- Interface
gate
gnd
in1/in2
in1
out
in2
Σ
var2v
v2var
+1
v_ppwl
in2
2
enbl
in1
out
in1
out
in1
ppwl:[0,0,9.9999u,2.7,10.00u,0]
Σ
Σ
+
comp_l4
Control
in1/in2
to
in1
out
in2
+1
+1
Voltage
integ
integ
Σ
-
in2
in2
mult
mult
mult
mult
1
1
in1
out
in1
out
var2v
Σ in1
k
in1
in1
k
in1
+1
Σ
in2
s
s
2
+1
+1
in2
k:1
in2
in2
in2
in2
k:0.5
in2
-1
-1
2.2u
enbl
comp_l4
lag
+
in
out
v_ppwl
v_ppwl
Control
+ Voltage
K
Sample-Hold
to
to
10
Control
Voltage
(s/w) + 1
-
- Interface
gate
gnd
40
in
out
ppwl:[0,1,5u,0,10u,1]
ppwl:[0,0.95,5u,-0.05,10u,0.95]
Sample-Hold
var2v
v2var
6.8u
gate
gnd
sw1_l4
v_ppwl
+
Voltage
to
v_ppwl
Control
ppwl:[0,0,0.9999u,2.7,1.00u,0]
-
Interface
v2var
ppwl:[0,0,9.9999u,2.7,10.00u,0]
100u
1m
1m
50u
200n
1m
100m
1.5u
6.8u
40
D1
22n
pp
DC/DC
sp
+
v_dc
Voltage
100
to
Control
Interface
-
n1:1
n2:2
v2var
v_dc
pm
sm
+
in
out
Control
+ Voltage
Sample-Hold
to
to
Control
Voltage
-
- Interface
gate
gnd
var2v
v2var
v_ppwl
ppwl:[0,0,0.9999u,2.7,1.00u,0]
enbl
comp_l4
v_ppwl
ppwl:[0,1,55.999m,1,56m,0,399.999m,0,400m,1]
v_dc
1m
comp_l4
enbl
v_ppwl
ppwl:[0,1,55.999m,1,56m,0,399.999m,0,4000m,1]
v_dc
1m
sw1_l4
20m
10m
2.5u
sw1_l4
pwld
143p
22
5n
+
Voltage
to
Control
Interface
-
v2var
100u
400n
v2var
-
Voltage
to
Control
Interface +
143p
sw1_l4
pwld
22
5n
4.4u
50