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Physics and Current Technology in Flash Memory

Ryan Rausch and Andy Thompson

April 15, 2005
ECE 3611 Introduction to Solid-State Semiconductors
University of Minnesota Duluth
Instructor: Dr. Stanley G. Burns


Flash memory has evolved over the last forty or so years in response to a desire for
electrically controlled computer memory. It began in the late sixties as Programmable
Read-Only Memory, which later was developed into Erasable, then Electrically Erasable
Programmable Read-Only Memory. Flash memory integrated advantages from all of
these types of memory and has proved to be a lucrative and useful component in todays
Flash memory is a MOS structure that acts as a memory cell by storing charge in a
floating gate. This charge can be programmed by hot carrier injection or by carrier
tunneling, and erased through tunneling. The charge affects the current in the device
which can be read as data.
Flash is everywhere, embedded in microprocessors and around our necks in the form of
usb flash disks. The two major types are NAND and NOR which have distinct
advantages and disadvantages. Flash can be improved by using better materials and
processes but will reach physical limits. Flash will come to physical limitations around
2007 and the need for new non-volatile memory will arise.
Five Main Points to Present:

1. What is non-volatile memory? Non volatile memory is solid-state non-

mechanical memory that does not lose its data when disconnected from a power
supply. Examples of this memory would be from PROM to the current Flash
2. Progression leading to Flash EEPROM: Non-volatile memory started out with
floating gate MOS devices that created Programmable Read-only Memory
(PROM). Later, this was developed to Erasable PROM (EPROM), then to
Electrically Erasable PROM (EEPROM), and finally Flash EEPROM. Each
progression from the desire for electrically controlled devices, and Flash was able
to do so with a smaller cell size.
3. Device Physics: How do they store data? Flash memory programs data
through either Hot Carrier Injection or Fowler-Nordheim Tunneling. Data is
typically erased through Fowler-Nordheim Tunneling, and data is read by the
deviations in the current flow through each memory cell.
4. Comparison of current technologies: There are many devices which rely on
non-volatile memory. The main types are the removable and embedded memory
chips. Depending on applications the flash memory will either be NAND or NOR
memory. The NAND and NOR have their own traits which make them suited for
certain applications where their counterpart may not be as good of a choice.
5. Limitations of flash: Looking to the future. : Flash has limited erase cycles,
limitations on device oxide thickness due to the high voltage (about 10 volts)
required to write to the memory cell, and limitation in the feature size (about
45nm by 2007). The solutions have been adding multiple bits per cell to double
capacity but scaling issues are still there even with the advancements of better
materials. New types of non-volatile memory are being developed to overcome
the obstacles that have plagued flash such as limited write cycles (MRAM) and
the ability to have a RAM like non-volatile memory such as the NOR but with
storage capacity and bandwidth as the NAND (FRAM). And others such as 3DM
and Ovonyx Unified Memory are being developed to replace the industry giant.


Computer memory can be divided into two main groups: volatile and non-volatile. An
example of volatile memory is RAM (random access memory), which loses its data every
time that the power connected to the device is removed. Non-volatile memory does not
lose its data when powered off. An example of this type of memory is ROM (read-only
memory). There are different types of ROM, the earliest being PROM (programmable
ROM). This type could be programmed once, and couldnt be changed. In the late
sixties, researchers proposed the first floating gate MOS devices [1]. This discovery
lead to EPROM (erasable PROM), later EEPROM (electrically EPROM), and finally
Flash EEPROM, which is the main focus of this paper.
Figure 1: Floating gate MOS structure [1]

With this floating gate, shown in Figure 1, the

gate is electrically isolated by the SiO2 and
effectively traps charge, which can be
interpreted as data in a memory cell. With
early EPROM, the only way to erase this
trapped charge was to excite it through UV
radiation. This posed a problem, however,
since the chip would have to be taken out of the
system and exposed to the radiation. Designers
have created chips with quartz windows so the UV radiation can enter the chip more
easily, but the chips are costly. Cheaper plastic casing EPROMs exist but are not easily
erasable [1].
Figure 2: EEPROM with Select Gate [1]
When researchers realized the potential
of an electrically erasable memory, they
produced a design with both a floating
gate and a select gate, shown in Figure
2. The control gate interfaced with the
rest of the circuit, the floating gate
stored the data, and the select gate
selected or deselected the cell for
programming or erasure. The main
problem with this design was that because of the extra transistor, the memory cells were
two to three times larger, causing less memory density [1].

The solution to these problems came along in Flash EEPROM, which came along in the
1980s. Flash memory is electrically erasable, yet does not require a large area as
previous EEPROM devices had. This is because Flash memory uses a structure like
shown in Figure 1, with one transistor. The difference is instead of using UV radiation to
excite the charge carriers, the device utilizes a tunneling process. This will be discussed
in the proceeding section on device physics.

Device Physics

As mentioned before, Flash memory devices program and erase data electrically. There
are multiple approaches to these processes: Hot Carrier Injection (HCI) and Fowler-
Nordheim (FN) Tunneling. Both methods can be used for the program cycle; typically,
FN Tunneling is used for the erase cycle [1]. This section will explore the physics of
how these methods work.
Figure 3: Energy band diag. for HCI
programming [1]
The Hot Carrier Injection programming process
is depicted in Figure 3 to the right. In this
process, a high voltage is applied to the drain
with the source grounded. This creates a strong
electric field, which in turn excites the carrier to
the point of surmounting the high energy barrier
of the gate oxide. Since holes have less
mobility, they take much longer to acquire the
required energy, and the device timing is slow.
As a result, most memory devices are n-type on
a p-substrate. Once the voltage is removed, the
electron that had passed into the floating gate is
trapped there until it is removed by an erase
cycle. Figure 6 below gives a visualization of
how the charges move within the device.
Figure 4: Energy band diag. for FN
tunneling programming [1]
In the Fowler-Nordheim tunneling
programming process (shown in Figure 4), a
high positive voltage is applied to the control
gate with the source grounded and a smaller
voltage on the drain [1,2]. The substrate
band bends up, and the potential barrier
between the substrate and floating gate
decreases. This allows the carriers to tunnel
into the floating gate, where they are trapped
once the voltage is removed. An equation for
the tunneling current density is as follows
q3m 4 2m *b3 / 2
J Einj e^ (
8hb m * Einj q
Einj = E-field at injection surface;
m = mass of e-; m* = effective mass of e-;
b = Energy barrier; h = planks constant; = h/(2); q = electronic charge
Figure 7 below gives a visualization of how the charges move within the device.

Figure 5: Energy band diag. for FN
tunneling erasing [1]
In the Fowler-Nordheim tunneling erasing process
(shown in Figure 5), a high negative voltage is
applied to the control gate with the drain grounded
and a smaller voltage on the source [1,2]. Now, the
substrate band bends down, and the potential barrier
decreases again, and the carriers tunnel back into the
substrate again. Now there is little or no charge left
in the floating gate and the memory is erased.
Figure 8 below gives a visualization of how the
charges move within the device.

The preceding tunneling techniques are called drain-side tunneling, because of the small
voltage bias on source or drain. Since the tunneling is isolated to one side, there is a
smaller current density, and the process is much faster. However, it is less reliable. A
more reliable, but slower approach is called uniform tunneling, where rather than having
a bias voltage, both source and drain are grounded, and the high voltage on the gate is
slightly higher [1]. Below are depicted the various programming and erasing techniques,
to give an idea of how the carriers move within the device.

Figure 6: Hot Electron Injection

Programming Method

Figure 7: FN Tunneling Drain-Side Figure 8: FN Tunneling Drain-side

Programming Method Erasing method

Figure 9: FN Tunneling Uniform Figure 10: FN Tunneling Uniform
Programming Method Erasing Method

Just to note: in the above figures for the drain side methods, it is shown that both erasing
and programming have a bias voltage on the drain. Earlier, it was discussed that erasing
was done by biasing the source. This is a result of conflicting sources. According to
Matwana and Schroeder [1], the bias is on the drain both times. According to Otsuka and
Horowitz [2], the source is biased for erasure. A table from this source is shown in
Figure 11. Therefore, the bias must be allowed on either source or drain, but is more

beneficial on one or the other depending on the device. The evidence is not totally
conclusive, but does seem to support this argument.
Figure 11: Table of Contact Voltages [2]
The read cycle is less complex, and doesnt require
tunneling. This also means it does not require such
a high voltage, as can be seen in Figure 11 to the
left. The extra carriers in the floating gate changes
the current in the device, and with a current-
detecting circuit, the differing current levels
traveling through the cell can be interpreted as data.

Current available technology

In current market place there are many types of flash memory available to the consumer.
Consumers use flash memory in such devices as their cell phones, pdas, digital cameras,
mp3s and so on. Almost everything that requires the ability to store digital data even
when the power source has been removed uses some sort of flash memory.

Flash memory comes in two types the embedded and the external. Embedded flash
memory is memory that has now replaced the EEPROMS because of lower price and a
longer lifetime is associated with flash memory. The other type of flash memory is the
type that most people are more familiar with, this is of course the removable flash.
Removable flash are the SD cards, MM cards, compact flash, xd, memory sticks, and usb
flash drives are the most common of the consumer flash media that are available.

The above picture from the left to the right pny technologys 512 Mb usb flash, 512 Mb
compact flash and 512 Mb secure digital flash memory chips. All of these different types
of flash media weather embedded or removable are of two distinct types with their own
advantages and disadvantages. These two types of flash technology are NOR and NAND

The question of which type of flash is better NAND or NOR is somewhat debated due to
clear advantages depending upon what type of application is being used. NAND based
solutions are ideal for high capacity data storage, while NOR is best used for code storage
and execution, usually in small capacities.

When it comes to performance of the NOR and the NAND technology the main
differences are in the read and write cycles, interface and the storage capacity.

As far and the read cycle NOR reads slightly faster than the NAND but NAND writes
much faster than NOR. The NAND erases astoundingly faster than NOR (3ms max
compared to 5s). The speed of the erase time is critical to the write time because in flash
memory in order to write to a specific block of memory it must first be erased. Flash
devices are divided into erase units, also called blocks. In NAND devices an erase
operation is straightforward, NOR devices require all bytes in the block to be written with
zeros before they can be erased. The size of erase blocks in NOR devices ranges from
64KByte to 128KBytes (in NAND: 8KByte to 64KBytes), such a write/erase operation
can take up to 5 seconds. A NAND performs the identical operation in 3msec
maximum. The difference in the block size makes NOR use more erase operations than
that of NAND with any given set of write operations.

As for the interfaces of the NOR and the NAND the NOR has been well established and
used for the past 10-15 years whereas the NAND is very complicated and required
additional software to check for errors. A different code design methodology is usually
not a favorable step to take when the standard technology (NOR) will do. However,
there will come a time when an alternative to the NOR flash will need to be replaced for
certain applications and the tradeoff will be more functionality at a cost of more difficult
code design. NOR flash acts like a random access memory device (RAM). There are
enough address pins to map its entire media, which allow easy access to all of its bytes.
NAND devices are interfaced serially with a complicated I/O interface. The I/O interface
may vary from one device to another depending on the vendor. It uses the same eight pins
as control, address and data information. NAND is typically accessed in bursts of 512
bytes. This means that 512 bytes can be read and written at a time (similar to hard
drives). This makes NOR ideal for running code, while NAND is best used as a data
storage device.

The storage capacities are the last big difference between the NOR and the NAND
memory. The image below shows the architecture for the NOR and NAND chips.

The picture shows that the NAND cell is almost half the size than that of the NOR cell.
The smaller cell size and the simpler production process associated with the NAND
architecture yields larger densities and with more capacity on any given die size. The
image below illustrates this effectively.

It is seen in the industry that NOR dominates the market in ranges of 1MB to 4MB
(32MB and larger are available), while the NAND ranges form 8MB to 512MB
commonly and reaching even higher capacities. This shows again that NOR devices are
typically used for code storage while NAND devices are much better suited for large data
storage applications.

Looking to the future

There are definite limitations to the current flash technology which mostly involve the
size limitations and the write capacities of the specific devices.

The flash memory weather it be NOR or NAND does sadly have a finite number of write
cycles before errors occur.

The 130nm process is common place these days while intel has a 90nm process. The
estimation of the dimension of the process is about 45nm before it becomes too difficult
to make the chips work properly, however it may become smaller if new developments
are made but it wont be much smaller. However, Samsung, Toshiba, ScanDisk, and
others say that by focusing on the NAND flash they will be able to get past the 45nm
barrier. But there will be problems with density, power consumption and speed as time
goes on. So there still is a need for a new solution to either improve or replace flash.

Also the thickness of the gate oxide comes into play because of the high voltage required
to have electrons tunnel through the floating gate and the oxide (about 10Volts). The
current oxide thickness used is about 90 angstroms or 9nm thick. It is possible to scale

down to about 8nm before the electrons begin to leak out. This would yield data loss or

There have been a number of ways used to overcome these challenges with increasing
densities without decreasing the process. There are also innovations made that allow for
a decreased process to be possible.

One method that is being commonly used by a number of companies such as intel,
infineon, and numerous others is placing 2 or more bits per cell to get twice the data
(density) per chip. This advancement allows for a larger density without the problem of
scaling but it leads into other problems with the correct algorithms to write the data to the
specific cell. The complex algorithms slow the write and erase process down and reduce
the life span of the device, but within acceptable margins for commercial applications.
Some companies such as AMD and Infineon also want to go to a multi-bit configuration
storing 4 bits per cell. This would increase the density greatly but would once again
create a far more complex algorithm to work with as well as issues with scaling down
toward the 45nm mark. The critics such as Intel and ScanDisk say that electrical
signaling could prove problematic ads the number of the bits makes it more difficult to
differentiate between the 16 combinations of the 1 and 0. The pictures below to the

left show the two types of

multibit per cell structures
that infineon offers. The top
picture shows the twinflash
where the bits are to the sides
of the gate and the multilevel
where the individual bits are

stacked and the information is stored when a particular voltage is applied which
corresponds to the correct bit combination. The advantage of the twinflash over the
multilevel is that it is faster and has a clear shrink roadmap and the performance
of the single level flash memory. These solutions are however only prolonging the
inevitability that there is a limit to amount of data which can be stored quickly

The major advance in the reduction from the standard 130nm process to the new 90nm
process that Intel has developed relies on improving the material used. This 90nm
process combines higher-performance, lower-power transistors, strained silicon, high-
speed copper interconnects and a new low-k dielectric material. This is the first time all
of these technologies will be integrated into a single manufacturing process. They also
only use new 300mm wafers as opposed to the old 200mm wafers.

Copper interconnects with new Low-k dielectric are being used to reduce wire to wire
capacitance. The process also integrates a new carbon-doped oxide (CDO) dielectric
material that increases signal speed inside the chip and reduces chip power consumption.
This dielectric is implemented in a simple, two-layer stack design, which is easy to

manufacture. A combination of 248 nm and 193 nm wavelength lithography equipment
is used for this process.

Intel has integrated its own implementation of high-performance strained silicon into this
process. By using strained silicon, current flows more smoothly, increasing the speed of
the transistors. This will be the first process in the industry to implement strained silicon
in production. What is strained silicon, well basically the lattice is stretched or stressed
so that the electrons are allowed to flow freely with less resistance. This allows the
transistors to switch faster and allows the chips to compute faster. There have been
improvements of 10 percent in the NMOS and 25 percent in the PMOS in the drive
current. There have been problems associated with NMOS and PMOS performance
benefits and high defect rates. The same process cannot be used to stress the lattice for
both NMOS and PMOS.

The above picture to the left shows what a 64MB flash chip looks like at the various
process sizes. It is quite evident that the 90nm process can store the same data on much
smaller piece of silicon. The 90nm process is greatly dependent on the strained silicon
which is pictured on the bottom of the previous page to the right. As can be seen the
lattice once stressed or stretched allows for a much better electron flow through the

There are many new products being produced and developed to replace the current flash
technology. This is a major development when the revenue of the flash industry is
considered. In 2001 the revenue from flash was 7.3 billion, in 2003 it was 13.9 billion, in
2005 its estimated to hit 20.7 billion and in 2007 an estimated 43 billion according to
Semico Research. The year 2007 is also the year when it is estimated that the tricks for
shrinking the chip will reach their limitations. In short a 43 billion dollar industry will
most likely be replaced by a process which isnt fully developed yet.

There is the FRAM which is non-volatile memory but operates in other respects as RAM.
Fuijitsu is the first semiconductor manufacturer to establish an embedded FRAM process.
FRAM is (ferroelectric-RAM) and has a destructive write cycle like DRAM and the
ferroelectric capacitor gets damaged during the processing due to the hydrogen produced
by the semiconductor processing. MRAM is also being developed which boasts
unlimited write cycles which would be a dramatic improvement over traditional flash

memory. Some other types of non-volatile memory under development are 3DM and
Ovonyx Unified Memory. These all hope to replace todays current flash memory as
flash replaced EEPROM in the past.


Since the production of flash memory in 1988 it has taken over the market in non-volatile
memory completely eliminating EEPROM due to its cost effective production and greater
storage capacity. The Flash market will reach an estimated 43 billion dollar revenue in
the year 2007 which happens to be the very year that the physical limitations will be
stretched to the max. The physical structure just wont allow for the devices to be scaled
down any further and the memory density will not be sufficient for future application. It
is destined for flash to go the way of EEPROM but what new device will take the 43
billion dollar industry into the next generation. The next generation of non-volatile
memory will include things such as FRAM with the storage capabilities of current
NAND flash technology and the RAM like qualities of NOR flash technology, MRAM
(magnetic RAM) which boasts unlimited erase cycles that have tormented flash and even
FRAM technologies, and others such as 3DM and Ovonyx Unified Memory. One or
more of these technologies will likely replace the flash memory that we have grown so
accustom to in the past 2-3 decades. The fact is that new technologies must be developed
in order to keep pace with moores law.

[1] ABI Research. NOR vs. NAND FLASH memory

[2] Dipert, Brian. Hitting their stride: Nonvolatild-memory upstarst draw near to
established leaders. EDN magazine January 20, 2005.

[3] Infineon technologies. TwinFlash Technology Advantages.

[4] Kanellos, Michael. Is flash fried? March 27, 2003.

[5] M-Systems. NAND Flash Technology vs. NOR Flash Technology.

[6] Makwana, Jitu J. and Schroder, Dr. Dieter K. A Non-Volatile Memory Overview. .

[7] Otsuka, Nobuaki and Horowitz, Mark A. Circuit Techniques for 1.5-V
Power Supply Flash Memory. IEEE Journal of Solid-State Circuits, Vol. 32, No.
8, August 1997.

[8] Streetman, Ben G. and Banerjee, Sanjay. Solid State Electronic Devices. Fifth
Edition. 2000 Prentice Hall, Inc.