FACULTY OF ELECTRICAL ENGINEERING Answer all questions in

UNIVERSITI TEKNOLOGI MALAYSIA the provided space TOTAL

MARKS
SKEE 1223 TEST 3 (15%) DATE : 26.05.15
NAME : SECTION :
LECTURER : TIME : 1 HOUR

1. The logic symbol of a 74LS148 priority encoder is shown in Figure 1. The device has
data inputs and outputs which are active at the LOW logic level.
[3 marks]

(i) If E (Enable input) = 1, O2O1O0 = 111

(ii) If E = 0 and all the inputs are HIGH, O2O1O0 = 111

(iii) If E = 0 and all the inputs are LOW, O2O1O0 = 000

I7
I6
I5 7
I4 4 O0
L
I3 O1
S
I2
1 O2
I1 4
I0 8
E

Figure 1

2. The block diagram of a half-adder is shown in Figure 2(i). The circuit can be
implemented in various ways. You are given three circuits : Figure 2(ii), Figure 2(iii) and
Figure 2(iv). By obtaining the truth-table for each circuit, identify whether the circuits
perform the half-adder function or not.
[6 marks]

A
A Carry F0
half- B
adder
B Sum
F1

Figure 2(i) Figure 2(ii)

1
 O0
A S1 A
O1
F0
O2
B S0
B
O3

F1
2-to-4 line
decoder
F1 F0

Figure 2(iii) Figure 2(iv)

Figure 2(ii) Figure 2(iii) Figure 2(iv)

A B F1 F0 F1 F0 F1 F0
0 0 0 0 0 0 0 0
0 1 0 1 0 1 0 1
1 0 0 1 0 1 0 1
1 1 1 0 1 0 1 0
half-adder? yes/no yes/no yes/no

3. (a) Explain the similarity and difference between a latch and a flip flop.
[2 marks]

Similarity - temporary storage device that has two stable states

Difference - latch - level triggered

flip-flop - edge triggered

(b) Discuss a difference between asynchronous and synchronous counters.

[2 marks]

Any of the following

I. Asynchronous counter
The clock is applied to the first stage, subsequent stages derive the
clock from the previous stage.

Synchronous counter
The clock is applied to all stages using a common clock

II. Asynchronous counter suffers from propagation delay which

increases with subsequent stages while synchronous counter has the
same delay for each stage.

2
 III. Synchronous counter can be designed to count random sequence
while asynchronous counter cannot.

(c) From the circuit given in Figure 3(i), complete the timing diagram in Figure 3(ii).
Outputs A and B are initially 0.
[8 marks]

J J Q A
CON EN
K Q

J Q B

K K Q

Figure 3(i)

CON

Figure 3(ii)

4. Figure 4(i) shows the logic symbol and Figure 4(ii) shows the logic diagram of a 74293
asynchronous counter chip.

(i) Built a mod-12 counter (count from 010 to 1110) using this chip. You may use
additional logic gates if necessary.
[3 marks]

MR2 MR2
CP1 CP1
MR1 MR1
CP0 Q3 Q2 Q1 Q0 CP0 Q3 Q2 Q1 Q0

or

3
(ii) Design a counter using two 74293 chips to count binary coded decimal (BCD)
numbers from 010 to 9910. You may use additional logic gates if necessary.
[6 marks]

MR2 MR2
CP1 CP1
MR1 MR1
CP0 Q3 Q2 Q1 Q0 CP0 Q3 Q2 Q1 Q0

or

MR2 MR2
CP1 CP1
MR1 MR1
CP0 Q3 Q2 Q1 Q0 CP0 Q3 Q2 Q1 Q0

or

MR2 MR2
CP1 CP1
MR1 MR1
CP0 Q3 Q2 Q1 Q0 CP0 Q3 Q2 Q1 Q0