ABSTRACT

There is a need for an improved face detection engine which can detect human faces
accurately. There are several face detection techniques which uses skin colour information,
or facial pattern, object patterns etc. As the skin colour is a fundamental feature of human
faces, skin colour detection can be performed on the input image to reduce the
computational complexity. If skin colour is not detected, then there are no chances of a face
in the image. Thus relaxing any further processing. This design proposal will form a
powerful and efficient face detection for mobile devices which can work in real time.

This implementation works for different skin colours or tones. Following skin
detection, the face is detected using adaboost algorithm. This becomes an accurate technique to
avoid being cheated by fake faces, or even other face like objects. The hardware architecture for
real-time processing will be implanted on a FPGA. FPGA makes an ideal use, because it provides
good performance with low power dissipation at marginally low cost. All of which is essential for a
power constraint mobile units.

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 ACKNOWLEDGEMENT

The satisfaction and euphoria that accompany the successful completion of any
task would be incomplete without the mention of the people who made it possible, whose
constant guidance and encouragement crowned the efforts with success.

I express my gratitude to Dr. B.M.Satish, Principal, East Point College of

Engineering and Technology, Bangalore. He has always been a great source of inspiration.

I would like to express my deepest gratitude to my guide Mr. Arun Kumar M,

Associate professor, Dept. of ECE, EPCET for assistance and useful suggestions.

I express my sincere gratitude to Dr. Rohini Deshpande, Professor and Head of

Department of Electronics and Communication Engineering, for support and
encouragement.

I would also thank my parents for all support and encouragement and blessings
they gave me all the way that kept me going, without which nothing would have been
possible.

Last but not the least I would like to thank all the other faculty members of E&C
Department and my friends for their help and support.

VINAY P
EP11LVS15

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 CONTENTS

1 Abstract i
2 Acknowledgment ii
3 List of tables iii
4 List of figures iv
5 Acronyms v

CHAPTER 1: PREAMBLE 1

1.1 Introduction 1
1.2 Importance Of Face Detection 2
1.3 Face Detection Techniques 3
1.3.1 Face detection by Pattern Classification 3
1.3.2 Controlled Background Face Detection 3
1.3.3 Color Based Face Detection 4
1.3.4 Motion Face Detection 4
1.3.5 Model Based Face Detection 4
1.4 Problem Defintion 4
1.5 Proposed Work 5
1.6 Aim of the Project 5
1.7 Methodology 5
1.7 Organization Of The Report 6

CHAPTER 2: LITERATURE SURVEY 7

2.1 Paper 1 7
2.1.1 Introduction 7
2.1.2 Methodology and Implementation 7
2.2 Paper 2 8
2.2.1 Introduction 8
2.2.2 Methodology and Implementation 8
2.3 Paper 3 9

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 2.3.1 Introduction 9
2.3.2 Methodology and Implementation 9

CHAPTER 3: FACE DETECTION SYSTEM 10

3.1 Bock Diagram 10
3.2 Skin Segmentation 10
3.3 Haar Features 11
3.4 Integral Image 11
3.5 Adaboost Algorithm 12

CHAPTER 4: SKIN SEGMENTATION 13

4.1. Introduction 13
4.2 Colour Spaces 13
4.2.1. RGB Colour Space. 14
4.2.2. YCBCR Colour Space 15
4.2.3. HSI Colour Space 16
4.3. Colour Space and Conversion 16
4.3.1. RGB to YCbCr Colour Space Transform 17
4.7. Result of Skin Detection 19

CHAPTER 5: HAAR CASCADE AND ADABOOST ALGORITHM 21

5.1. Introduction 21
5.2. Haar Features 21
5.3. Cascaded Classifiers 22
5.4. Adaboost Algorithm 23
5.6. Training Classifiers using Adaboost 26

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CHAPTER 6: SYSTEM CONTROL FLOW 28
6.1. Flow Chart 28
6.2 Algorithm 29
6.2.1 Part I: Adaboost Learning Algorithm 29
6.2.2 Part II: Detection Algorithm 29

CHAPTER 7: MATLAB SIMULATION 30

7.1. Matlab Overview 30
7.2. Adaboost Training in Matlab 30
7.3. Face Detection in Matlab 33

CHAPTER 8: SIMULINK MODELS 35

8.1. Simulink Overview 35
8.2. Face Detection in Simulink 35

CHAPTER 9: FPGA IMPLEMENTATION 38

9.1. Verilog Overview

9.2. Face Detection on FPGA 38

9.3. Spartan6 FPGA 40
9.4. VGA Interface 40
9.5. Chipscope 41
9.6. Face Detection Core Module 41
9.7. Results of Face Detection Using FPGA 45
9.8. Design Summary 46
9.8.1. Xilinx Device Utilization Report 46
9.8.2. Xilinx Device Timing Summary 46

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CHAPTER 10: APPLICATIONS 47
CHAPTER 11: FUTURE SCOPE 48
CHAPTER 12: CONCLUSION 49
REFERENCES 50

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 List of Figures

Figure 3.1. Block Diagram of the Face Detection System. 10

Figure. 3.2 Different types of haar features. 11
Figure 3.3 (a) Input Image (b)Integral Image 11
Figure. 3.4. Sum calculation from Integral image 12
Figure 4.1. Peppers Image in RGB Colour space. 17
Figure 4.2. Peppers Image in YCbCr Colourspace 18
Figure 4.3. Skin Colour Detection From Different Colour Spaces 20
Figure 5.1 Example of haar feature for face detection. 21
Figure 5.2 Haar feature detection. 22
Figure 5.3 Cascade of Haar classifiers. 23
Figure. 5.4. Pseudo code for Adaboost Algorithm 25
Figure 6.1 Flow Description of Face Detection 28
Figure. 6.2. Block diagram of FPGA implementation. 29
Figure.7.1. Image from the database with markings to crop. 31
Figure.7.2. After cropping at red markings and conversion to grayscale. 31
Figure.7.3. One of the non-face image example. It is a 640x480 image. 32
Figure.7.4. Few examples of face images used for training adaboost. All individual
images are 24x24 in size. 32
Figure.7.5. Some of the haar features used in the face detection are generated in
matlab. 33
Figure. 7.6. Result of face detection on Matlab. 34
Figure.8.1 Simulink model for preprocessing block. 36
Figure. 8.2 Post-processing block to display image. 37
Figure. 9.1. Skin segmentation with grayscale skin. 39
Figure. 9.2. RTL view of the face detection with VGA output. 42
Figure. 9.3. Internal sub-modules of the Face detection system of TOP module 43
Figure. 9.4. Sub-module of the face detection engine 44
Figure. 9.5. Chipscope analysis. DataPort signal shows the pixel values whose actual
range is 0 to 16383. 45
Figure. 9.6. Chipscope analysis. A part of DataPort signal is zoomed in to show the
pixel values in given range. 45

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 List of Tables

Table 4.1: 100% Amplitude, 100% Saturated RGB Colour Bars 14

Table 9.1 Signal description of the module core. 41
Table 9.2. Face Detection project module in xilinx 46

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 List of Acronyms

CCIR - International Consultative Committee on Broadcasting

FPGA - Field Programmable Gate Array

HDL - Hardware Description Language

HDMI - High Definition Media interface

HSI - Hue, Saturation, Intensity

HSV - Hue, saturation, Value

MCT - modified census transform

RGB - Red, blue green color-space

RTL - Register Transfer Level

YCbCr - Luminance(Y), Chrominance of blue(Cb), Chrominance of red(Cr)

VGA - Video Graphics Array

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