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Project Code:
Project Name: Synchronous FIFO Design Using
VHDL
Account:
Vertical: PES
Location: Bangalore
Customer Name: Internal
Technical Manager/ Email ID: Giri.Raju@wipro.com
Project Manager / Email ID: Gurmeet.Ubhi@wipro.com
Quality Co-ordinator / Email ID:
Wipro Technologies
Bangalore
Revision History
Revision Description Date Changes By
Chetan.DNarayana
0.1 Initial Revision 09-Mar-07 @wipro.com
VLSI / System Design Business Unit
Wipro Technologies
6.1 BASIC READ AND W RITE AND FIFO EMPTY ................................ ................................ ....................... 12
6.2 FIFO F ULL ................................ ................................ ................................ ................................ ....12
6.3 ERROR WHEN FIFO IS EMPTY ................................ ................................ ................................ ..........13
6.4 ERROR WHEN FIFO IS FULL ................................ ................................ ................................ ............. 13
List of figures
1 Introduction
This document explains the scope and features of the Synchronous FIFO designed using
VHDL as a part of an internal project carried out during March 2007.
FIFO is an acronym for First In, First Out. This expression describes the principle of a queue or
first-come, first-served (FCFS) behavior: what comes in first is handled first, what comes in
next waits until the first is finished and so on. FIFOs are used commonly in electronic circuits
for buffering and flow control. It usually achieves a Store and Forward path for data.
There can be two types of FIFOs, a Synchronous FIFO, where the same clock is used for both
reading and writing. An Asynchronous FIFO which uses different clocks for reading and
writing.
2 Architectural Overview
The following block diagram shows the architecture and interface of the FIFO unit.
Rst
MEMORY
Clk (BUSWIDTH x
FIFODEPTH)
Dout Din
READ WRITE
UNIT UNIT
Rd Wr
Full
STATUS MONITOR Err
Empty
The design is parameterized, using the generics concept of VHDL, to have desirable data
width, and the depth of the FIFO. The data width refers to the width of the data bus and the
memory block in bits and the depth refers to the size of the FIFO, as to how many entries can
be pushed into the FIFO before filling it completely.
The FIFO consists of a set of contiguous memory locations to which data can be written or
read from, on a first-in-first-out basis. The data can be continuously written to the FIFO until it
is full and can be read back when required. The data that was written first will be the data that
is obtained on the first read. Subsequent reads will return the data that was written
successively in time.
The design also flags the memory status as to whether it is full, without space for any incoming
data or empty, when no more data is available in memory. The module which issues a read or
write request should monitor the FIFO status before initiating a transaction. If the request
violates the rules for respective transaction an Error pulse is triggered by the FIFO.
Write Signals
Wr - Indicates a Write Request to the FIFO. For a valid write
request, this signal should be asserted during the rising
edge of the system clock.
Din - Data to be written to the FIFO. The data should be
available at the same clock edge when the Wr signal is
asserted.
Read Signal
Rd - Indicates a Read Request to the FIFO. For a valid read
request, this signal should be asserted during the rising
edge of the system clock.
Miscellaneous
Clk - System Clock. The design works on the positive edge
every clock cycle.
Rst - Active High Asynchronous Reset input.
3.2 Outputs
Data signal
Dout - Output Data that is read from memory during a read
transaction.
Status Signals
Full - The FIFO full flag. This asserts on the successful write
operation which last caused the FIFO memory to be
full, and is de-asserted until a read operation happens
to vacate a memory location.
Empty - The FIFO empty flag. This when asserted indicates
that there is no data in the FIFO, and de-asserts when
a write operation is initiated on the empty FIFO.
Err - An error flag. A pulse of 1 clock duration is generated
on this output, if a write to FIFO is attempted when it is
full or a FIFO read is attempted when it is empty.
4 Sub-Module Description
4.1 Memory
This is a collection of contiguous memory locations which constitute a RAM.
Each memory location is of width BUSWIDTH in bits, where BUSWIDTH is the deign
parameter. The number of such memory locations will be equal to another parameter defined
as FIFODEPTH. So the memory can hold maximum number of entries equal to the
FIFODEPTH at any instant of time.
The write pointer maintained internal to the Write Unit can be accessed by the Status Monitor
for the purpose of generating the FIFO Full flag.
On every rising edge of the clock input, the Write Unit will sample the Wr signal of the FIFO
input, if found to be asserted, a write operation is initiated. The data that is to be written will
also have to be available on the Din input, by the same clock edge. It will next check from the
Status Monitor if the FIFO is full. If so, then it updates the Status Monitor of an illegal operation
detected, else the data on Din input is transferred o the memory location pointed by write
pointer and then increments the write pointer.
The read pointer maintained internal to the Read Unit can be accessed by the Status Monitor
for the purpose of generating the FIFO Empty flag.
On every rising edge of the clock input, the Read Unit will sample the Rd signal of the FIFO
input, if found asserted, a read operation is initiated. It will next check from the Status Monitor
if the FIFO is empty. If so, then it updates the Status Monitor of an illegal operation detected,
else the data from the memory location pointed by read pointer is transferred to the external
interface and then increments the read pointer.
Full Flag: The Full signal on the FIFO output is asserted by the Status Unit to indicate that the
FIFO memory is full, and any further write operation will not be supported. If such an
unsupported operation is attempted, an error flag will be pulsed.
Error Flag: If a FIFO read is requested when it is empty, or if a FIFO write is requested when it
is full, then an error is flagged by the Status Monitor. This occurs as a pulse of one clock
duration on the Err output of the FIFO. The duration of the error pulse may extend beyond one
clock period, if the unsupported request is continued even in the next clock cycle.
The external module which tries to access the FIFO should take care that it does not attempt a
read when the FIFO is empty or a write when the FIFO is full. Such a request will not be
supported by the FIFO and will in turn pulse the Err signal, intimating the requestor of an illegal
request attempted. If the FIFO receives both read and write requests simultaneously and an
Err pulse is tossed, the requestor will be able to identify which request has failed, by sampling
the Full and Empty signals at that instant. If the Full is asserted in the event of an Err pulse,
then the write request wouldn’t have succeeded, else if the Empty is asserted, then the read
request wouldn’t have succeeded.
6 Timing Diagrams
6.1 Basic Read and Write and FIFO Empty
Clk
Rst
Wr
Rd
Din Data 1
Dout Data 1
Full
Err
Rst //
Wr //
Rd //
Dout //
Err //
Rst
Wr
Rd
Din
Dout
Full
Err Error
Figure 4: FIFO Empty Error Timing Diagram
Rst //
Wr //
Rd //
Dout //
Empty FIFOempty //
Err // Error
Figure 5: FIFO Full Error Timing Diagram
Glossary
FIFO : First In First Out
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