SIMULATION AND MODELING OF SINGLE-STAGE

SINGLE-PHASE GRID CONNECTED DC-AC BOOST

CONVERTER WITH ACTIVE POWER INJECTION AND
REACTIVE POWER COMPENSATION

A PROJECT REPORT
submitted by

AJITH BALAKRISHNAN
AWH15EEPE01
to
the APJ Abdul Kalam Technological University
in partial fulfillment of the requirements for the award of the Degree
of
Master of Technology
In
Power Electronics

Department of Electrical & Electronics Engineering

AWH Engineering College
Calicut
MAY 2017
 ACKNOWLEDGEMENT

First and foremost, I would like to invoke the grace of the Almighty, without which no fruitful
event occurs in this world.
I wish to express my sincere gratitude and thanks to Mr. Subhash Joshi T.G., Senior Engineer,
Power Electronics Group, CDAC, (TVM) for his guidance, encouragement and support during
this project.
I am grateful to my Honourable Principal Prof. Shahir V.K., for providing me with all facilities
and help for the successful completion of this project.
I owe a whole hearted sense of reverence and gratitude to Mrs. FATHIMA SAPNA P.,
Associate Professor & Head of the Department, EEE, for her constant support and
encouragement rendered to me.
I also convey my immense gratitude to my guide, Ms. MERCY THOMAS, Assistant
Professor, EEE, for her efficient and excellent guidance.
I also convey my sincere gratitude to Mr. MURALI KRISHNAN K., Assistant Professor, EEE,
for his guidance and support.
I also extend my heartfelt thanks to all the faculty members of EEE Department who have
rendered their valuable help.
Last but not the least, I thank my family and friends for their encouragement and prayers.

i
 ABSTRACT

This paper presents a new single-stage single-phase solar PV based, grid connected dc-
ac boost converter with an active power injection and reactive power compensation scheme.
The single stage topology is based on a full-bridge DC-AC inverter, which uses a single circuit
for DC-DC boost conversion and DC-AC conversion. The proposed converter not only acts as
inverter, but also boosts the output voltage with respect to input. Two additional diodes and
one input inductor implement the two boost converters that share the same input inductor.
Switching strategy for this topology is similar to a conventional inverter, and in each half
cycle, boost operation is done by one of the two boost converter. For generating the sinusoidal
output voltage, a variable duty cycle is applied to the switches. A current based perturb and
observe control algorithm is used for tracking the maximum power point of the solar panel.
The active power is injected from the PV panel and the reactive power is compensated by
extracting the load current.

ii
 CONTENTS
Contents Page No.
ACKNOWLEDGEMENT i
ABSTRACT ii
LIST OF TABLES iii
LIST OF FIGURES iv
ABBREVIATIONS v
Chapter 1. INTRODUCTION 1
1.1 General 1
1.2 Project Objective 2
1.3 Scope of the project work 2
1.4 Scheme of the project work 3
1.5 Conclusion 4
Chapter 2. LITERATURE SURVEY 5
2.1 Introduction 5
2.2 Literature review 5
2.2 Conclusion 12
Chapter 3. MODELING OF SOLAR PV SYSTEM 13
3.1 Introduction 13
3.2 Modeling of a solar pv module 13
3.3 Solar cell characteristics 13
3.1 Introduction 13
3.2 Modeling of a solar pv module 13
3.3 Solar cell characteristics 13
3.3.1 Effect of variation of solar irradiation 16
3.3.2 Effect of variation of temperature 17
3.4 Maximum power point tracking 18
3.4.1 Perturb and observe method 18
3.3.2 Flowchart of perturb and observe method 19
3.5 Conclusion 19

iii
Chapter 4. SINGLE STAGE DC-AC BOOST CONVERTER 20
4.1 Introduction 20
4.2 Single stage dc-ac boost converter 20
4.3Modes of operation of the proposed converter 21
4.3.1 State I [0<t<T/2] 21
4.3.2 State II [T/2<t<T] 22
4.4 Steady state analysis of the converter 23
4.5 Switching strategy 24
4.6 Design of the dc-ac boost converter 25
4.6.1 DC capacitor voltage 25
4.6.2 DC capacitor 26
4.6.3 Boost inductor 26
4.7 Conclusion 26
Chapter 5. CONTROL SCHEME FOR THE GRID CONNECTED
DC-AC BOOST CONVERTER 27
5.1 Introduction 27
5.2 Control block diagram 27
5.3 Unit vector for single-phase grid 28
5.4 Scheme for active current extraction 29
5.4.1 Expression for active current extraction 29
5.5 Scheme for reactive current extraction 30
5.5.1 Expression for active current extraction 30
5.6 Control law for the current controller 32
5.7 Scheme for duty cycle generation 33
5.8 Conclusion 33
Chapter 6. SIMULATION OF THE PROPOSED SINGLE-STAGE
GRID CONNECTED BOOST CONVERTER 34
6.1 Introduction 34
6.2 Simulation parameters 34
6.3 Simulation diagram 34
6.4 Simulation results 38

iv
 6.5 Conclusion 49
Chapter 7 . HARDWARE IMPLEMENTATION 50
7.1 Introduction 50
7.2 Design of the dc-dc boost converter 50
7.3.1 Design of the boost inductor 50
7.3.2 Design of the output capacitor 51
7.3 Hardware parameters 51
7.4 Circuit diagram 52
7.5 Hardware set up 54
7.6 Description of circuit 55
7.6.1 Power supply unit 55
7.6.2 Control unit 56
7.6.3 M-board unit 58
7.6.4 DC-DC converter unit 59
7.6.5 Inverter unit 60
7.7 Working 61
7.8 Hardware results 61
7.9 Conclusion 62
Chapter 8. CONCLUSION 63
8.1 General 63
8.2 Future Works 64
REFERENCES 65

v
 LIST OF TABLES

No Title Page No

6.1 Simulation parameter values 34

7.1 Hardware parameter values 52

vi
 LIST OF FIGURES

No Title Page No

3.1 Single diode model of solar cell 14

3.2 Equivalent circuit of a solar module 15
3.3 I-V, P-V curve of a solar cell at a given temperature and solar
irradiation 15
3.4 Variation of P-V curve with solar irradiation 16
3.5 Variation of I-V curve with solar irradiation 16
3.6 Variation of P-V curve with temperature 17
3.7 Variation of I-V curve with temperature 17
3.8 Flowchart of perturb and observe method 19
4.1 Proposed single stage DC-AC boost converter 20
4.2 Stage 1 of state I (T1, T3 on T2, T4 off) 21
4.3 Stage 2 of state I (T1, T3 off T2, T4 off) 21
4.4 Stage 1 of state II (T2, T4 on T1, T3 off) 21
4.5 Stage 2 of state II (T2, T4 off T1, T3 off) 21
4.6 Sample pulses for T1 - T3 and T2 - T4 24
4.7 Variable duty cycle of T1 and T3 25
4.8 Variable duty cycle of T2 and T4 25
5.1 Control block diagram for the proposed system 27
5.2 Unit vector components 28
6.1 Simulation diagram of the proposed single-phase single-stage grid
connected dc-ac converter with active power injection and
reactive power compensation 35
6.2 Simulation diagram of MPPT using current controlled P&O 36
6.3 Simulation diagram for reference current generation 37
6.4 Simulation diagram for variable duty cycle generation 38
6.5 Simulation diagram of variation of irradiation level with time 38
6.6 Simulation diagram showing variation of with time 39

vii
6.7 Simulation diagram showing variation of with time 40
6.8 Simulation diagram showing current command generation 40
6.9 Simulation diagram showing the variation of inductor current 41
6.10 Simulation diagram showing the variation of capacitor voltage 42
6.11 Simulation diagram showing the variation of duty cycle in one
period, for T1 and T3 43
6.12 Simulation diagram showing the variation of duty cycle in one
period, for T2 and T4 43
6.13 Simulation diagram showing the variation of active current 44
6.14 Simulation diagram showing the variation of reactive current 44
6.15 Simulation diagram showing the variation of reference current 45
6.16 Simulation diagram showing the variation of converter current 45
6.17 Simulation diagram showing the variation of grid current 46
6.18 Simulation diagram showing the variation of active current and
grid current 47
6.19 Simulation diagram showing the variation of load current 47
6.20 Simulation diagram showing the converter voltage 48
6.21 Simulation diagram showing the grid voltage 48
7.1 Circuit diagram of the hardware prototype 53
7.2 Hardware prototype of the PV based multi-stage dc-ac converter 54
7.3 Solar module used at the input of dc-dc converter 55
7.4 Power supply unit (a) circuit diagram (b) Hardware prototype 56
7.5 Control unit (a) circuit diagram (b) Hardware prototype 57
7.6 M-board unit (a) circuit diagram (b) Hardware prototype 58
7.7 Converter unit (a) circuit diagram (b) Hardware prototype 59
7.8 Inverter unit (a) circuit diagram (b) Hardware prototype 60
7.7 Gate pulses of dc-dc boost converter MOSFET 61
7.8 Gate pulses of inverter MOSFET 62

viii
 ABBREVIATIONS

AC Alternating Current

DC Direct Current
LCD Liquid Crystal Display
LED Light Emitting Diode
MPPT Maximum Power Point Tracking
MW Mega Watt
MOSFET Metal Oxide Semiconductor Field Effect Transistor
PLL Phase Locked Loop
PV Photo Voltaic
PWM Pulse Width Modulation
THD Total Harmonic Distortion
TTL Transistor Transistor Logic
USART Universal Synchronous Asynchronous Receiver Transmitter

NOTATIONS

I Current, A

D Duty Cycle
Fs Switching Frequency, kHz
L Inductance, mH
C Capacitance, F
V Voltage, V

ix
 CHAPTER 1
INTRODUCTION

1.1 GENERAL BACKGROUND

The depletion of fossil fuel energy has become a global concern due to the rapid
growth in population, urbanization and industrialization. The deficit between the demand and
supply of energy, the difficulty and cost involvement in the planning and installation of
centralized power plants, along with the environmental consequences of the non-conventional
resources, have led to the search for alternate renewable energy sources like the solar energy,
wind energy, wave energy etc., which are abundant in nature, freely available and also,
distributed throughout the earth. The most common among the existing renewable energy
systems is the solar photovoltaic (PV) system.
The PV systems are built using low-voltage photovoltaic cells, usually connected in
series to form a solar module. However, the output voltage of the cells is not large enough for
connecting to ac utility service. For attaining a reasonable voltage, a large number of solar
panels are interconnected so as to form a solar array. This not only leads to an increase in
system complexity but also reduces its performance due to the mismatch between cells and
variation in working conditions. So, it becomes necessary that the PV dc output voltage be
boosted with high conversion ratio before being inverted to ac for practical applications. For
this, conventionally a dc-dc boost converter is used between the source and the dc-ac inverter.
But, depending on the output power and voltage levels needed, such a multi-stage system can
result in a higher volume, weight, cost and reduction in the efficiency and compactness of the
system.
In order to overcome the above said drawbacks, it becomes necessary to integrate the
different stages of a multi-stage unit into a single-stage configuration, with as many features
of multi-stage system, as possible. A single-stage system has the advantages of compactness,
modularity, lower cost and higher efficiency. Hence, such single-stage topologies are
becoming increasingly popular as compared to the multi-stage units, particularly for
interfacing non-conventional energy sources with the grid.

1
 1.2 PROJECT OBJECTIVE
To model a new single-phase single-stage dc-ac boost converter with lesser

number of switches.

To implement a new maximum power point tracking algorithm for the PV

system, using a current control scheme.

To implement control scheme for active power injection for grid interfacing of

the single-stage dc-ac boost converter.

To implement control scheme for reactive power compensation for grid

interfacing single-stage dc-ac boost converter.

To ascertain the effectiveness of the proposed single-stage grid connected

system using PSIM.

To implement a hardware prototype with multi-stage topology, using a dc-dc

boost converter and dc-ac inverter feeding a single phase induction motor.

1.3 SCOPE OF THE PROJECT WORK

This project proposes a new single-phase single-stage grid connected solar PV based
dc-ac boost converter with active power injection and reactive power compensation. The
proposed single-stage converter not only acts as inverter, but also boosts the output voltage
with respect to input voltage. The single-stage topology is based on a full bridge dc-ac
inverter, which uses a single circuit for dc-dc boost conversion and dc-ac conversion. Two
additional diodes and one input inductor implement the two boost converters that share the
same input inductor. The switching strategy for the proposed topology is similar to a
conventional inverter. In each half cycle, the boost operation is done by one of the two boost
converters. For generating the sinusoidal output voltage, a high frequency and variable duty
cycle is applied to the switches. A control scheme is adopted for connection to the grid and to
achieve active power injection and reactive power compensation. Theoretical analysis and
principle of operation are discussed in detail. To verify the performance of the proposed

2
system, a prototype single-phase single-stage grid connected solar converter with active
power injection and reactive power compensation is simulated using PSIM software.
Simulation results are presented to demonstrate the effectiveness of the proposed grid
connected system. The results validate the theoretical analyses and the practicability of the
proposed single-phase single-stage grid connected converter.
A hardware prototype with multi-stage topology using a dc-dc boost converter and a
dc-ac inverter feeding a single phase induction motor is also implemented. In the hardware
prototype, speed control of the single phase induction motor is implemented using
microcontroller based control.

1.4 SCHEME OF THE PROJECT WORK

This report is organized as follows:
Chapter 2 presents a literature review about the proposed single-phase single-stage
grid connected solar PV based dc-ac boost converter. The review mainly focused on single-
stage and multi-stage converter systems, modulation techniques, control schemes for grid
interfacing and control schemes for active power injection and reactive power compensation.
Chapter 3 deals with modeling of solar PV systems, solar cell characteristics in
accordance with the variations in irradiance and temperature and explains scheme for
maximum power point tracking using perturb and observe method.
Chapter 4 introduces a new single-stage dc-ac boost converter topology. The different
modes of operation along with the steady state analysis are also discussed. The switching
strategy for sinusoidal waveform generation is also presented.
Chapter 5 discusses the control scheme for active power injection and reactive power
compensation for the proposed grid connected dc-ac boost converter. The concept of unit
vector is also introduced. The reference current generation algorithm and the scheme for the
duty cycle generation are also discussed.
Chapter 6 presents the simulation of the proposed single-stage grid connected boost
converter with active power injection and reactive power compensation. The simulations are
carried out using PSIM software. The results obtained are also discussed in detail.
Chapter 7 presents the real time implementation of a multi-stage converter, with a
speed control scheme for a single phase induction motor.
Chapter 8 includes the conclusion and future scope of this thesis work.

3
1.5 CONCLUSION
The chapter dealt with a brief introduction of the single-stage system and its
advantages over the multi-stage system. A new single-phase single-stage dc-ac boost
converter with lesser number of switches was proposed. A control scheme for the active
power injection and reactive power compensation was also presented. The scope of the thesis
was presented and the overview of various chapters included in this thesis was also presented.

4
 CHAPTER 2
LITERATURE SURVEY

2.1 INTRODUCTION
This chapter reviews the papers based on different topologies of single-stage grid
connected boost converters, solar photovoltaic (PV) systems with maximum power point
tracking (MPPT), various previous studies done on the active power injection and reactive
power compensation.

2.2 LITERATURE REVIEW

R. O. Caceres, and I. Barbi [1], introduced a new VSI referred as boost dcac
converter. Depending on the instantaneous duty cycle, the converter generated an ac output
voltage which was larger than the dc input. This was achieved by connecting the load
differentially across the two dc-dc converters and then, modulating the converter output
voltages sinusoidally. For modulation, a sliding mode hysteresis control was used, which
involved the sensing of all the system state variables followed by the generation of suitable
reference for each variable. Using this, the maximum switching frequency and duty cycle for
the switches was obtained.
N. C. Foureaux, L. Adolpho, S.M. Silva, Brito de S, De J. Cardoso and Filho Jose
Antonio [2], introduced a modular converter based on line frequency solid state transformers
(SST). In the proposed system, the high frequency transformers were used, replacing the
bulky medium-voltage line-frequency ones. The converter output was provided by a series
connection of dc-dc-ac converter stages, supplied by independent PV module arrays. SST not
only gave the galvanic isolation and avoided the leakage currents, but also served the means
for the centralized control of the plant and for connection to medium voltage grid. On the dc
side, MPPT control was used for the PV arrays, and on the ac side, vector controller was used
to regulate the line current to be injected to the power control centre. The proposed structure
had many MPPT trackers and higher reliability due to redundancy and unbalance operation
capability.
H. S. Krishnamoorthy, S. Essakiappan, P. N. Enjeti, R. S. Balog and S. Ahmed [3],
introduced a new multi-level dc-dc-ac converter topology for medium voltage grid integration
of Megawatt (MW) scale utility photovoltaic (PV) plants. It consisted of dc-dc converter,

5
followed by full-bridge inverter feeding transformer with three secondary windings. It was
envisioned that a large PV field is divided into many zones, each comprising of two PV
arrays. The number of zones depended on the voltage of the grid with which it is interfaced.
The power conversion architecture consisted of an IGBT based full-bridge inverter feeding
the medium frequency transformer. The voltage at the transformer secondary was then
converted to three phase line frequency ac by full-bridge ac-ac converters. This also
eliminated the second harmonic power from the DC bus, thereby reducing the capacitor size.
A new control method was also proposed for the series connected modules during partial
shading while minimizing the switch ratings.
S. Pouresmaeil, B. Eskandari, and M. T. Bina [4], introduced an efficient modulation
technique for a conventional six pulse, three-phase dc-ac boost converter. This paper
suggested a simple formulation of pulse widths for generation of sinusoidal waveform for
boost inverter. It was observed that, despite waveform improvement, still the output was
distorted. It was also noted that even the use of PI controllers still lead to distorted output
voltage because of the non-linear structure of the converter. An optimized offset modulation
technique was defined to overcome the issues. The proposed technique led to a lower dc link
current oscillation, reduction in the dc offset produced, lower component counts and less
losses in converter. The three phase sinusoidal voltage with bigger amplitude compared to the
source voltage at different levels with different desired frequency could be produced.
Soeren Baekhoej Kjaer, John K. Pedersen, and Frede Blaabjerg [5], explained about
some of the standards that inverters for PV and grid applications must fulfil, which focused on
power quality, injection of dc currents into the grid, detection of islanding operation, and
system grounding. The role of power decoupling between the modules and the grid was also
investigated and concluded that the ripple amplitude across a PV module should never exceed
3V in order to have a utilization efficiency of 98% at full generation. A historical summary of
the string inverters was done. Also, PV module interfaced to the grid with its own dcac
inverter was investigated. It was followed with a classification of the inverters. It was
concluded that the multi string grid connected concept was a better choice. Also, it was
concluded that the preferable location for the capacitor was in the dc link, where the voltage
was high and a large fluctuation could be allowed, with the use of film capacitors instead of
electrolytic capacitors. Inverter topology with dual grounding was found suitable to mitigate
the resonance between the PV modules and inductances in the current paths.

6
 T. Kerekes, R. Teodorescu and U. Borup [6], analysed and compared the most
common single-stage transformer-less PV inverter topologies for single-phase with respect to
the leakage current generation. It was found that the best results were obtained when the
middle point of the input capacitors was connected to the neutral point, thereby minimizing
the voltage fluctuations present at the terminals of the PV panel. By experimental results, it
was concluded that the single phase full-bridge topology with bipolar switching was suitable
for transformer less PV inverters, because the leakage current was much lower than in case of
the unipolar switching. The NPC was also found to be a good, due to its grounded middle
point, which minimized the voltage fluctuations present at PV panel terminals that would
generate high leakage currents through the parasitic capacitance of the PV panel.
H. Ribeiro, A. Pinto, and B. Borges [7], introduced a new dc-ac converter, merging a
dc-dc converter and an inverter in a single-stage topology. It was based on a full bridge
converter with three levels of output voltage, where two diodes and one inductor were added
in order to create a boost converter. The control system was based on a digital variable for the
voltage polarity and two hysteretic controllers: one for the grid injected current, and the other
for controlling the PV panel current. The topology was found suitable to be operated with low
PV voltages, due to high voltage gain given by the two input boosts. Also, a reduction in the
leakage inductance resulted in reduction of the dissipated power, with an increase in the
efficiency.
Hiren Patel and Vivek Agarwal [8], introduced a single-phase single-stage
transformer-less doubly grounded, PV-fed buckboost grid connected inverter. Only one,
undivided PV source and one buckboost inductor and a decoupling capacitor was used and
shared between the two half cycles, which prevented asymmetrical operation and parameter
mismatch problems. It was demonstrated that, as compared to the split PV source topology,
the proposed double grounding configuration was more effective in MPPT and array
utilization. It was observed that in the proposed topology, the maximum voltage that could be
developed on the ungrounded conductor was limited to the PV array output voltage, and
hence, not only the topology exhibited a good safety feature but also eliminated the problems
arising out of asymmetrical operation and mismatch in the components. Thus the THD and
the dc component of the injected grid current were much lower. Also, due to its inherent
nature, it could work over a wide input voltage range. The effectiveness of the proposed
inverter configuration to operate in non-uniform insolation conditions was also demonstrated.

7
 Mihai Ciobotaru, Remus Teodorescu and Frede Blaabjergis [9], aimed at presenting a
single-stage converter for single-phase PV systems. Two different current controllers using PI
and PR were implemented and experimental comparison between them was made. A
complete control structure for the single-phase PV system was also presented. An incremental
conductance method was used to track the MPPT of the PV system. For grid synchronization,
a PLL based on delay structure was used. The PLL provided a unity power factor operation,
which involved synchronization of the inverter output current with the grid voltage to give a
clean sinusoidal current reference. It was demonstrated that the PR+HC controller gave better
performances then the classical PI controller for the grid current loop. The main drawbacks of
a PI controller are the steady-state error and poor harmonics rejection capability. The former
could be overcome by the PR controller itself, and the latter could be addressed by adding
selective harmonic compensator to the PR controller, which gave a very good rejection of the
dominant harmonics.
S. Ozdemir, N. Altin and I. Sefa [10], designed a single stage, three-phase, three level
neutral point clamped inverter is for grid connected solar supplied systems. The proposed
voltage source inverter was operated in current controlled mode and a PI current controller
was used for the production of switching. The inverter was operated in parallel with public
grid by using phase locked loop method. MPPT algorithm was used to generate the current
reference for the current controller. Experimental results showed that the inverter output
current was in phase with line current, and unity power factor operation was also obtained. a
very good rejection of the dominant harmonics.
Yuansheng XiongSuxiang Qian and Jianming Xu [11], designed a grid connected
inverter consisting of two boost converters for single-phase grid connected PV system. A
double loop control structure was included with an outer current loop and inner voltage loop.
The phase error between grid current and grid voltage was computed whenever the negative
zero-crossing of grid voltage was detected. Two PI controllers were used in the outer current
loop to regulate the phase of the grid reference current and to compute the reference voltage
of inner loop. The amplitude and phase of the grid connected reference current was adjusted
when the positive zero crossing of grid voltage was detected. The error between the reference
current and actual current was the input of the PI controller, and the output added to grid
voltage was used as the given voltage for the inner voltage loop. The sliding mode controller
was designed for the inner voltage loop of boost inverter. The simulated results showed that

8
the system could be realized under the condition that the PV array voltage was lower than the
amplitude of the grid voltage. Also, the grid current had good sine degree, and was also
synchronous with grid voltage. The amplitude of reference grid current was tracked with no
error.
T.I. Marisa, St. Kourtesib, L. Ekonomouc, G.P. Fotisd [12], designed a model of a
single-phase grid connected PV voltage inverter. The simulation was done using
PSCAD/EMTDC simulation package. This inverter model was used to show real and reactive
power flow. The satisfactory operation of the inverter circuit was ensured obtaining a square
wave as the output. With the introduction of a relative phase shift between the two output
voltages, it was proved that the real power was a function of the power angle d. It was also
found that the inverters performance could be improved using faster switching devices. The
operation of the inverter in this work showed the models ability to both absorb and generate
reactive power. It was shown that increasing the supply voltage at the input of the inverter,
resulted in exporting reactive power from the inverter, and the vice versa. Also, when the dc
supply was increased, the magnitude of the fundamental of the inverter output was increased
with respect to the grid voltage magnitude. The difference in voltage magnitudes lead to the
injection of reactive power by the inverter and vice versa. This ability proved to be useful if
such models were installed in houses fed from the main distribution grid, as the inverter could
compensate for some of the power needed to supply such loads at good sine degree,
synchronous with grid voltage. The amplitude of reference grid current was tracked with no
error.
P. Liengpradis and V. Kinnares [13], proposed the active power control of a single-
phase grid connected system supplying nonlinear load. The main objective was to employ the
converter acting as multifunction for single-phase grid connection. The control method
employed reference current calculation combining the required real component of the grid
current derived from required active power transfer to the grid and required harmonic current
for harmonic elimination associated with the nonlinear load. With this method, power of any
type of renewable energy could be transferred to the nonlinear load and the grid. Also, the
grid current obtained was nearly sinusoidal, the reactive power of the nonlinear load was also
compensated and the power factor was always nearly unity. The simulation results using
MATLAB/Simulink verified the correctness of operation for the proposed functions. The

9
achievement of control of active power delivery, current harmonic distortion and power factor
improvements were efficiently obtained.
Martin Gahid and Pavol Spanik [14], proposed a model of PV solar cell and module.
The model was verified by the simulation using Matlab. The influence of temperature and
solar irradiation on the PV module was investigated. A mathematical model for the PV
module was proposed to simulate this dependence on the environmental conditions. The
model was based on fundamental circuit equations of PV solar cell. The accuracy of the
model was confirmed by comparison between the Sharp NU-245(J5) 245Wp datasheet and
the simulated I-V characteristics. The influence of the temperature and the solar irradiation
was investigated. The solar irradiation influence was found to be bigger than temperature
especially when the decrease of the solar irradiation was focussed upon. The impact on the
output power was much heavier. The proposed simple model of the PV solar module was
found enough accurate and could be used for the development and simulation of a stand-alone
power system.
Sachin Jain and Vivek Agarwal [15], presented a new MPPT algorithm based on
current control for a single-stage grid connected PV system. This algorithm could predict the
approximate amplitude of the reference current waveform or power that could be derived
from the PV array with the help of an intermediate variable. A variable step size for the
change in reference amplitude during initial tracking helped in faster tracking. With variable,
large step changes in reference current, an approximate MPP was reached within a few
iteration steps, drastically reducing the tracking time as compared to conventional techniques.
It was also observed that if the reference current amplitude was greater than the array
capacity, the system got unstable. The proposed algorithm prevented that. It was also capable
of restoring stability if the system got unstable due to a sudden environmental change. The
proposed algorithm was tested on a new single-stage grid connected PV configuration. The
system was operated in a CCM to realize advantages such as low device current stress, lower
losses high efficiency and low EMI. Specific cases of the system, operating in just DCM and
DCM and their relative merits and demerits were also discussed.
Yang Jun, Lian Xiaoqin, Zhang Xiaol, Duan Zhengang and Wang Min [16], proposed
a versatile simulation model for PV array based on the DC physical model of PV module
under PSIM environment. The I-V, P-V characteristics of the PV array with different
combinations were simulated by the model, using PSIM. In addition, the model included the

10
function of MPPT using the Perturb and Observe method. It was concluded from the analysis
of simulation results that high accuracy of the model simulation could accurately reflect the
physical characteristics of the PV array, which would provide a basis for the simulation of the
power generation systems.
M. El-Habrouk, M. K. Darwish and P. Mehta [17], proposed an overview of the state
of the art techniques in reactive power compensation and active power filters. The
presentation and the subdivisions of the power system conditioners presented showed the
merits and drawbacks of each type and the technique used. The results would enable design
engineers and researchers in power quality to enable them to select the correct system for their
specific applications.
Leonardo B. G. Campanhol, Srgio A. Oliveira da Silva, Leonardo P. Sampaio and
Azauri A. O. Junior [18], proposed a single-phase, single-stage solar PV system, connected to
the utility grid by using a full bridge dc-ac converter. The proposed system had active power
injection ability from the PV panels. Simultaneously, it performed reactive power
compensation and harmonic current suppression generated by nonlinear loads. For the PV
system, MPP tracking using P&O algorithm, was implemented utilizing an equivalent electric
model proposed in the literature. The algorithm adopted to obtain the current reference of the
converter was based on the synchronous reference frame. The dynamic behaviour of the PV-
active filter system for different levels of solar radiation was also verified. The fast response
at the inverter side was also verified by means of load transients. Simulation results using
Matlab were presented to validate the proposed control strategy for active power injection,
reactive power compensation and harmonic current suppression as well as to verify the system
feasibility.
Woo-Jun Cha, Yong-Won Cho, Jung-Min Kwon [19], proposed a novel highly
efficient micro-inverter with a soft-switching step-up dcdc converter using an active clamp
circuit with a series resonant voltage doubler and a high-efficiency inverter with single-
switch-modulation inverter for single-phase grid-connected PV system. The active-clamp
circuit provided ZVS turn on, recycled the energy stored in the leakage inductance of the
transformer, and also limited the switch voltage stress by clamping the voltage stress across it.
The series resonant voltage doubler removed the reverse-recovery problem of the rectifier
diodes. To improve efficiency and reliability, only a single switch was modulated at the
switching frequency without a shoot-through problem. A modified controller was also

11
adopted to achieve fast output control. Thus, the proposed PV micro-inverter has the structure
to minimize power losses. The experimental results showed a maximum efficiency of 96.2%
for a 400-W hardware prototype.

2.3 CONCLUSION
The literature review on the single-phase grid connected solar PV systems, maximum
power point tracking for PV panel, active power injection and reactive power compensation
was presented. Also, the literatures dealing with the various control algorithms were
presented.

12
 CHAPTER 3
MODELING OF SOLAR PV SYSTEM

3.1 INTRODUCTION
The most readily available renewable source of energy is the solar energy. Solar
energy can be converted into electrical energy by means of a solar cell. A single cell produces
a very small voltage. Therefore, many cells need to be connected in series or parallel
combinations to achieve the desired dc voltage or current. A group of solar cells connected in
series is called a solar module. A series and/or parallel combinations of modules form a solar
panel, and a combination of group of such panels form a solar array. Because of the non-
linear iv characteristics of the solar array, the power extracted from a PV source depends on
its operating point. For a given insolation and temperature, there exists a unique operating
point corresponding to the maximum power point of the PV array. Therefore, to extract
maximum power from the PV array, it is necessary to operate at the corresponding MPP as
insolation and temperature. This is called the electrical tracking of the maximum power point
or simply maximum power point tracking [16]. The modelling of a solar cell, solar cell
characteristics and maximum power point tracking are discussed in this chapter.

3.2 MODELING OF A SOLAR PV MODULE

The basic building block of a solar PV module is a solar photovoltaic cell. A solar
module is formed by connecting many solar cells in series and parallel. A solar cell is
basically a semiconductor P-N junction diode that converts light energy into electrical energy
by the photovoltaic effect. When photon particles of light having energy greater than the band
gap of the valence electron is bombarded to the Junction electron hole pairs are generated
which when acted upon by internal electric field result in a photocurrent. A solar cell is
basically a current source, where the current is produced by the variation of photons and not
the voltage. A single solar cell can be modelled by using the single diode equivalent circuit
consisting of a current source connected in parallel with a diode, a series resistance, Rs and a
parallel (shunt) resistance, Rsh. For ideal condition, the series resistance very small (Rs = 0)
and Rsh is very large (Rsh = ). The series resistance is an important parameter, especially for
irradiances and cell temperatures far from the reference condition. The single diode model is
as shown in Fig. 3.1.

13
 Fig. 3.1 Single diode model of a solar cell

The characteristic equation for a photovoltaic cell is given as

I = Ilg Ios[exp{q(V+IRS) / (AkT)}1] (V+IRs)Rsh (3.1)
here,
Ios= Ior(T/Tr)3[exp{qEg(1/ Tr1/T) / Ak}] (3.2)
Ilg = {Iscr + Ki(T25)} (3.3)
where,
I : solar cell output current;
V : solar cell output voltage;
Ios : solar cell reverse saturation current;
T : solar cell temperature in Celsius;
-19
k : Boltzmann's constant, 1.38*10 J/K;
-23
q : Electron charge, 1.6*10 C;
Ki : Short circuit current temperature coefficient at Iscr;
: Solar irradiation in W/m2;
Iscr : Short circuit current at 25 degree Celsius;
Ilg : Light-generated current;
Eg : Band gap for silicon;
A : Ideality factor;
Tr : Reference temperature;
Ior : Cell saturation current at Tr;
Rsh : Shunt resistance;
Rs : Series resistance;

The solar module characteristic equation is dependent on the number of cells in series
and number of cells in parallel. Also, it has been observed from the experimental results that
the solar cell output current variation is more dependent on the series resistance. The cell
output current is given as,
I=NpIlg-NpIos[exp{qVNs+IRsNp/AkT}-1]-V(Np/Ns)+IRs/Rsh (3.4)

14
 The equivalent circuit of a solar module, with Ns number of series cells and Np number
of cells in parallel, is as shown in Fig. 3.2
.

Fig. 3.2 Equivalent circuit of a solar module

3.3 SOLAR CELL CHARACTERISTICS

The I-V and P-V characteristics of a solar cell at a given temperature and irradiation
are as shown in Fig. 3.3. It can be seen that the cell operates as a constant current source at
low values of operating voltages and as a constant voltage source at low values of current.
The point on the I-V curve that has the highest value of the product of its corresponding
voltage and current, or the highest power output, is called the maximum power point.

Fig. 3.3 I-V, P-V curve of a solar cell at a given temperature and solar irradiation

15
3.3.1 Effect of variation of solar irradiation

The I-V and P-V characteristics of a solar cell are dependent on the incident solar
irradiation. As the solar irradiation increases, the solar input also increases. Both the open
circuit voltage and the short circuit current of the cell also increases as, now the electrons are
supplied with higher excitation energy, thereby increasing the electron mobility, which in turn
leads to more power being generated. Hence, for an increase in the solar irradiation level, the
power magnitude increases for the same voltage value. The I-V and P-V characteristics of a
solar cell, with the variation of irradiation, are as shown in the Fig. 3.4 and Fig. 3.5.

Fig. 3.4 Variation of P-V curve with solar irradiation

Fig. 3.5 Variation of I-V curve with solar irradiation

16
3.3.2 Effect of variation of temperature

Solar cell performance decreases with an increase in the ambient temperature. This
negative impact on the power generation capability is because of an increase in the internal
carrier recombination rates caused by an increase in carrier concentration. An increase in
temperature causes the band gap of the material to increase. Hence, more energy is required to
cross the energy barrier, which in turn causes a decrease in the open circuit voltage value and
a decrease in the efficiency of solar cell. The I-V and P-V characteristics of a solar cell, with
the variation of temperature, are as shown in the Fig. 3.6 and Fig. 3.7.

Fig.3.6 Variation of P-V curve with temperature

Fig. 3.7 Variation of I-V with temperature

17
3.4 MAXIMUM POWER POINT TRACKING
As discussed earlier, for a given insolation and temperature, there exists a unique
operating point corresponding to the maximum power point of the PV array. Therefore, to
extract maximum power from the PV array, it is necessary to operate at the corresponding
MPP as insolation and temperature varies. Also, the I-V curve being non-linear, methods are
to be undertaken to increase the efficiency. One such method is the Maximum Power Point
Tracking, MPPT, used to obtain the maximum power from a varying source. It is done by
varying the duty cycle of a boost converter by using an algorithm. There are several methods
for the MPPT, like the perturbation and observation method, incremental conductance
method, fractional short circuit current method, fractional open circuit voltage method, etc. In
the proposed work, the perturb and observe, or hill climbing method using a current control
algorithm is used for tracking the maximum power point.

3.4.1 Perturb and observe method

Perturb and observe is the most widely used algorithm in MPPT because of its simple
structure and the few measured parameters which are required. In the proposed scheme, the
MPPT operates by periodically measuring the voltage and current of the panel so as to get the
PV output power and then perturbing (i.e. incrementing or decrementing) the array current
and comparing the PV output power with that of the previous perturbation cycle. If the power
is increasing, the perturbation will continue in the same direction in the next cycle, otherwise
the perturbation direction will be reversed. This process is repeated until the maximum power
point is reached. Thus, the proposed algorithm compares the current power reading with the
previous one. If the power has increased, it keeps the same direction (increases current),
otherwise it changes direction (decreases current). This process is repeated at each maximum
power point step until the MPP is reached. After reaching the MPP, the algorithm oscillates
around the correct value. The basic algorithm uses a fixed step to increase or decrease current.
The size of the step determines the size of the deviation while oscillating about the MPP.
Having a smaller step will help reduce the oscillation, but will slow down tracking, while
having a bigger step will help reach MPP faster, but will increase power loss when it
oscillates. The proposed algorithm uses a fixed step of 0.5 to increment or decrement the
current.

18
3.4.2 Flowchart of perturb and observe method

Fig. 3.8 shows the flowchart of perturb and observe method.

Fig. 3.8 Flowchart of perturb and observe method

3.5 CONCLUSION
The modelling of a solar cell, solar cell characteristics and maximum power point
tracking using perturb and observe method were discussed in this chapter.

19
 CHAPTER 4
SINGLE-STAGE DC-AC BOOST CONVERTER

4.1. GENERAL
Conventionally, PV based grid connected systems use a multi-stage topology,
with a dc-dc boost converter and a dc-ac inverter. But depending on the output power and
voltage levels needed, such a system can result in higher volume, cost and a reduced
efficiency and compactness of the system. In order to overcome the above said drawbacks, it
is preferable to use single-stage system, with as many features of a multi-stage system, as
possible. Such systems have advantages of compactness, modularity and higher efficiency.
This chapter introduces a new single-stage DC-AC boost converter topology [20]. The
different modes of operation are also discussed. The design of the converter is also presented.

4.2 SINGLE STAGE DC-AC BOOST CONVERTER

A new single-stage dc-ac converter is proposed, which not only acts as inverter, but
also boosts the output voltage with respect to the input. The proposed topology, as shown in
Fig. 4.1, is based on a full-bridge inverter, but uses a single circuit for dc-dc boost operation
and dc-ac conversion. Two additional diodes and one input inductor implement the two boost
converters that share the same inductor. Switching strategy is similar to a conventional
inverter. In each half cycle, the boost operation is done by one of the two boost converter. For
generating sinusoidal output voltage, a variable duty cycle is applied to the switches.

Fig.4.1 Proposed single stage dc-ac boost converter

20
4.3 MODES OF OPERATION OF THE PROPOSED CONVERTER
There are two states for the converter operation, and in each state, two stages for the
boost operation are defined. For obtaining the sinusoidal output voltage, the duty cycle to the
switches in this structure should be variable. The ac output frequency is taken to be 50Hz and
the switching frequency is taken as 10 kHz. The modes of operation are also discussed.

4.3.1 State I [0<t<T/2]

In state I, the switches T1 and T3 are switched with a frequency of 10 kHz and a
variable duty cycle, while switches T2 and T4 are completely off. This state has two stages.
First stage is when T1 and T3 are on, and the second, when T1 and T3 are off, while in both
stages, T2 and T4 are always off, as shown in Fig. 4.2 and Fig. 4.3.

Fig.4.2 Stage 1 of state I (T1, T3 on T2, T4 off)

Fig.4.3 Stage 2 of state I (T1, T3 off T2, T4 off)

21
 In stage 1 of state I, inductor current increases linearly. This current is alternative and
has tiny fluctuations of switching. At the same time, the capacitor which has a stored energy
from the source and the inductor, discharges through load. As inductor current as well as the
duty cycle is variable, capacitor voltage is also variable. As the load voltage is same as the
capacitor voltage, the positive half cycle of the load voltage is thus obtained. In stage 2, the
inductor discharges, and capacitor gets charged by the source voltage and the inductor current.

4.3.2 State II [T/2<t<T]

In state II, the switches T2 and T4 are switched with a frequency of 10 kHz and a
variable duty cycle, while T1 and T3 are completely off. This state has two stages. First stage
is when T2 and T4 are on, and the second, when T2 and T4 are off, while in both stages, T1 and
T3 are always off, as shown in Fig. 4.4 and Fig. 4.5.

Fig. 4.4 Stage 1 of state II (T2, T4 on T1, T3 off)

Fig. 4.5 Stage 2 of state II (T2, T4 off T1, T3 off)

22
 As the duty cycle for both states is similar, the inductor current and the capacitor
voltage in state 2 are similar to state 1. But, the output voltage in state 2 is negative, as the
switches T2, T4 changes the path of the circuit. Thus, an ac voltage with a higher amplitude is
obtained.

4.4 STEADY STATE ANALYSIS OF THE CONVERTER

The steady state equations of the converter can be written by using the KVL. In stage
1 of state II, there are two loops. Hence, two equations can be attained for this stage as given:

KVL ( )

( ) ( )
( ) }

KVL ( )

( )

As the duty cycle is variable, consequently, in different periods will also be

variable, and hence, the inductor current, and the capacitor voltage, will also be variable.
For stage 2 of state I, by applying the KVL, the following equations can be attained as:

KVL ( )

} ( )
( )

Differentiating,

( )

where,
( )
} ( )
( )

23
 Solving,

( ) ( )

( )
( ) ( ) ( )

( ) ( ) ( )

4.5 SWITCHING STRATEGY

As the output voltage in each half cycle is to be sinusoidal, the duty cycle in each state
for each pair of switches must be variable. Switching strategy is in the way that, switches T1
and T3 are switched in the positive half cycle, while T2 and T4 are off in this state. Switches T2
and T4 are switched in the negative half cycle, while T1 and T3 are off in this state. Sample
pulses for T1 and T3 in the positive half cycle and that for T2 and T4 in the next half cycle are
shown in Fig. 4.6.

Fig. 4.6 Sample pulses for T1 - T3 and T2 - T4

24
 Duty cycle of T1 and T3 during the positive half cycle and the duty cycle of T2 and T4
in the negative half cycle is as shown in Fig. 4.7 and Fig. 4.8.

Fig. 4.7 Variable duty cycle of T1 and T3

Fig. 4.8 Variable duty cycle of T2 and T4

4.6 DESIGN OF THE DC-AC BOOST CONVERTER

The design of the boost inductor and the dc capacitor [20], is as given.

4.6.1 DC capacitor voltage

The minimum dc bus voltage of the converter should be greater than twice the peak of
the phase voltage of the system. The dc bus voltage [21] is calculated as

( )

25
where, m is the modulation index and is taken as 1, and is the ac line output voltage of the
converter, which is 48V.
For of 48 V, is obtained as 71.287 V and is selected as 72 V.

4.6.2 DC capacitor
The value of dc capacitor ( ), of the converter depends upon the instantaneous
energy available to the converter during transients. Using the energy conservation principle,

[ ] ( ) ( )

where, is the reference dc voltage and is the minimum voltage level of dc bus, a is
the overloading factor, Vis the phase voltage, I is the phase current, and t is the time by which
the dc bus voltage is to be recovered.
Taking the minimum voltage level of the dc bus, = 71.5V, = 72 V, V = 33.95 V,
I= 3.39 A, t = 100 s, a = 1.2, the value of is 385 F and is selected as 400 F.

4.6.3 Boost inductor

The value of boost inductor depends on the current ripple and the switching frequency.
( )
( )

where, is the switching frequency, and is the ripple current of the inductor. to be 20
Taking output voltage, = 72 V, input voltage, = 12 V, maximum value of output
current = 3.4 A, and the value of ripple current of inductor to be 20 of maximum value of
output current, the value of is 9 mH and is selected as 10 .

4.7 CONCLUSION
A new single-stage dc-ac boost converter topology has been discussed in this chapter.
The different modes of operation along with the steady state analysis and the working
principle were also dealt with. A switching strategy with variable duty cycle so as to achieve a
sinusoidal voltage waveform was also introduced. The design of the proposed single-stage
converter was also done.

26
 CHAPTER 5
CONTROL SCHEME FOR THE GRID CONNECTED
DC-AC BOOST CONVERTER

5.1 INTRODUCTION
This chapter discusses the control scheme for active power injection and reactive
power compensation for the proposed grid connected dc-ac boost converter. The reference
current generation algorithm and the scheme for duty cycle generation are also discussed.

5.2 CONTROL BLOCK DIAGRAM

The control block diagram with active power injection and reactive power
compensation for the proposed single-stage grid connected dc-ac boost converter is as shown
in Fig. 5.1.

Fig. 5.1 Control block diagram for the proposed system

The proposed single-phase system comprises of a grid connected single-stage step-up

dc-ac boost converter with an RL load and an L filter for harmonic current suppression, a
solar PV array, an MPPT controller utilizing P&O algorithm for tracking the maximum power
point and also for the generation of active current command, a control scheme for the
generation of reactive current command utilizing the actual grid current, a controller for the

27
active power injection and that for the reactive power compensation and a control scheme for
the duty ratio generation with variable pulse width modulation scheme for the dc-ac boost
converter topology.

5.3 UNIT VECTOR FOR SINGLE-PHASE GRID

Unit vector is two unity magnitude fundamental sinusoidal quantities, which are
displaced by 90 from each other. One of the sinusoidal quantities is in phase with the grid
voltage and the other is 90 displaced with respect to the grid voltage. Also, the unit vector
components are always 90 displaced irrespective of the grid frequency. At the zero crossing
of the in phase unit vector component, the 90 displaced unit vector component will be in
peak and vice versa [22]. The unit vector components are as shown in Fig. 5.2. The unit
vector finds diverse uses such as helping to synchronize STATCOM voltage and grid voltage,
separating the individual harmonics in case of active power filters etc.

Fig. 5.2 Unit vector components

The unit vector can be used for the calculation of current reference and also for
extracting the active power component and the reactive power component separately. The in
phase unit vector component is used in extracting the active component of the power, while
the 90 displaced unit vector component is used in extracting the reactive component of the
power.

28
5.4 SCHEME FOR ACTIVE CURRENT EXTRACTION
For the proposed grid connected system, the active current command is obtained from
the MPPT by using the current controlled P&O algorithm. The active current command so
obtained is then multiplied with the in phase component of the unit vector. The resultant so
obtained will give the fundamental active component of the load current.

5.4.1 Expression for active current extraction

Let the grid voltage be,
Vgrid =Vg sinst
Then,
cos = sinst and sin= sin(st-900) (5.1)
The generalized form of load current can be written as,
I I I sin t I cos t
load 0 P s Q s

I 2h

sin 2h t
s 2h
I
2h 1

sin 2h 1 t
s 2h 1

h 1
(5.2)

where,
I0 is the dc component in the load current.
IP is the peak of the active current
IQ is the peak of the reactive current
IP sinSt is the active current present in the load current
IQ cosSt is the reactive current present in the load current
I2h is the peak of even harmonics in the load current
I2h+1 is the peak of odd harmonics in the load current
Let the active current command obtained from MPPT by using the current controlled
P&O algorithm be IP. Multiplying this active current command with cos will result in,
I cos I sin t I sin t (5.3)
P P s P s
which is the same as the active current present in the generalized form of load current,
given in equation (5.3).

29
5.5 SCHEME FOR REACTIVE CURRENT EXTRACTION
For reactive current extraction, the actual load current is first sensed. The sensed load
current is then multiplied with the component of unit vector, which is 90 displaced with
respect to the grid voltage. The resultant fundamental reactive term thus becomes a dc
quantity. Now, using a low pass filter of corner frequency, 1Hz, this dc quantity can be
extracted. This extracted dc quantity is again multiplied with the same 90 displaced
component of the unit vector. The resultant so obtained will give the fundamental reactive
component of the load current.

5.5.1 Expression for reactive current extraction

Let the grid voltage be,
Vgrid =Vg sinst
Then,
cos = sinst and sin= sin(st-900) (5.4)
The generalized form of load current can be written as,
I I I sin t I cos t
load 0 P s Q s

(5.5)
I sin 2h t I sin 2h 1 t
2h s 2h 2h 1 s 2h 1
h 1

Multiplying equation (5.4) by sin given in equation (5.5),

I sin I sin t 90 I sin t sin t 90 I cos t sin t 90

load 0 s P s s Q s s


I sin 2h t I
2h s 2h
2h 1

sin 2h 1 t
s

2h 1
sin t 90
s
h 1
(5.6)
Expanding the above equation, we get,
I cos t I sin t cos t I cos t cos t
0 s P s s Q s s

2h

I sin 2h t
s 2h
I
2h 1

sin 2h 1 t
s
2h 1
cos t
s

h 1
(5.7)

30

I I
Q
I sin I cos t P sin 2 t 1 cos 2 t
load 0 s 2 s 2 s

2
I 2h

sin 2 h 1
s
t
2h
sin 2 h 1
s
t
2h




h 1 I 2h 1



2

sin 2h 2 t
s 2 h 1

sin 2h t
s 2 h 1




(5.8)
I I I
Q Q
I cos t P sin 2 t cos 2 t
2 0 s 2 s 2 s

I 2h
2

sin 2h 1 t
s 2h

sin 2h 1 t
s 2h





h 1 I 2h 1



2

sin 2h 2 t
s 2h 1

sin 2h t
s
2h 1



(5.9)

To get the reactive component peak present in the load current given in the above
equation (5.9), the above result is passed through a low pass filter of corner frequency, 1Hz.
Increasing the corner frequency will pass the 50Hz component present in the equation (5.9),
which is the dc quantity present in the load current, practically which will be absent. The next
frequency will be 100Hz, which is the reflection of fundamental present in the load current.
To avoid this 100Hz component in the output of the low pass filter, the corner frequency is
chosen as 1Hz. The resultant will be,
I
Q (5.10)

2

which is the negative of the half of reactive component peak present in the load
current, given in equation (5.5). Multiplying equation (5.10) with 2sin, results in load current
reference as,

I I
2 sin t 90 I cos t (5.11)
Q Q
I 2 sin
load Re f 2 2 s Q s

which is the same as the reactive current present in the generalized form of load
current, given in equation (5.5).

31
5.6 CONTROL LAW FOR THE CURRENT CONTROLLER
The response of the inverter current can be considered as first order, and its response
can be written as,
dI
conv I I (5.12)
i dt conv conv Re f

where,
Iconv is the inverter current
IconvRef is the converter current reference
i is the time constant chosen for the converter current controller
The voltage equation can be written as,
dI
V L conv V (5.13)
conv dt grid

Combining equation (5.12) and (5.13), the control law can be written as,
I conv Re f I conv
V V L
(5.14)
conv Re f grid
i

where,
dI
1 1 T
I
conv conv

dIconv Ts I
conv Re f
I
conv s
(5.15)
i i
where,
Ts is the sampling time
Rewriting equation (5.14),

V k I I (5.16)
conv
V
conv Re f grid P conv Re f

where,
L
k = Proportional controller constant for the current controller
P
i
For the switching frequency of 10kHz, the sampling time will be 100s. The time
constant of the current controller is taken as 70% of the sampling time. Hence, is chosen to
i
be 70s.

32
5.7 SCHEME FOR DUTY CYCLE GENERATION
The difference between the reference current and the inverter current is taken and is
fed to a proportional current controller. The proportional controller is used so that the make
the grid current track its current reference For obtaining the modulating signal and to scale it
to the carrier signal, the grid voltage, Vg is added to the output from the proportional current
controller, and the resultant signal is divided with the dc bus voltage across the capacitor. A
limiter is used so that the peak magnitude of the modulating signal remains limited to the peak
magnitude of the carrier signal. The high frequency carrier waveform (10kHZ) is then
compared with the modulating signal using comparators. The comparator output is further
used to control the high and low level switches of the proposed single-stage dc-ac converter.

5.8 CONCLUSION
The scheme for active power injection and reactive power compensation for the
proposed grid connected single-stage boost converter has been discussed in this chapter. The
current control scheme with reference current generation algorithm was also discussed. The
scheme for duty cycle generation was also discussed.

33
 CHAPTER 6
SIMULATION OF THE PROPOSED SINGLE-STAGE
GRID CONNECTED BOOST CONVERTER

6.1 INTRODUCTION
The simulation of the proposed single-phase single-stage grid connected dc-ac boost
converter with active power injection and reactive power compensation is discussed in this
chapter. The simulation is done using PSIM software. The results obtained are also discussed.

6.2 SIMULATION PARAMETERS

The circuit parameter values used for the simulation are as given in Table 6.1.

Table 6.1 Table of simulation parameter values

PARAMETER VALUE

Input dc voltage 145 V

Grid voltage 340 V

Solar capacitor 500 F

Boost inductor 110 mH

DC capacitor 4400 F

Load resistor 55
Load inductor 140 mH

Ripple filter 110 mH

Switching frequency 10 kHz

Low pass filter 1 Hz

6.3 SIMULATION DIAGRAM

The simulation diagram of the proposed single-phase single-stage solar PV based grid
connected dc-ac boost converter with active and reactive power control is as shown in Fig. 6.1

34
35
 Fig. 6.2 shows the simulation diagram of MPPT using current controlled P&O
method, and the generation of active current command. The instantaneous value of power is
first calculated using the and values, and is then compared with the previous value of
power using a comparator. A time delay using trigger is used to make the comparator output
high. The output of the comparator is then given to a multiplex, where the increment or
decrement to be done in PV current value is decided. This scheme is as shown in first figure.
The second figure shows the generation of the active current command. Here, the feedback
command is first added to a constant. The resultant is then added to the output from multiplex,
thus providing the increment or decrement to be provided in the value of current command, in
accordance with the maximum power point. The resultant magnitude is then limited by using
a limiter. The output from the limiter is fed to a circular buffer consisting of a comparator and
two sample and hold. The current command is held before being fed back in the next instant,
at the rising edge of the trigger point, by using the first sample and hold,. It is then sent at the
falling edge of the trigger point, by using the second sample and hold. A sine wave is used at
the first comparator input for the zero crossing detection of the generated current command.

Fig. 6.2 Simulation diagram of MPPT using current controlled P&O method and
the generation of active current command

36
 Fig. 6.3 shows the simulation diagram for the generation of the active and reactive
components of the load current and the generation of reference current. The active current
command from MPPT is first limited by using a limiter and then, multiplied with a unity
magnitude in phase template, to obtain the fundamental active component of the load current.
For obtaining the reactive component, the grid current is multiplied with a unity magnitude
90 lagging template. The resultant fundamental term is a dc quantity. This dc quantity is then
extracted using a low pass filter of corner frequency, 1Hz. The extracted dc quantity is limited
by using a limiter and is then multiplied with the same unity magnitude 90 lagging template.
The resultant so obtained gives the fundamental reactive component of the load current. The
sum of the active and the reactive components of the load current will give the reference
current.

Fig. 6.3 Simulation diagram for reference current generation using the active current
command and the reactive current command

Fig. 6.4 shows the simulation diagram for obtaining the variable duty cycle for the
switches of the proposed dc-ac converter. The difference between the reference current and
the inverter current is taken and is given to the proportional current controller. To get the
modulating signal, and to scale it to the carrier signal, the grid voltage is added to the
controller output, and the resultant signal is divided with the dc bus voltage. Peak magnitude
of the modulating signal is limited by limiter. The 10kHz frequency carrier waveform is then
compared with modulating signal using two comparators, to get a variable duty cycle, which

37
is further given for controlling the switches of the proposed dc-ac boost converter.

Fig. 6.4 Simulation diagram for variable duty cycle generation for the switches

6.4 SIMULATION RESULTS

Fig. 6.5 shows the variation of solar irradiation with time. The initial irradiation level
is taken to be as 800W/m2 and at time t= 2sec, it rises to 1000W/m2 till time t= 5sec.

Fig. 6.5 Simulation diagram of variation of irradiation level with time

38
 Fig. 6.6 shows the variation of photovoltaic voltage, with the variation in solar
irradiation. It can be seen that after the initial transient phase, the is constant at 145V for
the irradiation of 800W/m2 till time, t= 2sec. then increases with an increase in irradiation,
and then starts decreasing, as the irradiation reaches 1000W/m2 and finally reaches a steady
state value. The decrease in , with an increase in irradiance and a corresponding increase
in current, is in accordance with the I-V characteristics of the solar cell.

Fig. 6.6 Simulation diagram showing variation of with time

Fig. 6.7 shows the variation of photovoltaic current, with the variation in solar
irradiation. It can be seen that after the initial transient phase, is constant at 4A for the
irradiation of 800W/m2 till time, t= 2sec. then increases with an increase in irradiation, as
the irradiation reaches 1000W/m2, and finally reaches a steady state value. The increase in
, with an increase in solar irradiance, is in accordance with the I-V characteristics of the
solar cell.

39
 Fig 6.7 Simulation diagram showing variation of with time

Fig 6.8 Simulation diagram showing current command generation using P&O method

40
 Fig 6.8 shows the maximum power point tracking, using the current controlled P&O
method. The current command increases from zero, and reaches a steady state value of 2.5A,
for the irradiation of 800W/m2, corresponding to the maximum power point, for this value of
irradiation. As the irradiation increases, current command also increases, and reaches a steady
state value of 3.25A, for the irradiation of 1000W/m2, corresponding to maximum power
point, for this irradiation value.
Fig 6.9 shows the current waveform of the input boost inductor of the dc-ac boost converter.
As the inductor current is equal to the sum of the two boost converter currents, the inductor
current is alternating, which has tiny fluctuations of switching with the frequency of 10kHz.
The ripple of this voltage is depended on inductor value and the switching frequency.The
inductor current magnitude is constant for a given value of irradiance, and increases with an
increase in the irradiance value.

Fig 6.9 Simulation diagram showing the variation of inductor current

41
 Fig. 6.10 shows the voltage waveform of the capacitor of the dc-ac boost converter. As the
stored energy in inductor in each stage is given to the capacitor and as the duty cycle is
variable, like the inductor current, this voltage is also variable and has tiny fluctuation of
switching. The ripple of this voltage is depended on capacitor value and switching frequency.
The capacitor voltage is constant for a given value of irradiance.

Fig 6.10 Simulation diagram showing the variation of capacitor voltage

Fig. 6.11 shows the waveform of the duty cycle in one period, for the upper level
switches, T1 and T3. Fig. 6.12 shows the waveform of the duty cycle in one period, for the
lower level switches, T2 and T4. It can be seen that the duty cycle in both the periods, for both
set of switches, is variable.

42
Fig 6.11 Simulation diagram showing the variation of duty cycle in one period, for T1 and T3

Fig 6.12 Simulation diagram showing the variation of duty cycle in one period, for T2 and T4

Fig. 6.13 shows the waveform of the active current component. As the active current
command is constant for a given value of irradiance, and increases with an increase in the
irradiance value, so does the active current component. Fig. 6.14 shows the waveform of the
reactive current component. This current is always constant for a given value of load.
Fig. 6.15 shows the waveform of reference current, which is the sum of the active and reactive
current components. The reference current is constant for a given value of irradiance, and
increases with an increase in the irradiance, as, the active current increases with an increase in
the irradiance. Fig. 6.16 shows the waveform of converter current. It can be seen that the
converter current tracks its grid current reference at every instant.

43
 Fig 6.13 Simulation diagram showing the variation of active current

Fig 6.14 Simulation diagram showing the variation of reactive current

44
Fig 6.15 Simulation diagram showing the variation of reference current

Fig 6.16 Simulation diagram showing the variation of converter current

45
 Fig. 6.17 shows the waveform of the grid current. Initially, as the active current
component of load current is less, the current drawn from the grid is higher. But, as the active
current value increases, with an increase in the value of irradiance, the grid current demand
starts decreasing. Also, the grid current is constant for a given value of irradiance, as the
active current component is a constant. As the irradiance increases further, the active current
component of load current also increases, and the current drawn from the grid reduces to a
low value. Fig. 6.18 shows the combined waveform of the grid current and the active current
component of the load current, which shows a proportional variation in the value of the grid
current, with an increase in the value of the active current.

Fig 6.17 Simulation diagram showing the variation of grid current

Fig. 6.19 shows the waveform of the net load current. As the load current is the sum
of the active component of load current and the grid current, it is always seen as a constant,
irrespective of the variation in the value of irradiance.

46
Fig 6.18 Simulation diagram showing the variation of active current and grid current

Fig 6.19 Simulation diagram showing the variation of load current

47
 Fig. 6.20 shows the waveform of the proposed single-stage dc-ac converter voltage.
Fig. 6.21 shows the waveform of the grid voltage. Both voltages have the same value.

Fig 6.20 Simulation diagram showing the converter voltage

Fig 6.21 Simulation diagram showing the grid voltage

48
6.5 CONCLUSION
The chapter discussed the simulation of the proposed single-phase single-stage grid
connected dc-ac boost converter with active power injection and reactive power compensation
using the PSIM software. The simulated waveforms along with the results obtained were also
discussed.

49
 CHAPTER 7
HARDWARE IMPLEMENTATION

7.1 INTRODUCTION
This chapter describes the hardware implementation of a single-phase, solar PV based
multi-stage dc-ac converter configuration, with a speed control scheme for a single-phase
induction motor. The results obtained are also discussed.

7.2 DESIGN OF THE DC-DC BOOST CONVERTER

The design of the duty cycle, boost inductor and output capacitor, for the hardware
prototype is as given.

7.2.1 Design of boost inductor

Input power of panel,
Input voltage of converter,
Output voltage of converter,
Now,

( )

where,
D is the duty ratio
Substituting the value in equation (7.1)

( )

or,
Input current of the panel,

( )

( )

50
 Output current of the panel,
( ) ( )
( ) )
Choosing the ripple current of inductor to be 20 of input current,

Now, Boost inductor value,

( )
( )

where,
is the switching frequency = 10kHz
( )

7.2.2 Design of output capacitor

Output capacitor,

( )

Choosing the ripple voltage of capacitor, to be 20 of output voltage,

Capacitor value,

7.4 HARDWARE PARAMETERS

The circuit parameter values used for the hardware prototype are chosen as per the
design values obtained. The hardware parameter values for the hardware set up is as given in
Table 7.1.

51
 Table 7.1 Table of hardware parameter values

PARAMETER VALUE

Solar panel voltage 18 V

Output voltage 60 V

Transformer 230/15V

Microcontroller PIC16F877A

LCD display 1602A

Boost inductor 3.3 mH

DC capacitor 10 F

Boost switching frequency 10 kHz

Boost MOSFET IRF250

MOSFET driver ICL7667

TTL optocoupler 6N137

Inverter MOSFET IRF840

MOSFET driver IR2110

Optocoupler K1010

Switching frequency 50 Hz

Voltage regulator 7805, 7812

Trimming potentiometer 10 k

Glass passivated rectifier W04M

1- Induction motor 0.25HP,230V

7.4 CIRCUIT DIAGRAM

The circuit diagram of the hardware prototype is as shown in Fig. 7.1.

52
Fig 7.1 Circuit diagram of the hardware prototype

53
7.5 HARDWARE SET UP
The hardware set up of the single-phase, solar PV based multi-stage dc-ac converter
configuration, with a speed control scheme for a single-phase induction motor, is as shown in
Fig.7.2. The proposed prototype consists of a power supply unit, a controller unit, an M-board
unit, a dc-dc boost converter, a dc-ac inverter and a single-phase induction motor with a
proximity sensor. The solar module used at the input of the dc-dc boost converter unit is as
shown in Fig.7.3.

POWER SUPPLY UNIT INVERTER UNIT 1-INDUCTION MOTOR

CONTROL UNIT CONVERTER UNIT M-BOARD UNIT PROXIMITY SENSOR

Fig 7.2 Hardware prototype of the solar based multi-stage dc-ac converter

54
 Fig 7.3 Solar module used at the input of dc-dc converter

7.6 DESCRIPTION OF CIRCUIT

The description of different units of the proposed prototype is as follows.

7.6.1 Power supply unit

The 230V is firstly stepped down to 15V using two step down transformers, which is
then supplied to two separate power supply units. In the first unit, the 15V is rectified using a
full wave rectifier, filtered, and given to a 7805 voltage regulator, which is further used for the
working of the PIC microcontroller, LCD and the reset button, and for the working of the
optocoupler of dc-dc converter driver and the optocoupler of inverter driver. In the second
unit, the 15V is rectified using a W04M glass passivated silicon bridge rectifier, filtered, and
given to a 7812 voltage regulator which is then used for the working of the gate driver of the
dc-dc converter MOSFET and the gate driver of the inverter MOSFET. The circuit diagram
and the hardware set up of the power supply unit are given in Fig. 7.4.

55
 (a)
DIODE RECTIFIER VOLTAGE REGULATOR GLASS PASSIVATED RECTIFIER

(b)
Fig 7.4 Power supply unit (a) circuit diagram (b) Hardware prototype

7.6.2 Control unit

The controller unit consists of a PIC16F877A microcontroller, a 1602A 16x2 LCD
display and a reset button. PIC16F877A has 256 bytes EEPROM data memory, 8 channels of
10-bit analog to digital converters, two PWM 10-bit pins and a universal synchronous
asynchronous receiver transmitter (USART). The PIC microcontroller is programmed to
generate the PWM signals for both, the dc-dc boost converter MOSFET as well as the inverter
MOSFETs and also, for displaying readings in the LCD. It also gets a feedback voltage of the
boost converter output and displays it in the LCD.

56
 (a)
RESET CRYSTAL OSCILLATOR PIC16F877A MICROCONTROLLER 1602A LCD

(b)
Fig 7.5 Control unit (a) circuit diagram (b) Hardware prototype

57
7.6.3 M-board unit
The M-board unit is used for controlling the gate of dc-dc converter. The unit
consists of a 6N137 high speed TTL optocoupler, which has a GaAsP LED with an integrated
high gain photo detector for providing isolation, an ICL7667 dual monolithic high speed
MOSFET driver, to convert TTL level signals into outputs with an output voltage swing only
millivolts less than the supply voltage, and a 12V power supply unit for driving the gate driver
IC. The circuit diagram and the hardware set up of the M-board unit are as shown in Fig. 7.6.

(a)
6N137 OPTOCOUPLER ICL7667 MOSFET DRIVER BC547 TRANSISTOR

(b)
Fig 7.6 M-board unit (a) circuit diagram (b) Hardware prototype

58
7.6.4 DC-DC converter unit
The dc-dc converter unit consists of a 3.3mH inductor being supplied from a solar
PV source, an IRF250 n-channel MOSFET, a diode, a 1000F capacitor and a trimming
potentiometer for the output voltage measurement. The circuit diagram and the hardware set
up of the dc-dc converter unit are as shown in Fig. 7.7.

(a)
12mH INDUCTOR IRF250 MOSFET DIODE CAPACITOR TRIMMING POT

(b)
Fig 7.7 Converter unit (a) circuit diagram (b) Hardware prototype

59
7.6.5 Inverter unit
The inverter unit consists of four IRF840 power MOSFETs, four COSMO K1010
optocoupler with infrared emitting diodes, which are optically coupled to phototransistor
detectors, two IR2110 high speed power MOSFET gate drivers, and related circuit elements.
The circuit diagram and the hardware set up of the inverter unit are as shown in Fig. 7.8.

(a)
K1010 OPTOCOUPLER IR2110 MOSFET DRIVER IRF840 MOSFET

(b)
Fig 7.8 Inverter unit (a) circuit diagram (b) Hardware prototype

60
7.7 WORKING
The solar PV panel dc voltage is fed to the dc-dc boost converter. The switching
frequency of the converter MOSFET is 10kHz. The boosted output voltage is fed to the dc-ac
inverter, where, the input dc voltage is inverted to ac voltage with a switching frequency of
50Hz. The output voltage from the inverter is used to drive a single-phase induction motor.
The speed of rotation of the motor is measured using a proximity sensor. The speed of the
motor can be changed by varying the trimming potentiometer. The desired speed at which the
motor is to be rotated can thus be set. PIC16F877A microcontroller is programmed in such a
way, as to generate the PWM signals for both, the dc-dc boost converter MOSFET as well as
the inverter MOSFETs and also, for sensing the speed from the proximity sensor, and for
sensing the set speed using the trimming potentiometer. The microcontroller is also
programmed to displaying readings of the speed of the motor, the desired speed at which the
motor should rotate, and also, the voltage of the dc-dc boost converter output, in the LCD.
When the trimming potentiometer is varied, the width of the pulses to the boost converter
MOSFET varies, and the motor rotates at the desired speed.

7.8 HARDWARE RESULTS

For an input of 18V, an output of 56V was obtained at the output of the dc-dc boost
converter. For this value of input voltage, an output of 51V peak value was obtained at the
inverter output. This verifies the theoretical calculations. The PWM signal obtained at the gate
of the boost converter MOSFET is as shown in Fig. 7.9.

Fig 7.9 Gate pulses of dc-dc boost converter MOSFET

61
 The PWM signals obtained at the gate of the inverter MOSFET is as shown in Fig.
7.10.

Fig 7.10 Gate pulses of inverter MOSFET

The initial speed of the motor was nearly 1400 rpm. By varying the trimming
potentiometer, the desired speed of the motor was set at 900 rpm. The motor speed reduced
correspondingly, and the motor started running at 900 rpm, the set value of speed.

7.9 CONCLUSION
The hardware prototype of a single-phase, solar PV based multi-stage dc-ac converter
configuration, with a speed control scheme for a single-phase induction motor was
implemented. The speed control scheme was also realized.

62
 CHAPTER 8
CONCLUSION

8.1 GENERAL
In this project, a new single-phase single-stage dc-ac boost converter, with lesser
number of switches is modelled. An MPPT algorithm for the solar PV system is developed
using a current control scheme. The concept of unit vector is introduced. A control scheme for
active power injection, and for reactive power compensation, for the grid interfacing of the
proposed single-stage dc-ac boost converter is developed using the unit vector.
To ascertain the effectiveness of the single-stage dc-ac converter, the solar MPPT
algorithm, and the power control scheme, the proposed grid connected system is simulated
using the PSIM. The simulation results show that, for the single stage dc-ac converter, from a
low voltage dc input, an ac voltage with higher amplitude and desired frequency is achieved,
by using a variable duty cycle and by changing the path of capacitor discharge. The
performance of the solar PV system is validated for varying irradiance levels. The simulation
results show that the maximum power point is extracted from the PV array, for each of the
irradiance levels. Also, the active current command is generated by the MPPT algorithm in
accordance with the input irradiance value. The simulation results also validate that, the
fundamental active component of the load current can be obtained by utilizing the in-phase
component of the unit vector and the fundamental reactive component of the load current can
be obtained by utilizing the 90 displaced component of the unit vector. The grid current
reference is also obtained. It is found that the converter current tracks its grid current
reference at every instant. It is also seen from the simulation results, that the grid interfaced
solar PV based single-stage system is capable of injecting active power into the grid and is
also able to compensate for the load reactive power. Thus, the performance of the power
controller is found satisfactory.
A hardware prototype with multi-stage topology, with a dc-dc boost converter, and a
dc-ac inverter, with a speed control scheme for a single-phase induction motor is also
implemented and tested. The experimental results demonstrate the validity of the proposed
system.

63
8.2 FUTURE WORKS
For the proposed single-stage dc-ac converter, a separate control scheme for the dc
capacitor can be implemented for regulating its voltage level. The proposed system is
designed for a fixed load. The same can be extended for an instantaneously varying load.
Also, further studies can be carried on total harmonic distortion of grid power quality.
Another area of interest is islanding, a condition in which a distributed generator (solar panel
or wind turbine) continues to generate power and feed the grid, even though the power from
the electrical utility is no longer present. A scheme for islanding detection and protection can
be implemented.

64
 REFERENCES

1. R.O Caceres and I. Barbi (1999) A boost DC-AC converter: analysis, design, and
experimentation. IEEE Power Electronics, 14, 134-141.

2. N. C. Foureaux, L. Adolpho, S.M. Silva, Brito de S, Jose Antonio and De J.

Cardoso Filho (2014) Application of solid state transformers in utility scale solar power
plants, IEEE Photovoltaic Specialist Conference, 3695-3700.

3. H. S. Krishnamoorthy, S. Essakiappan, P. N. Enjeti, R. S. Balog and S. Ahmed

(2012) A new multilevel converter for Megawatt scale solar photovoltaic utility integration,
IEEE Transl. Applied Power Electronics Conference and Exposition, 1431-1438.

4. S. Pouresmaeil, B. Eskandari, and M. T. Bina (2014) Optimized offset modulation

technique for three-phase DC-AC boost-converter, Power Electronics, Drive Systems and
Technologies Conference PED, 193-198.

5. Soeren Baekhoej Kjaer, John K. Pedersen, and Frede Blaabjerg (2005 ) A Review
of Single-Phase Grid-Connected Inverters for PV Modules, IEEE Transaction on Industry
application, 41, Issue: 5, 1292-1305

6. T. Kerekes, R. Teodorescu and U. Borup (2011) Transformer less photovoltaic

inverters connected to the grid, IEEE Applied Power Electronics Conference and Exposition
(APEC),26, 1733-1737.

7. H. Ribeiro, A. Pinto, and B. Borges (2010) Single-Stage DC-AC Converter for

Photovoltaic Systems, IEEE Energy Conversion Congress and Exposition (ECCE), 604-610.

8. Hiren Patel and Vivek Agarwal (2009) A single-stage single-phase transformer-less

doubly grounded grid-connected PV interface, IEEE Transactions on Energy Conversion,
24, 93-101.

65
9. Mihai Ciobotaru, Remus Teodorescu and Frede Blaabjergis (2006) Control of
single-stage single-phase PV inverter, IEEE Power Electronics and Applications, 2005
European Conference,1-10.

10. S. Ozdemir, N. Altin and I. Sefa (2012) Single stage three-level MPPT inverter for
solar supplied systems, Power Electronics, Electrical Drives, Automation and Motion
(SPEEDAM), 103-108.

11. Yuanshen giong, Suxiang Qian and Jianming Xu (2012) Single phase grid
connected photovoltaic system based on boost inverter, Power and Energy Engineering
Conference (APPEEC), 178-180.

12. T.I. Marisa, St. Kourtesib, L. Ekonomouc and G.P. Fotisd marisa (2007)
Modeling of a single-phase photovoltaic inverter, Solar Energy Materials & Solar Cells 9,
17131725.

13. P.Liengpradis and V.Kinnares (2014) Active power control of single-phase grid-
connected system supplying nonlinear load, IEEE Eleectrical Machines and
Systems(ICEMS), 1524-1527.

14. Martin Gahid and Pavol Spanik (2014) Design of photovoltaic solar cell model for
stand-alone renewable system, IEEE ELEKTRO, 285-288.

15. Sachin Jain and Vivek Agarwal (2007) New current control based MPPT
technique for single stage grid connected PV systems, Energy Conversion & Management,
V48, 625-644.

16. Yang Jun, Lian Xiaoqin, Zhang Xiaol, Duan Zhengang and Wang Min (2011)
Versatile PSIM Simulation Model for Photovoltaic Array with MPPT Function, IEEE
International Conference on Intelligent Computation Technology and Automation, 987-990.

66
17. M. El-Habrouk, M. K. Darwish and P. Mehta (2012) A survey of active filters
and reactive power compensation techniques, IEEE Power Electronics and Variable Speed
Drives, 7-12.

18. Leonardo B. G, Campanhol, Srgio A, Oliveira da Silva, Leonardo P. Sampaio

and Azauri A. O. Junior (2014) A grid-connected photovoltaic power system with active
power injection, reactive power compensation and harmonic filtering, IEEE Power
Electronics Conference (COBEP), 642-649.

19. Woo-Jun Cha, Yong-Won Cho and Jung-Min Kwon (2015) Highly efficient
microinverter with soft-switching step-up converter and single-switch-modulation inverter,
IEEE Transactions on Industrial Electronics, 3516-3523.

20. Ali Nahavandi, Mehdi Roostaee and Mohammad Reza Azizi (2016) Single stage
dc-ac boost converter, IEEE Power Electronics, Drive Systems & Technologies Conference,
362-366.

21. Rahul Kumar Agarwal, Ikhlaq Hussain, Bhim Singh (2016) LMF-Based Control
Algorithm for Single Stage Three-Phase Grid Integrated Solar PV System, IEEE Trans. on
Sustainable Energy, V7, 1379-1387.

22. Subhash Joshi T.G, Aby Joseph and Unnikrishnan A.K (2012) Harmonics
extraction of nonlinear load operating in wide frequency variation, IEEE Industrial
Technology (ICIT), 463-468.

67
 5 4 3 2 1

SINGLE STAGE DC TO AC INVERTER

15V

C7
0.1/400V
R1
1K R2
VCC 1K R31 C25 D11 D12
R3 1000MFD/200V
47K Q1 D2 100K 6A10 6A10
IRF840 BY399 R7
U1 100H/1W

10 7
HIN HO
12 1
LIN LO C30 J2

4
15V 11 0.1/400V
ISO1 SHDN 1
FOD817 GND 2 2
COM
6

3
15V VB L3-300V
3
15V VCC CON2
9 RED
GND C3 C4 VDD C8
5
PIC MICRO CONTROLLER D1
1N4007 C5 C6
13
VS
VSS
0.1/400V
C26
D LCD CONNECTOR 10MFD 0.1MFD 10MFD 0.1MFD 1000MFD/200V D
R5
GND IR2110 47K Q2 D3 D14 D15
5V IRF840 BY399 R8 6A10 6A10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
100H/1W
15V 15V

GND
820H

5V

GND
RC4

RC5
5V

5V
R9
1K R10
32

11
120H VCC 1K
GND
VCC

VCC

2 30 RD7
RA0 RD7 RD6
3 29
RA1 RD6 RD5
4 28

4
RA2 RD5 RD4
5 27
RA3 RD4 RD3 ISO2
6 22
RA4 RD3 RD2 FOD817
7 21
RA5 RD2 RD0
19

3
RD0 RD1
20
RD1
8
RE0 GND
9
RE1
10
RE2
40
PIC16F877 RB7
39
RB6
15 38
RCO RB5 15V
16 37
RC1 RB4
17 36
RC2 RB3
18 35
RC4 RC3 RB2 C15
23 34
RC5 RC4 RB1 0.1/400V
24 33 R11
RXD RC5 RB0 1K R12
26
RC7 VCC 1K
R13
RESET CIRCUIT TXD 25
RC6 13
13
27PF
47K Q3
IRF840
D5
BY399 R17
14 U2 100H/1W
14
1
5V 1
12MHZ GND 10 7
TO LOAD
GND

GND

HIN HO
12 1
LIN LO
1

4
15V 11 2
10K 27PF
31

12

ISO3 SHDN
FOD817 GND 2
GND 6
COM CON2

3
15V VB
3
15V VCC
1 2 3 4 9
GND C11 C12 VDD C16
5
D4 VS 0.1/400V
13
1N4007 C13 C14 VSS
7414 7414 10MFD 0.1MFD 10MFD 0.1MFD
R15
GND IR2110 47K Q4 D6
BY399 R18
IRF840 100H/1W
15V 15V
0.1MF
GND
R19
1K R20
VCC 1K

4
ISO4
FOD817

3
C C
GND

BOOST CONVERTER
L1 D7

12MH
UF5408 R14
10K

TO LOAD
VARIABLE
Q5
DC C18
SOURCE IRF250
10MFD R16
10K
GND
VOLTAGE
MMT

M DRIVE

15V

ISOLATION WITH DRIVER1 R24

47K
U6
R23 1K 6N137
5V 2 8 U7

7 1 8
6 2 7
3 GND 3 6 15V
4 5
R21
7667 47K/1W

5
R26 10K R25
Q6 470H A
BC547

R27 R22
10K 10K

B GND B
GND

POWERSUPPLY 7815
CON3
1
2
3

15V
Transformer Rectifier 7805

1 3 5V D16 D17
1

VIN VOUT 1N4007 1N4007

AC-18V
230V

1 3 4 - + 3 C27 C28
1 1000MFD/35V 10MFD/25V
AC

2 4
1000mfd 10mfd CON2
2

D18 D19
1N4007 1N4007

GND
GND

A A

5 4 3 2 1
 INCHANGE Semiconductor

isc Three Terminal Positive Voltage Regulator L7812CV

FEATURES
Output current in excess of 1.5A
Output voltage of 12V
Internal thermal overload protection
Output transition Safe-Area compensation
Minimum Lot-to-Lot variations for robust device
performance and reliable operation

ABSOLUTE MAXIMUM RATINGS(Ta=25)

SYMBOL PARAMETER RATING UNIT

Vi DC input voltage 35 V

Io Output current internally limited

Ptot Power dissipation internally limited

TOP Operating junction temperature 0~150

Tstg Storage temperature -55~150

THERMAL CHARACTERISTICS

SYMBOL PARAMETER MAX UNIT

Rth j-c Thermal Resistance, Junction to Case 5 /W

Rth j-a Thermal Resistance,Junction to Ambient 50 /W

isc websitewww.iscsemi.com 1 isc & iscsemi is registered trademark

 INCHANGE Semiconductor

isc Three Terminal Positive Voltage Regulator L7812CV

ELECTRICAL CHARACTERISTICS
Tj=25 (Vi= 19V, IO=0.5A, Ci= 0.33F, CO= 0.1F unless otherwise specified)

SYMBOL PARAMETER CONDITIONS MIN MAX UNIT

VO Output Voltage Vin=19V; IO=500mA 11.5 12.5 V

VV Line Regulation 14.5VVin30V; IO=500mA 120 mV

Vi Load Regulation 5.0mAIO1.5A;Vin=19V 100 mV

Ib Quiescent Current Vin=19V; IO=1.0A 6.0 mA

b1 Quiescent Current Change 5.0mAIO1.0A;Vin=19V 0.5 mA

b2 Quiescent Current Change 15VVin30V; IO=500mA 0.8 mA

isc websitewww.iscsemi.com 2 isc & iscsemi is registered trademark

 W005M
RECTRON
SEMICONDUCTOR THRU
TECHNICAL SPECIFICATION
SINGLE-PHASE GLASS PASSIVATED W10M
SILICON BRIDGE RECTIFIER
VOLTAGE RANGE 50 to 1000 Volts CURRENT 1.5 Amperes

FEATURES
* High reverse voltage to 1000V
* Surge overload ratings to 50 amperes peak
* Good for printed circuit board assembly
* Mounting position: Any
* Weight: 1.20 grams
WOM
MECHANICAL DATA
* UL listed the recognized component directory, file #E94233 .360 (9.1)
* Epoxy: Device has UL flammability classification 94V-O .340 (8.6)

.217 (5.5)
.197 (5.0)

1.2 1.0
(30.5) (25.4)
MIN. MIN.

.032 (0.8)
POS. .028 (0.7)
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS LEAD

Ratings at 25 o C ambient temperature unless otherwise specified. .220 (5.6)

Single phase, half wave, 60 Hz, resistive or inductive load. .180 (4.6)

For capacitive load, derate current by 20%. .220 (5.6)

.180 (4.6)

Dimensions in inches and (millimeters)

MAXIMUM RATINGS (At T A = 25 oC unless otherwise noted)

RATINGS SYMBOL W005M W01M W02M W04M W06M W08M W10M UNITS
Maximum Recurrent Peak Reverse Voltage VRRM 50 100 200 400 600 800 1000 Volts

Maximum RMS Bridge Input Voltage VRMS 35 70 140 280 420 560 700 Volts
Maximum DC Blocking Voltage VDC 50 100 200 400 600 800 1000 Volts
Maximum Average Forward Rectified Output Current at T A = 25oC IO 1.5 Amps
Peak Forward Surge Current 8.3 ms single half sine-wave
I FSM 50 Amps
superimposed on rated load (JEDEC method)

Operating Temperature Range TJ -55 to + 150 0

C
0
Storage Temperature Range T STG -55 to + 150 C

ELECTRICAL CHARACTERISTICS (At TA = 25oC unless otherwise noted)

CHARACTERISTICS SYMBOL W005M W01M W02M W04M W06M W08M W10M UNITS
Maximum Forward Voltage Drop per element at 1.0A DC VF 1.0 Volts

Maximum Reverse Current at Rated @T A = 25 oC 5.0 uAmps

IR
DC Blocking Voltage per element @T A = 100 o C 1 mAmps

2002-8

This datasheet has been downloaded from http://www.digchip.com at this page

 RATING AND CHARACTERISTIC CURVES ( W005M THRU W10M )

FIG. 1 - MAXIMUM NON-REPETITIVE FORWARD FIG. 2 - TYPICAL FORWARD CURRENT

SURGE CURRENT DERATING CURVE
50 1.6

AVERAGE FORWARD CURRENT, (A)

PEAK FORWARD SURGE CURRENT, (A)

1.4
40 8.3ms Single Half Sine-Wave
(JEDED Method) 1.2

1.0
30
.8
20
.6
60 Hz RESISTIVE OR
.4 INDUCTIVE LOAD
10
.2

0 0
1 2 4 6 8 10 20 40 60 100 20 50 80 110 140 170 200
NUMBER OF CYCLES AT 60Hz AMBIENT TEMPERATURE, ( )

FIG. 3 - TYPICAL INSTANTANEOUS FORWARD FIG. 4 - TYPICAL REVERSE CHARACTERISTICS

CHARACTERISTICS
20 10
INSTANTANEOUS REVERSE CURRENT, (uA)
INSTANTANEOUS FORWARD CURRENT, (A)

10

TJ = 25
Pulse Width = 300us
1% Duty Cycle

1.0
1.0

TJ = 25
0.1
.1

.01 .01
.2 .4 .6 .8 1.0 1.2 1.4 1.6 0 20 40 60 80 100 120 140
INSTANTANEOUS FORWARD VOLTAGE, (V)
PERCENT OF RATED PEAK
REVERSE VOLTAGE, (%)

RECTRON

28/40/44-Pin Enhanced Flash Microcontrollers
Devices Included in this Data Sheet:
PIC16F873A PIC16F876A
PIC16F874A PIC16F877A
High-Performance RISC CPU:
Only 35 single-word instructions to learn
All single-cycle instructions except for program
branches, which are two-cycle
Operating speed: DC 20 MHz clock input
DC 200 ns instruction cycle
Up to 8K x 14 words of Flash Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM),
Up to 256 x 8 bytes of EEPROM Data Memory
Pinout compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via external
crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
Synchronous Serial Port (SSP) with SPI
(Master mode) and I2C (Master/Slave)
Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection
Parallel Slave Port (PSP) 8 bits wide with
external RD, WR and CS controls (40/44-pin only)
Brown-out detection circuitry for
Brown-out Reset (BOR)
PIC16F87XA
Analog Features:
10-bit, up to 8-channel Analog-to-Digital
Converter (A/D)
Brown-out Reset (BOR)
Analog Comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs are externally accessible
Special Microcontroller Features:
100,000 erase/write cycle Enhanced Flash
program memory typical
1,000,000 erase/write cycle Data EEPROM
memory typical
Data EEPROM Retention > 40 years
Self-reprogrammable under software control
In-Circuit Serial Programming (ICSP)
via two pins
Single-supply 5V In-Circuit Serial Programming
Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Programmable code protection
Power saving Sleep mode
Selectable oscillator options
In-Circuit Debug (ICD) via two pins
CMOS Technology:
Low-power, high-speed Flash/EEPROM
technology
Fully static design
Wide operating voltage range (2.0V to 5.5V)
Commercial and Industrial temperature ranges
Low-power consumption

Program Memory Data MSSP

EEPROM 10-bit CCP Timers
Device # Single Word SRAM I/O USART Comparators
Bytes (Bytes) A/D (ch) (PWM) SPI Master 8/16-bit
Instructions (Bytes) 2
I C
PIC16F873A 7.2K 4096 192 128 22 5 2 Yes Yes Yes 2/1 2
PIC16F874A 7.2K 4096 192 128 33 8 2 Yes Yes Yes 2/1 2
PIC16F876A 14.3K 8192 368 256 22 5 2 Yes Yes Yes 2/1 2
PIC16F877A 14.3K 8192 368 256 33 8 2 Yes Yes Yes 2/1 2

2003 Microchip Technology Inc. DS39582B-page 1

PIC16F87XA
Pin Diagrams

28-Pin PDIP, SOIC, SSOP

MCLR/VPP 1 28 RB7/PGD
RA0/AN0 2 27 RB6/PGC
RA1/AN1 3 26 RB5

PIC16F873A/876A
RA2/AN2/VREF-/CVREF 4 25 RB4
RA3/AN3/VREF+ 5 24 RB3/PGM
RA4/T0CKI/C1OUT 6 23 RB2
RA5/AN4/SS/C2OUT 7 22 RB1
VSS 8 21 RB0/INT
OSC1/CLKI 9 20 VDD
OSC2/CLKO 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA

MCLR/VPP
RB7/PGD
RB6/PGC
RA1/AN1
RA0/AN0
28-Pin QFN

RB5
RB4
28
27
26
25
24
23
22
RA2/AN2/VREF-/CVREF 1 21 RB3/PGM
RA3/AN3/VREF+ 2 20 RB2
RA4/T0CKI/C1OUT 3 19 RB1
PIC16F873A
RA5/AN4/SS/C2OUT 4 18 RB0/INT
VSS 5 PIC16F876A 17 VDD
OSC1/CLKI 6 16 VSS
OSC2/CLKO 7 10 15 RC7/RX/DT

12
13
14
11
8
9

RC4/SDI/SDA

RC6/TX/CK
RC2/CCP1
RC3/SCK/SCL

RC5/SDO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2

44-Pin QFN
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK

RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO
44
43
42
41
40
39
38
37
36
35
34

RC7/RX/DT 1 33 OSC2/CLKO
RD4/PSP4 2 32 OSC1/CLKI
RD5/PSP5 3 31 VSS
RD6/PSP6 4 30 VSS
RD7/PSP7 5 29 VDD
VSS
PIC16F874A VDD
6 28
VDD 7 PIC16F877A 27 RE2/CS/AN7
VDD 8 26 RE1/WR/AN6
RB0/INT 9 25 RE0/RD/AN5
RB1 10 24 RA5/AN4/SS/C2OUT
RB2 11 23 RA4/T0CKI/C1OUT
22
12
13
14
15
16
17
18
19
20
21
RA2/AN2/VREF-/CVREF
NC

RB6/PGC
RB7/PGD

RA3/AN3/VREF+
MCLR/VPP
RB3/PGM

RB4
RB5

RA0/AN0
RA1/AN1

DS39582B-page 2 2003 Microchip Technology Inc.

 PIC16F87XA
Pin Diagrams (Continued)

40-Pin PDIP
MCLR/VPP 1 40 RB7/PGD
RA0/AN0 2 39 RB6/PGC
RA1/AN1 3 38 RB5
RA2/AN2/VREF-/CVREF 4 37 RB4
RA3/AN3/VREF+ 5 36 RB3/PGM
RA4/T0CKI/C1OUT 6 35 RB2

PIC16F874A/877A
RA5/AN4/SS/C2OUT 7 34 RB1
RE0/RD/AN5 8 33 RB0/INT
RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
OSC1/CLKI 13 28 RD5/PSP5

RA2/AN2/VREF-/CVREF
OSC2/CLKO 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT

RA3/AN3/VREF+
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO

MCLR/VPP

RB7/PGD
RB6/PGC
RC3/SCK/SCL 18 23 RC4/SDI/SDA

RA1/AN1
RA0/AN0
RD0/PSP0 19 22 RD3/PSP3

RB5
RB4
RD1/PSP1 20 21 RD2/PSP2

NC

NC
44-Pin PLCC

6
5
4
3
2
1
44
43
42
41
40
RA4/T0CKI/C1OUT 39 RB3/PGM
7
RA5/AN4/SS/C2OUT 8 38 RB2
RE0/RD/AN5 9 37 RB1
RE1/WR/AN6 10 36 RB0/INT
RE2/CS/AN7 11 PIC16F874A 35 VDD
VDD 12 34 VSS
VSS 13
PIC16F877A 33 RD7/PSP7
OSC1/CLKI 14 32 RD6/PSP6
OSC2/CLKO 15 31 RD5/PSP5
RC0/T1OSO/T1CK1 16 30 RD4/PSP4
NC 17 9 RC7/RX/DT
18
19
20
21
22
23
24
25
26
27
282
RC1/T1OSI/CCP2
RC3/SCK/SCL
RC4/SDI/SDA
RC6/TX/CK

RC2/CCP1
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC5/SDO

RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3

RC5/SDO

NC
RC4/SDI/SDA

RC6/TX/CK
NC

44-Pin TQFP
44
43
42
41
40
39
38
37
36
35
34

RC7/RX/DT 1 33 NC
RD4/PSP4 2 32 RC0/T1OSO/T1CKI
RD5/PSP5 3 31 OSC2/CLKO
RD6/PSP6 4 30 OSC1/CLKI
RD7/PSP7 5 PIC16F874A 29 VSS
VSS 6 28 VDD
VDD 7
PIC16F877A 27 RE2/CS/AN7
RB0/INT 8 26 RE1/WR/AN6
RB1 9 25 RE0/RD/AN5
RB2 10 24 RA5/AN4/SS/C2OUT
RB3/PGM 11 23 RA4/T0CKI/C1OUT
12
13
14
15
16
17
18
19
20
21
22
RB4
RB5

RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
NC
NC

RB6/PGC
RB7/PGD

RA3/AN3/VREF+
MCLR/VPP

2003 Microchip Technology Inc. DS39582B-page 3

 PIC16F87XA
1.0 DEVICE OVERVIEW The available features are summarized in Table 1-1.
Block diagrams of the PIC16F873A/876A and
This document contains device specific information PIC16F874A/877A devices are provided in Figure 1-1
about the following devices: and Figure 1-2, respectively. The pinouts for these
PIC16F873A device families are listed in Table 1-2 and Table 1-3.
PIC16F874A Additional information may be found in the PICmicro
PIC16F876A Mid-Range Reference Manual (DS33023), which may
PIC16F877A be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip web site. The
PIC16F873A/876A devices are available only in 28-pin Reference Manual should be considered a complemen-
packages, while PIC16F874A/877A devices are avail- tary document to this data sheet and is highly recom-
able in 40-pin and 44-pin packages. All devices in the mended reading for a better understanding of the device
PIC16F87XA family share common architecture with architecture and operation of the peripheral modules.
the following differences:
The PIC16F873A and PIC16F874A have one-half
of the total on-chip memory of the PIC16F876A
and PIC16F877A
The 28-pin devices have three I/O ports, while the
40/44-pin devices have five
The 28-pin devices have fourteen interrupts, while
the 40/44-pin devices have fifteen
The 28-pin devices have five A/D input channels,
while the 40/44-pin devices have eight
The Parallel Slave Port is implemented only on
the 40/44-pin devices

TABLE 1-1: PIC16F87XA DEVICE FEATURES

Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A
Operating Frequency DC 20 MHz DC 20 MHz DC 20 MHz DC 20 MHz
Resets (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR
(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)
Flash Program Memory 4K 4K 8K 8K
(14-bit words)
Data Memory (bytes) 192 192 368 368
EEPROM Data Memory (bytes) 128 128 256 256
Interrupts 14 15 14 15
I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E
Timers 3 3 3 3
Capture/Compare/PWM modules 2 2 2 2
Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART
Parallel Communications PSP PSP
10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels
Analog Comparators 2 2 2 2
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Packages 28-pin PDIP 40-pin PDIP 28-pin PDIP 40-pin PDIP
28-pin SOIC 44-pin PLCC 28-pin SOIC 44-pin PLCC
28-pin SSOP 44-pin TQFP 28-pin SSOP 44-pin TQFP
28-pin QFN 44-pin QFN 28-pin QFN 44-pin QFN

2003 Microchip Technology Inc. DS39582B-page 5

 PIC16F87XA
FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM
13 Data Bus 8 PORTA
Program Counter
RA0/AN0
Flash RA1/AN1
Program RA2/AN2/VREF-/CVREF
Memory RAM RA3/AN3/VREF+
8 Level Stack
(13-bit) File RA4/T0CKI/C1OUT
Registers RA5/AN4/SS/C2OUT
Program 14
RAM Addr(1) PORTB
Bus 9
RB0/INT
Addr MUX RB1
Instruction reg
RB2
Direct Addr 7 Indirect
8 Addr RB3/PGM
RB4
FSR reg RB5
RB6/PGC
Status reg RB7/PGD
8
PORTC
RC0/T1OSO/T1CKI
3 MUX RC1/T1OSI/CCP2
Power-up
Timer RC2/CCP1
RC3/SCK/SCL
Instruction Oscillator
Start-up Timer RC4/SDI/SDA
Decode & ALU
Control RC5/SDO
Power-on RC6/TX/CK
Reset 8
RC7/RX/DT
Timing Watchdog
Generation W reg
Timer PORTD
OSC1/CLKI Brown-out RD0/PSP0
OSC2/CLKO Reset RD1/PSP1
In-Circuit RD2/PSP2
Debugger RD3/PSP3
Low-Voltage RD4/PSP4
Programming RD5/PSP5
RD6/PSP6
RD7/PSP7

PORTE

MCLR VDD, VSS RE0/RD/AN5

RE1/WR/AN6
RE2/CS/AN7

Timer2 Parallel
Timer0 Timer1 10-bit A/D Slave Port

Synchronous Voltage
Data EEPROM CCP1,2 USART Comparator Reference
Serial Port

Device Program Flash Data Memory Data EEPROM

PIC16F874A 4K words 192 Bytes 128 Bytes

PIC16F877A 8K words 368 Bytes 256 Bytes

Note 1: Higher order bits are from the Status register.

2003 Microchip Technology Inc. DS39582B-page 7

 ICL7667

Data Sheet September 4, 2015 FN2853.7

Dual Power MOSFET Driver Features

The ICL7667 is a dual monolithic high-speed driver designed Fast Rise and Fall Times
to convert TTL level signals into high current outputs at - 30ns with 1000pF Load
voltages up to 15V. Its high speed and current output enable
Wide 15V Supply Voltage Range
it to drive large capacitive loads with high slew rates and low
propagation delays. With an output voltage swing only - V+ = +4.5V to +15V
millivolts less than the supply voltage and a maximum supply - V- = -15V to Ground (0V)
voltage of 15V, the ICL7667 is well suited for driving power Low Power Consumption
MOSFETs in high frequency switched-mode power - 4mW with Inputs Low
converters. The ICL7667s high current outputs minimize - 20mW with Inputs High
power losses in the power MOSFETs by rapidly charging
and discharging the gate capacitance. The ICL7667s inputs TTL/CMOS Input Compatible Power Driver
are TTL compatible and can be directly driven by common - ROUT = 7 Typ
pulse-width modulation control ICs. Direct Interface with Common PWM Control ICs

Ordering Information Pin Equivalent to DS0026/DS0056; TSC426

PART TEMP. Pb-Free Available (RoHS Compliant)

NUMBER PART RANGE PKG.
(Note) MARKING (C) PACKAGE DWG. # Applications
ICL7667CBA* 7667 CBA 0 to 70 8 Ld SOIC (N) M8.15 Switching Power Supplies
(No longer
available, DC/DC Converters
recommended
Motor Controllers
replacement:
ICL7667CBAZA)
Pinout
ICL7667CBAZA 7667 CBAZ 0 to 70 8 Ld SOIC (N) M8.15
ICL7667
(Pb-Free)
(8 LD PDIP, SOIC)
ICL7667CPA* 7667 CPA 0 to 70 8 Ld PDIP E8.3 TOP VIEW

ICL7667CPAZ 7667 CPAZ 0 to 70 8 Ld PDIP** E8.3

(Pb-Free) N/C 1 8 N/C

*Add -T suffix for tape and reel. Please refer to TB347 for details IN A 2 7 OUT A
on reel specifications.
V- 3 6 V+
**Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder IN B 4 5 OUT B
processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination Functional Diagram (Each Driver)
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed V+
the Pb-free requirements of IPC/JEDEC J STD-020.
2mA

OUT

IN

V-

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas LLC.
Copyright Intersil Americas LLC. 1999, 2006, 2010, 2015. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 ICL7667

Absolute Maximum Ratings Thermal Information

Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Thermal Resistance (Typical, Note 1, 2) JA (C/W) JC(C/W)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3V to V+ +0.3V 8 Ld PDIP Package . . . . . . . . . . . . . . . 150 N/A
Package Dissipation, TA +25C . . . . . . . . . . . . . . . . . . . . . . .500mW 8 Ld SOIC Package . . . . . . . . . . . . . . . 170 N/A
Maximum Storage Temperature Range . . . . . . . . . . . -65 to +150C
Operating Conditions Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
(SOIC - Lead Tips Only)
ICL7667C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
Supply Voltages: V+ = +4.5V to +15V; V- = Ground to -15V
Logic Inputs: Logic Low = V- < Vin < 0.8V ; Logic High = 2.0V< Vin < http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Pb-free PDIPs can be used for through hole wave solder processing
V+
only. They are not intended for use in Reflow solder processing
applications.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
1. JA is measured with the component mounted on an evaluation PC board in free air.
2. For JC, the case temp location is the center of the exposed metal pad on the package underside.

Electrical Specifications Parameters with MIN and/or MAX limits are 100% tested at +25C, V+ = 0V unless otherwise specified.
Temperature limits established by characterization and are not production tested.

ICL7667C, M ICL7667M

TA = +25C 0C TA +70C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

DC SPECIFICATIONS

Logic 1 Input Voltage VIH V+ = 4.5V 2.0 - - 2.0 - - V

Logic 1 Input Voltage VIH V+V+ = 15V 2.0 - - 2.0 - - V

Logic 0 Input Voltage VIL V+ = 4.5V - - 0.8 - - 0.5 V

Logic 0 Input Voltage VIL V+ = 15V - - 0.8 - - 0.5 V

Input Current IIL V+ = 15V, VIN = 0V and 15V -0.1 - 0.1 -0.1 - 0.1 A

Output Voltage High VOH V+ = 4.5V and 15V V+ -0.05 V+ - V+ -0.1 V+ - V

Output Voltage Low VOL V+ = 4.5V and 15V - 0 0.05 - - 0.1 V

Output Resistance ROUT VIN = VIL, IOUT = -10mA, V+ = 15V - 7 10 - - 12

Output Resistance ROUT VIN = VIH, IOUT = 10mA, V+ = 15V - 8 12 - - 13

Power Supply Current ICC V+ = 15V, VIN = 3V both inputs - 5 7 - - 8 mA

Power Supply Current ICC V+ = 15V, VIN = 0V both inputs - 150 400 - - 400 A

SWITCHING SPECIFICATIONS

Delay Time TD2 (Figure 3) - 35 50 - - 60 ns

Rise Time TR (Figure 3) - 20 30 - - 40 ns

Fall Time TF (Figure 3) - 20 30 - - 40 ns

Delay Time TD1 (Figure 3) - 20 30 - - 40 ns

2 FN2853.7
September 4, 2015
 ICL7667

Test Circuits
V+ = 15V
+5V
90%
INPUT
+
4.7F 0.1F
10%
0.4V
INPUT OUTPUT TD1 TD2

ICL7667 CL = 1000pF tf tr
15V
INPUT RISE AND 90% 90%
FALL TIMES 10ns
OUTPUT
10% 10%
0V

Typical Performance Curves

1s 100
V+ = 15V
90
CL = 1nF
80
V+ = 15V
70

TD1 AND TD2 (ns)

100
60
tr AND tf (ns)

tRISE TD2
50

40
10 TD1
30

tFALL 20

10
1 0
10 100 1000 10k 100k
-55 0 25 70 125
CL (pF) TEMPERATURE (C)

FIGURE 1. RISE AND FALL TIMES vs CL FIGURE 2. TD1, TD2 vs TEMPERATURE

50 30
CL = 1nF V+ = 15V
V+ = 15V
40 200kHz
tr AND tf
10
tr AND tf (ns)

30
IV+ (mA)

20kHz
20
3.0

10

0
1.0
-55 0 25 70 125 10 100 1k 10k 100k
TEMPERATURE (C) CL (pF)

FIGURE 3. tr , tf vs TEMPERATURE FIGURE 4. IV+ vs CL

3 FN2853.7
September 4, 2015
 ICL7667

Typical Performance Curves (Continued)

100 100

V+ = 15V
IV+ (mA)

IV+ (mA)
10 10 V+ = 15V

V+ = 5V
1
1
V+ = 5V

CL = 1nF
CL = 10pF
100A 100mA
10k 100k 1M 10M 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

FIGURE 5. IV+ vs FREQUENCY FIGURE 6. NO LOAD IV+ vs FREQUENCY

50 50

40 40
tr AND tD2 (ns)

30
tD1 AND tf (ns)

30 tr = TD2
tf

20 20

tD1
10
10

CL = 1nF CL = 10pF

0 0
5 10 15 5 10 15
V+ (V) V+ (V)

FIGURE 7. DELAY AND FALL TIMES vs V+ FIGURE 8. RISE TIME vs V+

Detailed Description Input Stage

The ICL7667 is a dual high-power CMOS inverter whose
inputs respond to TTL levels while the outputs can swing as
high as 15V. Its high output current enables it to rapidly
charge and discharge the gate capacitance of power
MOSFETs, minimizing the switching losses in switchmode
power supplies. Since the output stage is CMOS, the output
will swing to within millivolts of both V- and V+ without any
external parts or extra power supplies as required by the
DS0026/56 family. Although most specifications are at
V+ = 15V, the propagation delays and specifications are
almost independent of V+.
In addition to power MOS drivers, the ICL7667 is well suited
for other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where
the load capacitance is large and low propagation delays are
required. Other potential applications include peripheral
power drivers and charge-pump voltage inverters.
The input stage is a large N-Channel FET with a P-Channel
constant-current source. This circuit has a threshold of about
1.5V, relatively independent of the V+ voltage. This means
that the inputs will be directly compatible with TTL over the
entire 4.5V - 15V V+ range. Being CMOS, the inputs draw
less than 1A of current over the entire input voltage range
of V- to V+. The quiescent current or no load supply current
of the ICL7667 is affected by the input voltage, going to
nearly zero when the inputs are at the 0 logic level and rising
to 7mA maximum when both inputs are at the 1 logic level. A
small amount of hysteresis, about 50mV to 100mV at the
input, is generated by positive feedback around the second
stage.
Output Stage
The ICL7667 output is a high-power CMOS inverter,
swinging between V- and V+. At V+ = 15V, the output
impedance of the inverter is typically 7. The high peak

4 FN2853.7
September 4, 2015
 ICL7667
current capability of the ICL7667 enables it to drive a
1000pF load with a rise time of only 40ns. Because the
output stage impedance is very low, up to 300mA will flow
through the series N-Channel and P-Channel output devices
(from V+ to V-) during output transitions. This crossover current
is responsible for a significant portion of the internal power
dissipation of the ICL7667 at high frequencies. It can be
minimized by keeping the rise and fall times of the input to the
ICL7667 below 1s.
Application Notes
Although the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be
paid.
Grounding
Since the input and the high current output current paths
both include the V- pin, it is very important to minimize and
common impedance in the ground return. Since the ICL7667
is an inverter, any common impedance will generate
negative feedback, and will degrade the delay, rise and fall
times. Use a ground plane if possible, or use separate
ground returns for the input and output circuits. To minimize
any common inductance in the ground return, separate the
input and output circuit ground returns as close to the
ICL7667 as is possible.
Bypassing
The rapid charging and discharging of the load capacitance
requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.7F
tantalum capacitor in parallel with a low inductance 0.1F
capacitor is usually sufficient bypassing.
Output Damping
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
Reduce inductance by making printed circuit board traces
as short as possible.
Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
Use a 10 to 30 resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly
increase the rise and fall times.
Use good by-passing techniques to prevent supply
voltage ringing.
Power Dissipation
The power dissipation of the ICL7667 has three main
components:
1. Input inverter current loss
5 FN2853.7
2. Output stage crossover current loss
3. Output stage I2R power loss
The sum of the above must stay within the specified limits for
reliable operation.
As noted above, the input inverter current is input voltage
dependent, with an IV+ of 0.1mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.
The output stage crowbar current is the current that flows
through the series N-Channel and P-Channel devices that
form the output. This current, about 300mA, occurs only
during output transitions. Caution: The inputs should never
be allowed to remain between VIL and VIH since this could
leave the output stage in a high current mode, rapidly
leading to destruction of the device. If only one of the drivers
is being used, be sure to tie the unused input to V- or
ground. NEVER leave an input floating. The average supply
current drawn by the output stage is frequency dependent,
as can be seen in Figure 5 (IV+ vs Frequency graph in the
Typical Characteristics Graphs).
The output stage I2R power dissipation is nothing more than
the product of the output current times the voltage drop
across the output device. In addition to the current drawn by
any resistive load, there will be an output current due to the
charging and discharging of the load capacitance. In most
high frequency circuits the current used to charge and
discharge capacitance dominates, and the power dissipation
is approximately:
P AC = CV V 2 f (EQ. 1)
where C = Load Capacitance, f = Frequency
In cases where the load is a power MOSFET and the gate
drive requirement are described in terms of gate charge, the
ICL7667 power dissipation will be:
P AC = QGV V f (EQ. 2)
where QG = Charge required to switch the gate, in
Coulombs, f = Frequency.
Power MOS Driver Circuits
Power MOS Driver Requirements
Because it has a very high peak current output, the ICL7667
the at driving the gate of power MOS devices. The high
current output is important since it minimizes the time the
power MOS device is in the linear region. Figure 9 is a
typical curve of Charge vs Gate voltage for a power
MOSFET. The flat region is caused by the Miller
capacitance, where the drain-to-gate capacitance is
multiplied by the voltage gain of the FET. This increase in
capacitance occurs while the power MOSFET is in the linear
region and is dissipating significant amounts of power. The
very high current output of the ICL7667 is able to rapidly
September 4, 2015
 ICL7667

overcome this high capacitance and quickly turns the SG1525 IC, except that the outputs are inverted. This
MOSFET fully on or off. inversion is needed since ICL7667 is an inverting buffer.

Transformer Coupled Drive of MOSFETs

18
ID = 1A Transformers are often used for isolation between the logic
16
and control section and the power section of a switching
GATE TO SOURCE VOLTAGE

14 regulator. The high output drive capability of the ICL7667

VDD = 50V
12 enables it to directly drive such transformers. Figure 11
10 VDD = 375V
shows a typical transformer coupled drive circuit. PWM ICs
8 680pF with either active high or active low output can be used in
this circuit, since any inversion required can be obtained by
6
VDD = 200V reversing the windings on the secondaries.
4
630pF
2 Buffered Drivers for Multiple MOSFETs
0 212pF
In very high power applications which use a group of
-2 MOSFETs in parallel, the input capacitance may be very large
0 2 4 6 8 10 12 14 16 18 20 and it can be difficult to charge and discharge quickly.
GATE CHARGE - QG (NANO-COULOMBS)
Figure 13 shows a circuit which works very well with very
FIGURE 9. MOSFET GATE DYNAMIC CHARACTERISTICS large capacitance loads. When the input of the driver is zero,
Q1 is held in conduction by the lower half of the ICL7667 and
Direct Drive of MOSFETs Q2 is clamped off by Q1. When the input goes positive, Q1 is
Figure 11 shows interfaces between the ICL7667 and typical turned off and a current pulse is applied to the gate of Q2 by
switching regulator ICs. Note that unlike the DS0026, the the upper half of the ICL7667 through the transformer, T1.
ICL7667 does not need a dropping resistor and speedup After about 20ns, T1 saturates and Q2 is held on by its own
capacitor between it and the regulator IC. The ICL7667, with CGS and the bootstrap circuit of C1, D1 and R1. This
its high slew rate and high voltage drive can directly drive the bootstrap circuit may not be needed at frequencies greater
gate of the MOSFET. The SG1527 IC is the same as the than 10kHz since the input capacitance of Q2 discharges
slowly.
15V
+165VDC

IRF730
+VC V+

SG1527 ICL7667
IRF730
B

GND V-

FIGURE 10A.

6 FN2853.7
September 4, 2015
6N137, HCNW137, HCNW2601, HCNW2611, HCPL-0600,
HCPL-0601, HCPL-0611, HCPL-0630, HCPL-0631, HCPL-0661,
HCPL-2601, HCPL-2611, HCPL-2630, HCPL-2631, HCPL-4661
High CMR, High Speed TTL Compatible Optocouplers

Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product

Description Features
The 6N137, HCPL-26xx/06xx/4661, HCNW137/26x1 are 15 kV/s minimum Common Mode Rejection (CMR)
optically coupled gates that combine a GaAsP light emit- at VCM= 1 kV for HCNW2611, HCPL-2611, HCPL-4661,
ting diode and an integrated high gain photo detector. HCPL-0611, HCPL-0661
An enable input allows the detector to be strobed. The High speed: 10 MBd typical
output of the detector IC is an open collector Schottky- LSTTL/TTL compatible
clamped transistor. The internal shield provides a guar- Low input current capability: 5 mA
anteed common mode transient immunity specification Guaranteed AC and DC performance over temper
up to 15,000 V/s at Vcm = 1000 V. ature: -40 C to +85 C
This unique design provides maximum AC and DC circuit Available in 8-Pin DIP, SOIC-8, widebody packages
isolation while achieving TTL compatibility. The optocou- Strobable output (single channel products only)
pler AC and DC operational parameters are guaranteed
Safety approval
from -40 C to +85 C allowing troublefree system per-
UL recognized - 3750 Vrms for 1 minute and 5000 Vrms*
formance.
for 1 minute per UL1577 CSA approved
Functional Diagram IEC/EN/DIN EN 60747-5-5 approved with
6N137, HCPL-2601/2611 HCPL-2630/2631/4661 VIORM= 567 Vpeak for 06xx Option 060
HCPL-0600/0601/0611 HCPL-0630/0631/0661
VIORM= 630 Vpeak for 6N137/26xx Option 060
NC 1 8 V CC ANODE 1 1 8 V CC
VIORM=1414 Vpeak for HCNW137/26x1
ANODE 2 7 VE CATHODE 1 2 7 V O1
MIL-PRF-38534 hermetic version available
CATHODE 3 6 VO CATHODE 2 3 6 V O2 (HCPL-56xx/66xx)
NC 4 5 GND ANODE 2 4 5 GND
SHIELD SHIELD Applications
Isolated line receiver
TRUTH TABLE TRUTH TABLE
(POSITIVE LOGIC) (POSITIVE LOGIC) Computer-peripheral interfaces
LED ENABLE OUTPUT LED OUTPUT
ON H L ON L Microprocessor system interfaces
OFF H H OFF H
ON L H Digital isolation for A/D, D/A conversion
OFF L H Switching power supply
ON NC L
OFF NC H Instrument input/output isolation
Ground loop elimination
A 0.1 F bypass capacitor must be connected between pins 5 and 8.
Pulse transformer replacement
Power transistor isolation in motor drives
Isolation of high speed logic systems

*5000 Vrms/1 Minute rating is for HCNW137/26X1 and Option 020

(6N137, HCPL-2601/11/30/31, HCPL-4661) products only.

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
The 6N137, HCPL-26xx, HCPL-06xx, HCPL-4661, HCNW137,
and HCNW26x1 are suitable for high speed logic interfac-
ing, input/output buffering, as line receivers in environ-
ments that conventional line receivers cannot tolerate
and are recommended for use in extremely high ground
or induced noise environments.

Selection Guide
Widebody
Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic
Input Single
On- Single Dual Single Dual Single and Dual
dV/dt VCM Current
Output Channel Channel Channel Channel Channel Channel
(V/s) (V) (mA) Enable Package Package Package Package Package Packages
1000 10 5 YES 6N137
5,000 1,000 5 YES HCPL-0600 HCNW137
NO HCPL-2630 HCPL-0630

10,000
1,000 YES HCPL-2601 HCPL-0601 HCNW2601
NO HCPL-2631 HCPL-0631

15,000
1,000 YES HCPL-2611 HCPL-0611 HCNW2611
NO HCPL-4661 HCPL-0661
1,000 50 YES HCPL-2602 [1]

3, 500 300 YES HCPL-2612[1]

1,000 50 3 YES HCPL-261A[1] HCPL-061A[1]
NO HCPL-263A[1] HCPL-063A[1]
1,000[2] 1,000 YES HCPL-261N[1] HCPL-061N[1]
NO HCPL-263N[1] HCPL-063N[1]
1,000 50 12.5 [3]
HCPL-193x[1]
HCPL-56xx[1]
HCPL-66xx[1]

Notes:
1. Technical data are on separate Avago publications.
2. 15 kV/s with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193x devices.

2
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)

9.65 0.25 7.62 0.25

(0.380 0.010) (0.300 0.010)

TYPE NUMBER 8 7 6 5 6.35 0.25

OPTION CODE* (0.250 0.010)
A XXXXZ DATE CODE

YYWW RU

UL
1 2 3 4 RECOGNITION

1.78 (0.070) MAX.

1.19 (0.047) MAX.
+ 0.076
5 TYP. 0.254 - 0.051

3.56 0.13 + 0.003)

4.70 (0.185) MAX. (0.010 - 0.002)
(0.140 0.005)

0.51 (0.020) MIN.

2.92 (0.115) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
1.080 0.320 0.65 (0.025) MAX. "V" = OPTION 060
(0.043 0.013) OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
**JEDEC Registered Data (for 6N137 only).

8-pin DIP Package with Gull Wing Surface Mount Option 300
(6N137, HCPL-2601/11/30/31, HCPL-4661)
LAND PATTERN RECOMMENDATION
9.65 0.25 1.016 (0.040)
(0.380 0.010)

8 7 6 5

6.350 0.25 10.9 (0.430)

(0.250 0.010)

1 2 3 4

2.0 (0.080)
1.27 (0.050)

1.780 9.65 0.25

(0.070) (0.380 0.010)
1.19 MAX.
(0.047) 7.62 0.25
MAX. (0.300 0.010) + 0.076
0.254 - 0.051
3.56 0.13 + 0.003)
(0.140 0.005) (0.010 - 0.002)

1.080 0.320
(0.043 0.013) 0.635 0.25
(0.025 0.010)
0.635 0.130 12 NOM.
2.54
(0.100) (0.025 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.

5
 IRF840, SiHF840
www.vishay.com
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
Dynamic dV/dt rating
VDS (V) 500 Available
RDS(on) () VGS = 10 V 0.85 Repetitive avalanche rated
Qg max. (nC) 63 Fast switching Available

Qgs (nC) 9.3 Ease of paralleling

Qgd (nC) 32 Simple drive requirements
Configuration Single Material categorization: for definitions of compliance
D please see www.vishay.com/doc?99912
Note
TO-220AB
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non-RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details.
G
DESCRIPTION
Third generation power MOSFETs from Vishay provide the
S
S designer with the best combination of fast switching,
D
G ruggedized device design, low on-resistance and
N-Channel MOSFET cost-effectiveness.
The TO-220AB package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 50 W. The low thermal resistance
and low package cost of the TO-220AB contribute to its
wide acceptance throughout the industry.

ORDERING INFORMATION
Package TO-220AB
IRF840PbF
Lead (Pb)-free
SiHF840-E3
IRF840
SnPb
SiHF840

ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS 20 V
TC = 25 C 8.0
Continuous Drain Current VGS at 10 V ID
TC = 100 C 5.1 A
Pulsed Drain Current a IDM 32
Linear Derating Factor 1.0 W/C
Single Pulse Avalanche Energy b EAS 510 mJ
Repetitive Avalanche Current a IAR 8.0 A
Repetitive Avalanche Energy a EAR 13 mJ
Maximum Power Dissipation TC = 25 C PD 125 W
Peak Diode Recovery dV/dt c dV/dt 3.5 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg -55 to +150
d
C
Soldering Recommendations (Peak temperature) for 10 s 300
10 lbf in
Mounting Torque 6-32 or M3 screw
1.1 Nm
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 C, L = 14 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).
c. ISD 8.0 A, dI/dt 100 A/s, VDD VDS, TJ 150 C.
d. 1.6 mm from case.

S16-0754-Rev. D, 02-May-16 1 Document Number: 91070

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF840, SiHF840
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Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA - 62
Case-to-Sink, Flat, Greased Surface RthCS 0.50 - C/W
Maximum Junction-to-Case (Drain) RthJC - 1.0

SPECIFICATIONS (TJ = 25 C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 A 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 C, ID = 1 mA - 0.78 - V/C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 A 2.0 - 4.0 V
Gate-Source Leakage IGSS VGS = 20 V - - 100 nA
VDS = 500 V, VGS = 0 V - - 25
Zero Gate Voltage Drain Current IDSS A
VDS = 400 V, VGS = 0 V, TJ = 125 C - - 250
Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 4.8 A b - - 0.85
Forward Transconductance gfs VDS = 50 V, ID = 4.8 A b 4.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V, - 1300 -
Output Capacitance Coss VDS = 25 V, - 310 - pF
Reverse Transfer Capacitance Crss f = 1.0 MHz, see fig. 5 - 120 -
Total Gate Charge Qg - - 63
ID = 8 A, VDS = 400 V,
Gate-Source Charge Qgs VGS = 10 V - - 9.3 nC
see fig. 6 and 13 b
Gate-Drain Charge Qgd - - 32
Turn-On Delay Time td(on) - 14 -
Rise Time tr VDD = 250 V, ID = 8 A - 23 -
ns
Turn-Off Delay Time td(off) Rg = 9.1 , RD = 31, see fig. 10 b - 49 -
Fall Time tf - 20 -
Between lead, D

Internal Drain Inductance LD - 4.5 -

6 mm (0.25") from
nH
package and center of G

Internal Source Inductance LS die contact S

- 7.5 -

Gate Input Resistance Rg f = 1 MHz, open drain 0.6 - 2.8

Drain-Source Body Diode Characteristics
MOSFET symbol
Continuous Source-Drain Diode Current IS D
- - 8.0
showing the
A
integral reverse G

Pulsed Diode Forward Current a ISM - - 32

p - n junction diode S

Body Diode Voltage VSD TJ = 25 C, IS = 8 A, VGS = 0 V b - - 2.0 V

Body Diode Reverse Recovery Time trr - 460 970 ns
TJ = 25 C, IF = 8 A, dI/dt = 100 A/s b
Body Diode Reverse Recovery Charge Qrr - 4.2 8.9 C
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 s; duty cycle 2 %.

S16-0754-Rev. D, 02-May-16 2 Document Number: 91070

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF840, SiHF840
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted)

3.0

RDS(on), Drain-to-Source On Resistance

VGS
ID = 8.0 A
Top 15 V
VGS = 10 V
10 V
2.5
8.0 V
ID, Drain Current (A)

7.0 V
101 6.0 V
2.0

(Normalized)
5.5 V
5.0 V
Bottom 4.5 V
1.5

1.0
4.5 V
0.5
100 20 s Pulse Width
TC = 25 C
0.0
100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91070_01 VDS, Drain-to-Source Voltage (V) 91070_04 TJ, Junction Temperature (C)

Fig. 1 - Typical Output Characteristics, TC = 25 C Fig. 4 - Normalized On-Resistance vs. Temperature

VGS 2500
VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
101 10 V Crss = Cgd
2000
8.0 V Coss = Cds + Cgd
ID, Drain Current (A)

7.0 V
Capacitance (pF)

6.0 V
5.5 V 1500 Ciss
4.5 V
5.0 V
Bottom 4.5 V
1000

Coss
500
100 Crss
20 s Pulse Width
TC = 150 C
0
100 101 100 101
91070_02 VDS, Drain-to-Source Voltage (V) 91070_05 VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics, TC = 150 C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

20
ID = 8.0 A
VGS, Gate-to-Source Voltage (V)

150 C VDS = 400 V

101 16
ID, Drain Current (A)

VDS = 250 V

25 C VDS = 100 V
12

8
100

4
20 s Pulse Width
For test circuit
VDS = 50 V
see figure 13
0
4 5 6 7 8 9 10 0 15 30 45 60 75
91070_03 VGS, Gate-to-Source Voltage (V) 91070_06 QG, Total Gate Charge (nC)

Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Drain-to-Source Voltage

S16-0754-Rev. D, 02-May-16 3 Document Number: 91070

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 IRF840, SiHF840
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Vishay Siliconix

8.0
ISD, Reverse Drain Current (A)

150 C

ID, Drain Current (A)

6.0
101

25 C
4.0

2.0

VGS = 0 V
100 0.0
0.4 0.6 0.8 1.0 1.2 1.4 25 50 75 100 125 150
91070_07 VSD, Source-to-Drain Voltage (V) 91070_09 TC, Case Temperature (C)

Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature

RD
102 VDS
Operation in this area limited
5 by RDS(on)
VGS
10 s D.U.T.
2
ID, Drain Current (A)

RG
+
10 - VDD
100 s
5
10 V
2 1 ms Pulse width 1 s
Duty factor 0.1 %
1
10 ms
5 Fig. 10a - Switching Time Test Circuit
TC = 25 C
2 TJ = 150 C VDS
Single Pulse
0.1 90 %
2 5 2 5 2 5 2 5 2 5
0.1 1 10 102 103 104

91070_08 VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area 10 %

VGS
td(on) tr td(off) tf

Fig. 10b - Switching Time Waveforms

10
Thermal Response (ZthJC)

1
0 - 0.5
0.2
0.1 0.1 PDM
0.05
0.02 Single Pulse
0.01 t1
(Thermal Response)
10-2 t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10 102

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

S16-0754-Rev. D, 02-May-16 4 Document Number: 91070

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
www.vishay.com
Vishay Siliconix
TO-220-1
A MILLIMETERS INCHES
E DIM.
MIN. MAX. MIN. MAX.
F
A 4.24 4.65 0.167 0.183
P b 0.69 1.02 0.027 0.040
Q

b(1) 1.14 1.78 0.045 0.070

H(1)

c 0.36 0.61 0.014 0.024

D 14.33 15.85 0.564 0.624
E 9.96 10.52 0.392 0.414
D

e 2.41 2.67 0.095 0.105

e(1) 4.88 5.28 0.192 0.208
F 1.14 1.40 0.045 0.055
H(1) 6.10 6.71 0.240 0.264
1 2 3
J(1) 2.41 2.92 0.095 0.115
L 13.36 14.40 0.526 0.567
L(1)

L(1) 3.33 4.04 0.131 0.159

M* P 3.53 3.94 0.139 0.155
Q 2.54 3.00 0.100 0.118
b(1)
ECN: X15-0364-Rev. C, 14-Dec-15
L

DWG: 6031
Note
M* = 0.052 inches to 0.064 inches (dimension including
protrusion), heatsink hole for HVM

C
b
e
J(1)
e(1)

Package Picture
ASE Xian

Revison: 14-Dec-15 1 Document Number: 66542

For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Data Sheet No. PD60147 rev.U

IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features Product Summary
Floating channel designed for bootstrap operation
Fully operational to +500V or +600V VOFFSET (IR2110) 500V max.
Tolerant to negative transient voltage (IR2113) 600V max.
dV/dt immune
Gate drive supply range from 10 to 20V IO+/- 2A / 2A
Undervoltage lockout for both channels
3.3V logic compatible VOUT 10 - 20V
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset ton/off (typ.) 120 & 94 ns
CMOS Schmitt-triggered inputs with pull-down
Delay Matching (IR2110) 10 ns max.
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels (IR2113) 20ns max.
Outputs in phase with inputs
Packages

Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output chan-
nels. Proprietary HVIC and latch immune CMOS technologies enable 16-Lead SOIC
14-Lead PDIP IR2110S/IR2113S
ruggedized monolithic construction. Logic inputs are compatible with IR2110/IR2113
standard CMOS or LSTTL output, down to 3.3V logic. The output
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 500 or 600 volts.

Typical Connection 




  


 

  

  
   
 

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

www.irf.com 1
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol Definition Min. Max. Units

VB High side floating supply voltage (IR2110) -0.3 525
(IR2113) -0.3 625
VS High side floating supply offset voltage VB - 25 VB + 0.3
VHO High side floating output voltage VS - 0.3 VB + 0.3
VCC Low side fixed supply voltage -0.3 25
V
VLO Low side output voltage -0.3 VCC + 0.3
VDD Logic supply voltage -0.3 VSS + 25
VSS Logic supply offset voltage VCC - 25 VCC + 0.3
VIN Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3
dVs/dt Allowable offset supply voltage transient (figure 2) 50 V/ns
PD Package power dissipation @ TA +25C (14 lead DIP) 1.6
W
(16 lead SOIC) 1.25
RTHJA Thermal resistance, junction to ambient (14 lead DIP) 75
C/W
(16 lead SOIC) 100
TJ Junction temperature 150
TS Storage temperature -55 150 C
TL Lead temperature (soldering, 10 seconds) 300

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Symbol Definition Min. Max. Units
VB High side floating supply absolute voltage VS + 10 VS + 20
VS High side floating supply offset voltage (IR2110) Note 1 500
(IR2113) Note 1 600
VHO High side floating output voltage VS VB
VCC Low side fixed supply voltage 10 20 V
VLO Low side output voltage 0 VCC
VDD Logic supply voltage VSS + 3 VSS + 20
VSS Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) VSS VDD
TA Ambient temperature -40 125 C
Note 1: Logic operational for VS of -4 to +500V. Logic state held for VS of -4V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD.

2 www.irf.com
 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

Dynamic Electrical Characteristics

VBIAS (VCC, VBS, VDD) = 15V, CL = 1000 pF, TA = 25C and VSS = COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Figure 3.

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

ton Turn-on propagation delay 7 120 150 VS = 0V
toff Turn-off propagation delay 8 94 125 VS = 500V/600V
tsd Shutdown propagation delay 9 110 140 VS = 500V/600V
ns
tr Turn-on rise time 10 25 35
tf Turn-off fall time 11 17 25
MT Delay matching, HS & LS (IR2110) 10
turn-on/off (IR2113) 20

Static Electrical Characteristics

VBIAS (VCC, VBS, VDD) = 15V, TA = 25C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

VIH Logic 1 input voltage 12 9.5
VIL Logic 0 input voltage 13 6.0
VOH High level output voltage, VBIAS - VO 14 1.2 V IO = 0A
VOL Low level output voltage, VO 15 0.1 IO = 0A
ILK Offset supply leakage current 16 50 VB=VS = 500V/600V
IQBS Quiescent VBS supply current 17 125 230 VIN = 0V or VDD
IQCC Quiescent VCC supply current 18 180 340 VIN = 0V or VDD
A
IQDD Quiescent VDD supply current 19 15 30 VIN = 0V or VDD
IIN+ Logic 1 input bias current 20 20 40 VIN = VDD
IIN- Logic 0 input bias current 21 1.0 VIN = 0V
VBSUV+ VBS supply undervoltage positive going 22 7.5 8.6 9.7
threshold
VBSUV- VBS supply undervoltage negative going 23 7.0 8.2 9.4
threshold
VCCUV+ VCC supply undervoltage positive going 24 7.4 8.5 9.6
threshold V
VCCUV- VCC supply undervoltage negative going 25 7.0 8.2 9.4
threshold
IO+ Output high short circuit pulsed current 26 2.0 2.5 VO = 0V, VIN = VDD
PW 10 s
A
IO- Output low short circuit pulsed current 27 2.0 2.5 VO = 15V, VIN = 0V
PW 10 s

www.irf.com 3
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

Functional Block Diagram



 
 


  

  

  
 

 

  






 
  
 

  

 

Lead Definitions
Symbol Description
VDD Logic supply
HIN Logic input for high side gate driver output (HO), in phase
SD Logic input for shutdown
LIN Logic input for low side gate driver output (LO), in phase
VSS Logic ground
VB High side floating supply
HO High side gate drive output
VS High side floating supply return
VCC Low side supply
LO Low side gate drive output
COM Low side return

4 www.irf.com
 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

250 250

200 200
Max.
Turn-On Delay Time (ns)

Turn-On Delay Time (ns)

150 150 Typ.

Max.

100 Typ. 100

50 50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (C) VCC/VBS Supply Voltage (V)

Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. VCC/VBS Supply Voltage

250 250
Max.
200 200
Turn-On Delay Time (ns)

Typ.
Turn-Off Delay Time (ns)

150 150

100 100
Max.

Typ.

50 50

0 0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Supply Voltage (V) Temperature (C)

Figure 7C. Turn-On Time vs. VDD Supply Voltage Figure 8A. Turn-Off Time vs. Temperature

250 250

200 200
Max.
Turn-Off Delay Time (ns)
Turn-Off Delay Time (ns)

150
Max.
150
Typ.

100
100
Typ
50
50

0
0
10 12 14 16 18 20
0 2 4 6 8 10 12 14 16 18 20
VDD Supply Voltage (V)
VCC/VBS Supply Voltage (V)

Figure 8B. Turn-Off Time vs. VCC/VBS Supply Voltage Figure 8C. Turn-Off Time vs. VDD Supply Voltage

www.irf.com 7
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

250 250

200 200
Max.
Shutdown Delay Time (ns)

Shutdown Delay time (ns)

150 150
Typ.

Max.

100 100
Typ.

50 50

0 0
-50 -25 0 25 50 75 100 125 10 12 14 16 18 20
Temperature (C) VCC/VBS Supply Voltage (V)

Figure 9A. Shutdown Time vs. Temperature Figure 9B. Shutdown Time vs. VCC/VBS Supply Voltage

250 100
Shutdown Delay Time (ns)

200 80
Max .
Turn-On Rise Time (ns)

150 60

100
Typ 40
M ax.

50 Typ.
20

0
0
0 2 4 6 8 10 12 14 16 18 20
-50 -25 0 25 50 75 100 125
VDD Supply Voltage (V) Temperature (C)

Figure 9C. Shutdown Time vs. VDD Supply Voltage Figure 10A. Turn-On Rise Time vs. Temperature

100 50

80 40
Turn-On Rise Time (ns)

Turn-Off Fall Time (ns)

60 30

Max.
Max.
40 20
Typ. Typ.

20 10

0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)

Figure 10B. Turn-On Rise Time vs. Voltage Figure 11A. Turn-Off Fall Time vs. Temperature

8 www.irf.com
 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

50
15.0

40
12.0

Logic "1" Input Threshold (V)

Turn-Off Fall Time (ns)

Max
Min.
30
9.0

20
6.0
Max.

Typ.
10
3.0

0
0.0
10 12 14 16 18 20
-50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V)
Temperature (C)
Figure 11B. Turn-Off Fall Time vs. Voltage Figure 12A. Logic 1 Input Threshold vs. Tempera-
ture
15 15.0

12
Logic " 1" Input Threshold (V)

12.0
Max.
Logic "0" Input Threshold (V)

9 9.0

6 6.0
Max.
Min.

3
3.0

0
0.0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)

Figure 12B. Logic 1 Input Threshold vs. Voltage Figure 13A. Logic 0 Input Threshold vs. Tempera-
ture
15 5.00

12 4.00
Logic "0" Input Threshold (V)

High Level Output Voltage (V)

9 3.00
Min.
6
2.00

Max.
3
1.00

0
0.00
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)

Figure 13B. Logic 0 Input Threshold vs. Voltage Figure 14A. High Level Output vs. Temperature

www.irf.com 9
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

5.00 1.00

4.00 0.80
High Level Output Voltage (V)

Low Level Output Voltage (V)

3.00 0.60

2.00 0.40

M ax.

1.00 0.20
Max.

0.00 0.00
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)

Figure 14B. High Level Output vs. Voltage Figure 15A. Low Level Output vs. Temperature

1.00 500

0.80 400
Offset Supply Leakage Current (A)
Low Level Output Voltage (V)

0.60 300

0.40 200

0.20 100
M ax.

Max.
0.00 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)

Figure 15B. Low Level Output vs. Voltage Figure 16A. Offset Supply Current vs. Temperature

500 500

400
Offset Supply Leakage Current (A)

400
VBS Supply Current (A)

300 300

Max.
200 200

Typ.
100 Max. 100

0 0
0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125
IR2110 IR2113
V B Boost Voltage (V) Temperature (C)

Figure 16B. Offset Supply Current vs. Voltage Figure 17A. VBS Supply Current vs. Temperature

10 www.irf.com
 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

500 625

400 500

VCC Supply Current (A)

VBS Supply Current (A)

300 375

Max.

200 250
Max.
Typ.

100 125
Typ.

0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBS Floating Supply Voltage (V) Temperature (C)

Figure 17B. VBS Supply Current vs. Voltage Figure 18A. VCC Supply Current vs. Temperature

625 100

500 80
VCC Supply Current (A)

VDD Supply Current (A)

375 60

250 40
Max.
Max.

125 20
Typ.
Typ.

0 0
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VCC Fixed Supply Voltage (V) Temperature (C)

Figure 18B. VCC Supply Current vs. Voltage Figure 19A. VDD Supply Current vs. Temperature

60 100

50
80
Logic "1" Input Bias Current (A)
VDD Supply Current (A)

40
60
30
40
20
Max.

10 20
Typ.

0
0
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)

Figure 19B. VDD Supply Current vs. VDD Voltage Figure 20A. Logic 1 Input Current vs. Temperature

www.irf.com 11
IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

60 5.00
Logic 1 Input Bias Current (A)

50
4.00

Logic "0" Input Bias Current (A)

40
3.00
30
2.00
20

10 1.00
Max.

0
0.00
0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V) Temperature (C)

Figure 20B. Logic 1 Input Current vs. VDD Voltage Figure 21A. Logic 0 Input Current vs. Temperature

5 11.0
Logic 0 Input Bias Current (A)

4 10.0
VBS Undervoltage Lockout + (V)

Max.

3
9.0
Typ.
2
8.0

1 Min.

7.0

0
0 2 4 6 8 10 12 14 16 18 20 6.0
-50 -25 0 25 50 75 100 125
VDD Logic Supply Voltage (V)
Temperature (C)

Figure 21B. Logic 0 Input Current vs. VDD Voltage Figure 22. VBS Undervoltage (+) vs. Temperature

11.0 11.0

10.0 10.0
VCC Undervoltage Lockout + (V)
VBS Undervoltage Lockout - (V)

Max.
Max.

9.0 9.0

Typ.
Typ.
8.0 8.0

Min.

7.0 Min.
7.0

6.0 6.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125

Temperature (C) Temperature (C)

Figure 23. VBS Undervoltage (-) vs. Temperature Figure 24. VCC Undervoltage (+) vs. Temperature

12 www.irf.com
 IR2110(-1-2)(S)PbF/IR2113(-1-2)(S)PbF

11.0 5.00

10.0 4.00
VCC Undervoltage Lockout - (V)

Output Source Current (A)

Max.

Typ.
9.0 3.00
Min.

Typ.
8.0 2.00

7.0 Min. 1.00

6.0 0.00
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (C) Temperature (C)

Figure 25. VCC Undervoltage (-) vs. Temperature Figure 26A. Output Source Current vs. Temperature

5.00 5.00

4.00 4.00
Output Source Current (A)

Output Sink Current (A)

3.00 3.00 Typ.

Min.

2.00 2.00
Typ.

1.00 1.00
Min.

0.00 0.00
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VBIAS Supply Voltage (V) Temperature (C)

Figure 26B. Output Source Current vs. Voltage Figure 27A. Output Sink Current vs. Temperature

320V
5.00 150

125
4.00
Junction Temperature (C)

140V
Output Sink Current (A)

100
3.00

75
2.00
10V
Typ. 50

1.00 Min.
25

0.00 0
10 12 14 16 18 20 1E+2 1E+3 1E+4 1E+5 1E+6
VBIAS Supply Voltage (V) Frequency (Hz)

Figure 27B. Output Sink Current vs. Voltage Figure 28. IR2110/IR2113 TJ vs. Frequency
(IRFBC20) RGATE = 33 , VCC = 15V

www.irf.com 13
 K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER

Description Schematic
The K1010 series consist of an infrared emitting
diode, optically coupled to a phototransistor detector.
They are packaged in a 4-pin DIP package and available
in wide-lead spacing and SMD option.

1. Anode
2. Cathode
3. Emitter
4. Collector
Features
1. Current transfer ratio
( CTRMin. 50% at IF=5mA VCE=5V )
2. High isolation voltage between input and output
( Viso5000Vrms )
3. Pb free and RoHS compliant
4. MSL class 1
5. Agency Approvals
UL Approved (No. E169586): UL1577
c-UL Approved (No. E169586)
VDE Approved (No. 101347): DIN EN60747-5-5
FIMKO Approved: EN60065, EN60950, EN60335
SEMKO Approved: EN60065, EN60950, EN60335
CQC Approved: GB8898-2011, GB4943.1-2011

Applications
System appliances
Measuring instruments
Computer terminals
Programmable controllers
Medical instruments
Physical and chemical equipment
Signal transmission between circuits of different potentials and impedances

Cosmo Electronics Corp. http://www.cosmo-ic.com

Document No. 69P00001.3 -1-
 K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER

Outside Dimension Unit : mm

1.Dual-in-line type. 2.Surface mount type.

K10101X K10104X

7.62
4.60 7.62
6.50
6.50 4.60
3.50

3.50
0~10
0.40
3.00

2.70

0.100.1
0.25

1.20
1.00
10.000.4 2.54
0.25 0.50
1.20

2.54
13.00 13.00

3.Long creepage distance type 4.Long creepage distance

for surface mount type.

K10103X K10106X

10.16
7.62 4.60 7.62
6.50 4.60
6.50
3.50
3.50

0.30

0~10
0.900.25 0.900.25
1.20
0.25

11.80+0.2
3.00

2.70

-0.5
0.25

0.25 2.54

10.160.50
1.20 0.50

2.54
TOLERANCE0.2mm
Device Marking

Notes:
cosmo
1010 cosmo
817 1010
YWW 817
YWW Y: Year code / WW: Week code
: CTR rank

Cosmo Electronics Corp. http://www.cosmo-ic.com

Document No. 69P00001.3 -2-
 K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER

Absolute Maximum Ratings (Ta=25)

Parameter Symbol Rating Unit
Forward current IF 50 mA
Peak forward current IFM 1 A
Input
Reverse voltage VR 6 V
Power dissipation PD 70 mW
Collector-emitter voltage VCEO 80 V
Emitter-collector voltage VECO 6 V
Output
Collector current IC 50 mA
Collector power dissipation PC 150 mW
Total power dissipation Ptot 200 mW
Isolation voltage 1 minute Viso 5000 Vrms
Operating temperature Topr -55 to +115
Storage temperature Tstg -55 to +125
Soldering temperature 10 seconds Tsol 260

Electro-optical Characteristics (Ta=25)

Parameter Symbol Conditions Min. Typ. Max. Unit

Forward voltage VF IF=20mA - 1.2 1.4 V

Peak forward voltage VFM IFM=0.5A - - 3.0 V
Input
Reverse current IR VR=4V - - 10 A

Terminal capacitance Ct V=0, f=1KHz - 30 - pF

Output Collector dark current ICEO VCE=20V, IF=0 - - 0.1 A
IF=5mA, VCE=5V 50 - 600
Current transfer ratio CTR %
IF=1mA, VCE=5V 15 - -
Collector-emitter saturation VCE(sat) IF=20mA, IC=1mA - 0.1 0.2 V
10 11
Transfer Isolation resistance Riso DC500V 5x10 10 -
charac-
teristics Floating capacitance Cf V=0, f=1MHz - 0.6 1.0 pF
Cut-off frequency fC VCC=5V, IC=2mA, RL=100 - 80 - KHz
Response time (Rise) tr - 4 18 s
VCE=2V, IC=2mA, RL=100
Response time (Fall) tf - 3 18 s

Cosmo Electronics Corp. http://www.cosmo-ic.com

Document No. 69P00001.3 -3-
 K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER

Fig.1 Current Transfer Ratio

vs. Forward Current
500
Classification table of current V CE =5V
450 Ta=25
transfer ratio is shown below.

Current Transfer Ratio

400
Marking of 350
K1010 Model No. CTR ( % )
Classification

CTR ( % )
300
K1010 A 80 ~ 160 A 250
K1010 B 130 ~ 260 B 200
K1010 C 200 ~ 400 C
150
K1010 D 300 ~ 600 D
100
K1010 E 50 ~ 600 Blank,A,B,C,D,E
50
0
0 0.5 1 2 5 10 20 50

Forward Current IF (mA)

Fig.2 Collector Power Dissipation Fig.3 Collector Dark Current

vs. Ambient Temperature vs. Ambient Temperature
-5
250 10
VCE=20V
Collector Power Dissipation

10-6
Collector Dark Current

200
-7
10
PC ( mW )

150
ICEO ( A )

-8
10
100 -9
10
-10
50 10
-11
0 10
-55 0 25 50 75 115 125 -55 0 25 50 75 115

Ambient Temperature Ta () Ambient Temperature Ta ()

Fig.4 Forward Current Fig.5 Forward Current
vs. Ambient Temperature vs. Forward Voltage
60 500

Ta=75C
Forward Current IF ( mA )

Forward Current IF ( mA )

50 200
50C 25C
40 100
50

30 0C
20
-25C
20 10
5
10
2

0 1
-55 0 25 50 75 115 125 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

Ambient Temperature Ta () Forward Voltage VF (V)

Cosmo Electronics Corp. http://www.cosmo-ic.com

Document No. 69P00001.3 -4-
 K1010 Series
4PIN PHOTOTRANSISTOR
cosmo PHOTOCOUPLER

Fig.6 Collector Current Fig.7 Relative Current Transfer Ratio

vs. Collector-Emitter Voltage vs. Ambient Temperature
30
150
IF =30mA Ta=25C
20mA IF =5mA

Relative Current Transfer

Collector Current IC (mA)

25 VCE=5V

20 100

Ratio ( % )
15 10mA

10 50
5mA
5

0 0
0 1 2 3 4 5 6 7 8 9 -55 -25 0 25 50 75 115
Collector-Emitter Voltage VCE (V) Ambient Temperature Ta ()

Fig.8 Collector-Emitter Saturation Voltage Fig.9 Collector-Emitter Saturation

vs. Ambient Temperature Voltage vs. Forward Current
0.16 7
IF =20mA Ta=25C
Collector-Emitter Saturation

Collector-Emitter Saturation

0.14
Ic=1mA 6
Ic=0.5mA
0.12
Voltage VCE ( V )

Voltage VCE ( V )

5
Ic=1mA
0.10
4
0.08 Ic=3mA
3
0.06
Ic=5mA
2
0.04
Ic=7mA
0.02 1

0 0
-55 0 25 50 75 115 0 5 10

Ambient Temperature Ta () Forward Current IF (mA)

Fig.10 Response Time (Rise) Fig.11 Response Time (Fall)

vs. Load Resistance vs. Load Resistance
100 100
VCE =2V VCE =2V
Ic=2mA
Response Rise Time ( us )

Response Fall Time ( us )

50 50 Ic=2mA
Ta=25C Ta=25C
tr
20 20 tf

10 10

5 5

2 2
1 1

0.5 0.5

0.2 0.2

0.1 0.1
0.1 1 10 0.1 1 10

Load Resistance RL (K) Load Resistance RL (K)

Cosmo Electronics Corp. http://www.cosmo-ic.com

Document No. 69P00001.3 -5-
 (.100)
3
2

1 2.54
5.23 (.100)
Features (.206)

BL S NT
n Multiturn / Cermet / Industrial / Sealed n Mounting hardware available

LA N IA
AI SIO PL
2.54 2.41
(H-117P)
AV R M n 5 terminal styles
VE S CO (.100) (.095)

E
n RoHS compliant* version available
3
oH

n Tape and reel packaging available

*R

n Chevron seal design n For trimmer applications/processing

2.54 1

guidelines, click here (.100)
n Listed on the QPL for style RJ24 per
MIL-R-22097 and RJR24 per High-Rel
Mil-R-39035 2.54

TN
(.100)

IA
PL
3

OM
oH
C
S 3296 - 3/8 Square Trimpot Trimming Potentiometer
2
1 2.54
*R

(.100) 2.41
(.095)

Electrical Characteristics Product Dimensions

Standard Resistance Range Common Dimensions 3296Y 1.14
.......................10 ohms to 2 megohms 6.40 1.32 10.03 2.54 (.045)

E
RE
(.100)
(see standard resistance table) (.252 .052) (.395) 3
F
AD
Resistance Tolerance............ 10 % std. 1.52 4.83 .13
2
LE

.38
MIN. 1
(tighter tolerance available) (.015) (.060) (.190 .005)
2.54 2.54
1.27 0.1
Absolute Minimum Resistance (.050 .004) 9.53
(.100) (.100)
............................ 1 % or 2 ohms max. (.375)
(whichever is greater) 2.54 3296Z
Contact Resistance Variation (.100)
ADJ. SLOT
1.27 0.1 1.14
(.050 .004) 2.54 (.045)
......................... 1.0 % or 3 ohms max. 2.54
2.19 DIA.

PL AR
(.100)

IA E
OM S E

*
(.100) 3

C ION FRE

NT
(whichever is greater) (.086)
HS RS D 2
.51 .03 DIA. .56
Adjustability
Ro VE LEA
X WIDE
(.020 .001) (.022) 1
2.54
Voltage................................... 0.01 % X
.76
DEEP (.100)
2.54
(.100)
Resistance............................. 0.05 % (.030)

Resolution.................................... Infinite 3296P

Insulation Resistance................ 500 vdc. 2.54 2.54
8.26 .64 2 WIPER

1,000 megohms min. (.100) (.100)

(.325 .025)

Dielectric Strength 3 CCW 1 3 CW

Sea Level................................ 900 vac 2 CLOCKWISE

70,000 Feet............................. 350 vac 2.54
1
Effective Travel..................25 turns nom. 5.23 (.100) MM
(.206) DIMENSIONS:
(INCHES)
Environmental Characteristics 0.25
3296W TOLERANCES: EXCEPT WHERE NOTED
Power Rating (300 volts max.) 2.54
(.100)
2.41
(.095)
(.010)
70 C....................................... 0.5 watt 3
125 C........................................ 0 watt 2 How To Order
Temperature Range.... -55 C to +125 C 2.54 1
Temperature Coefficient.... 100 ppm/C (.100)
3296 W - 1 - 103 __ LF
Seal Test.......................85 C Fluorinert Model
Humidity........MIL-STD-202 Method 103 Style
3296X
96 hours 2.54
Standard or Modified
(2 % TR, 10 Megohms IR) (.100)
Product Indicator
Vibration........ 20 G (1 % TR; 1 % VR) 3
-1 = Standard Product
Shock.......... 100 G (1 % TR; 1 % VR) 2
2.54 1 Resistance Code
Load Life... 1,000 hours 0.5 watt @ 70 C 2.41
(.100)
(3 % TR; 3 % or 3 ohms, (.095) Packaging Designator
whichever is greater, CRV) Blank = Tube (Standard)
Rotational Life........................200 cycles Standard Resistance Table R = Tape and Reel (X and W Pin Styles
Only)
(4 % TR; 3 % or 3 ohms, 1.14
Resistance Resistance A = Ammo Pack (X and W Pin Styles Only)
whichever is greater, CRV) 2.54
(Ohms) (.100) 3Code
(.045)
Tape and reel material meets Antistatic
10 100
Physical Characteristics 20 2 200 ANSI/ESD 5541-2003 packaging standards.
50 1 500
Torque.............................. 3.0 oz-in. max. 100 2.54 101 2.54 Terminations
Mechanical Stops.................. Wiper idles 200 (.100) 201 (.100) LF = 100 % Tin-plated (RoHS compliant)
Terminals........................Solderable pins 500 501 Blank = 90 % Tin / 10 % Lead-plated
1,000 102
Weight........................................ 0.03 oz. (Standard)
2,000 202
Marking............................ Manufacturers 5,000 502 1.14 Consult factory for other available options.
10,000 2.54 103
trademark, resistance code, 20,000 (.100) 3 203
(.045)

wiring diagram, date code, 25,000 253

50,000 2 503
manufacturers model 100,000 1 104
number and style 200,000 2.54 204 2.54
Wiper................ 50 % (Actual TR) 10 % 250,000 (.100) 254 (.100)
500,000 504
Flammability...........................U.L. 94V-0 1,000,000 105
Standard Packaging......50 pcs. per tube 2,000,000 205
Adjustment Tool...............................H-90
Popular values listed in boldface. Special
resistances available.
Fluorinert is a registered trademark of 3M Co.
*RoHS Directive 2002/95/EC Jan. 27, 2003 including annex and RoHS Recast 2011/65/EU June 8, 2011.
Specifications are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specific applications.
 8.89 + .76 /- .51 2
3
(.350 + .030 /- .020) 1

18 + 1.0/ - 0.5 4.0 .03

(709 + .040/ - .020) (.157 .001)
DIA.
12.7 + 0.3/ - 0.25
(.500 + .012/ - .010)

4.83 + .30/ -.25

(.190 + .012/ -.010)

2.41 .25
(.095 .010)

3296 - 3/8 Square Trimpot Trimming Potentiometer 2.54

ALL PINS IN-LINE ON CENTER
(.100)
MM
DIMENSIONS:
(INCHES)
1000/REEL/BOX
Packaging Specifications
SIDE ADJUST TOP ADJUST
3296X-1 3296W-1
3.81 .71
(.150 .028)
28.07 .76 12.70
REF. 8.89 + .76 /- .51
(1.105 .030) (.500) 12.70
(.350 + .030 /- .020) REF.
(.500)
3.81 .71 18 .76
18 .76
(.15 .028) (.709 .030)
(.709 .030)
8.89 + .76 /- .51 29.59 .76
3 2 (1.165 .030)
(.350 + .030 /- .020) 1 3 2
1

18 + 1.0/ - 0.5 4.0 .03

18 + 1.0/ - 0.5 4.0 .03
(709 + .040/ - .020) (.157 .001)
DIA. (709 + .040/ - .020) (.157 .001)
12.7 + 0.3/ - 0.25 DIA.
12.7 + 0.3/ - 0.25
(.500 + .012/ - .010)
(.500 + .012/ - .010)

4.83 + .30/ -.25

4.83 + .30/ -.25
(.190 + .012/ -.010)
(.190 + .012/ -.010)
2.54
(.100)
2.41 .25
2.41 .25
(.095 .010)
(.095 .010)
2.54
ALL PINS IN-LINE ON CENTER
(.100) 2.54
MM ALL PINS IN-LINE ON CENTER
DIMENSIONS: (.100) .51 .051
(INCHES) MM DIA. TYP.
(020 .002)
DIMENSIONS:
1000/REEL/BOX (INCHES)
1000/REEL/BOX
TOP ADJUST
3296W-1
3.81 .71
(.150 .028)
Meets EIA Specification 468.
8.89 + .76 /- .51
(.350 + .030 /- .020) 12.70
REF.
(.500)
18 .76
(.709 .030)
29.59 .76
(1.165 .030) 3 2
1

18 + 1.0/ - 0.5 4.0 .03

(709 + .040/ - .020) (.157 .001)
DIA.
12.7 + 0.3/ - 0.25
(.500 + .012/ - .010)

4.83 + .30/ -.25

(.190 + .012/ -.010)
2.54
(.100)
2.41 .25
(.095 .010)
2.54
ALL PINS IN-LINE ON CENTER
(.100) .51 .051
MM DIA. TYP.
(020 .002)
DIMENSIONS:
(INCHES)
1000/REEL/BOX

REV. 05/16
Trimpot is a registered trademark of Bourns, Inc.
Specifications are subject to change without notice.
The device characteristics and parameters in this data sheet can and do vary in different applications and actual device performance may vary over time.
Users should verify actual device performance in their specific applications.