1. Rangkaian kombinasional.

B C
Gambar rangkaian water level

List program

Library ieee;
Use ieee.std_logic_1164.all;

Entity switch is
Port (A,B,C :in bit;
Y : out bit;
End switch;
Architecture combinasional of switch is
Begin
Y <= ((A AND NOT C) OR (B AND C))AND NOT B;
End combinasional;

Hasil simulasi nova

 Tabel Kebenaran

A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

2. Demultiplexer 4 output
Demultiplexer
Multiplexer

DI Q0
S1

Q3
S4

sel0 sel1
ENB C2 C1

Gambar rangkaian demultiplexer 4 output

List Program
library ieee;
use ieee.std_logic_1164.all;
entity demux is
Port ( Q0,Q1,Q2,Q3 : out std_logic;
sel : in std_logic_vector (1 downto 0);
I : in std_logic);
end demux;
Architecture arch of demux is
begin
process (Q0,Q1,Q2,Q3)
begin
if sel = "00" then Q0 <= I;
else if sel = "01" then Q1 <= I;
else if sel = "10" then Q2 <= I;
else if sel = "11" then Q3 <= I;
end if;
end if;
end if;
end if;
end process;
end arch;
 Hasil simulasi NOVA

Tabel Kebenaran

I Q0 Q1 Q2 Q3 Sel_0 Sel_1
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 0
0 0 0 0 0 1 1
1 1 0 0 0 0 0
1 1 1 0 0 0 1
1 1 1 1 0 1 0
1 1 1 1 1 1 1
3. Decoder 3 ke 8

Decoder

S1 D1

S2 D8

S3

ENB

Gambar rangkaian decoder 3 ke 8

List Program
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (I : in std_logic_vector (2 downto 0);
O : out std_logic_vector (7 downto 0));
end decoder;
architecture behv of decoder is
begin
process (I)
begin
case I is
when "000" => O <= "00000001";
when "001" => O <= "00000010";
when "010" => O <= "00000100";
when "011" => O <= "00001000";
when "100" => O <= "00010000";
when "101" => O <= "00100000";
when "110" => O <= "01000000";
when "111" => O <= "10000000";
when others => O <= "ZZZZZZZZ";
end case;
end process;
end behv;
 Simulasi NOVA

Tabel Kebenaran

Input Output
I0 I1 I2 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
4. Rangkaian Sequensial

List Program
library ieee;
use ieee.std_logic_1164.all;
entity break1 is port(
a, b, c, d: in std_logic;
j, k: in std_logic;
x: out std_logic);
end break1;
architecture exclusive of break1 is
signal func1, func2, func3, func4: std_logic;
begin
func1 <= j or k;
func2 <= j and k;
func3 <= j xor k;
func4 <= j xnor k;

p1: process (a, b, c, d, j, k)

subtype select_type is std_logic_vector(3 downto 0);
begin
case select_type'(a & b & c & d) is
when "1000" => x <= func1;
when "0100" => x <= func2;
when "0010" => x <= func3;
when "0001" => x <= func4;
when others => x <= '-';
end case;
end process;
end;

Hasil Simulasi NOVA

 Tabel Kebenaran

Select Type Input

X
A B C D J K
0 0 0 0 J K -
0 0 0 1 J K J OR K Func 1
0 0 1 0 J K J AND K Func 2
0 0 1 1 J K -
0 1 0 0 J K J XOR K Func 3
0 1 0 1 J K -
0 1 1 0 J K -
0 1 1 1 J K -
1 0 0 0 J K J XNOR K Func 4
1 0 0 1 J K -
1 0 1 0 J K -
1 0 1 1 J K -
1 1 0 0 J K -
1 1 0 1 J K -
1 1 1 0 J K -
1 1 1 1 J K -