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Designing an automotive or
industrial RADAR/LIDAR system
by Paul McCormack, National Semiconductor
I Laser range finding and sensing technology bits). The ADC08D1000, for example, achieves quired range of interest. The transmitted light
continues to find its way into more and more over 7.5 ENOB while sampling at 1 GS/s to interacts with and is changed by the target.
exciting applications as analog technology im- Nyquist. Its input bandwidth of 1.7 GHz en- Some of this light is reflected/scattered back to
proves in performance, cost and availability. Au- ables direct RF conversion in many cases with- the receiver where it is analyzed. The change in
tomotive system designers are currently devel- out the need for expensive and complex down- the properties of the light enables some prop-
oping sophisticated LIDAR systems, intelligent conversion circuit blocks. Its multiple ADC syn- erties of the target to be determined. The time
enough to automatically controll vehicle speed chronisation feature allows sampling frequen- for the light to travel out to the target and back
and braking systems according to traffic condi- cies to be increased beyond 3 GS/s, if required, to the LIDAR module is used to determine the
tions or foreseen problems. Such systems can to meet the demanding technical requirements range to the target. In many systems an ava-
also control distance to other vehicles and ob- of high accuracy rangefinding systems. This lanche photo diode (APD) in the receiver is
stacles and even safety features such as airbags. report will begin with a description of LIDAR used to convert the received light pulse to an
Advancements in this technology improve and a typical LIDAR system using a block electrical signal. The electrical signal is then
driver comfort and, more importantly, safety. diagram to illustrate its main components. generally amplified before digitization by an
This is just one of many applications made pos- ADC. The sampling frequency, analog input
sible by recent developments in LIDAR system The benefits of over-sampling the received sig- bandwidth and dynamic performance of the
technology. Applications range in diversity nal are described before leading into a discus- ADC influence the accuracy of range measure-
from military rangefinding systems which can sion of the ADC08D1000. The CLC5526 is then ment as well as the degree of information that
operate over 100s of kilometres to vehicle detec- described as an example of a digital variable is extracted from the received signal about the
tion systems at toll booths which operate only gain amplifier that can be used to boost the target object. The transmitted pulse is general-
over a few metres. dynamic range of a LIDAR system analog ly attenuated (atmospheric conditions, etc.)
front-end. Finally, the most important and leading to a large difference in strength between
Irrespective of the application, the key analog interesting features of the ADC08D1000 for transmitted and received pulses. Objects in the
component in the front-end receive path of LIDAR applications are also described. near vicinity of the transmitter can also reflect
such a system is the ADC used to digitize the full power signals back to the receiver. This
narrow pulses reflected from near and/or dis- LIDAR is an acronym for light detection and leads to demanding dynamic range require-
tant objects. Such ADCs need very fast sam- ranging. LIDAR uses the same principle as ments for the system. The receive system
pling rates combined with high dynamic per- RADAR. The LIDAR instrument transmits should be sensitive enough to deal with full
formance, large analog input bandwidth and light out to a target. In the example of an auto- power and very low reflected pulses. Dynamic
low power consumption. Nationals new GIGA- motive system, the target may be another car or range requirements in the order of 100 dB are
HERTZ 8-bit ADC family can digitise analog any other obstacle in its path. The main com- not uncommon. This dynamic range is gener-
input signals at up to 3 GS/s while still main- ponent in the transmitter stage is a laser capa- ally achieved by using a VGA (variable gain am-
taining over 7.0 ENOB (effective number of ble of transmitting narrow pulses over the re- plifier) or DVGA (digital VGA) in the front end
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accomplished by a 3-bit parallel gain control input and a data valid pin
to latch the data. It can be used in conjunction with the ADC08D1000
and FPGA to boost the receive channel dynamic range. The DVGA, in
conjunction with the FPGA forms an automatic levelling loop that com-
presses the dynamic range of the input signal prior to sampling by the
ADC. By doing so, it extends the dynamic range of the ADC by as much
as 42 dB. In practice, the gain loop is implemented as follows. The FPGA
is used to measure the ADC output signal power and directly control the
CLC5526 gain based on this power measurement. This should be per-
formed in such a manner that the DVGA gain steps are user transparent,
i.e. the gain compensation function in the FPGA should remove the
DVGA gain steps at the output. The time alignment of this gain compen-
sation circuit should be adjusted to support the ADC latency, which is
13...14.5 clock cycles for the ADC08D1000. Figure 3 illustrates an exam-
ple of how the CLC5526 may be used to drive the differential inputs of
the ADC08D1000.
The dual edge sampling (DES) feature causes one of the two input pairs
to be routed to both ADCs. The other input pair is deactivated. One of
the ADCs samples the input signal on one input clock edge (the duty cycle
correction circuitry allows a clock duty cycle of 80/20% even in DES
mode), the other samples the input signal on the other input clock edge
(also duty cycle corrected). The result is a 4:1 de-multiplexed output with
a sample rate that is twice the input clock frequency. Therefore, the total
sample rate with a 1 GHz clock is 2 GS/s and the output data rate is
500 Mbit/s on each of the parallel differential LVDS buses.
The ADC08D1000 has the capability to precisely reset its sampling clock
input to DCLK output relationship as determined by the user-supplied
DCLK_RST pulse. This allows multiple ADCs in a system to have their
DCLK (and data) outputs transition at the same time with respect to the
shared CLK input that they all use for sampling. This enables system de-
signers to achieve sampling frequencies in excess of 2 GS/s, i.e. two
ADC08D1000s could be interleaved in DES mode to achieve a total of
4 GS/s. This naturally requires careful circuit and board layout design, the
clock trace should be the same length between devices to precisely match
trace delays. Timing mismatches lead to increased harmonic distortion at
the converters output. In figure 4, the DES feature is illustrated with a
200 MHz input signal. The performance is so good that ENOB only drops
by 0.1 bits when the sampling frequency is doubled from 1 GS/s to 2 GS/s.
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