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Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E


Engineering & Technology, Radaur

VHDL LAB Page:1

V.H.D.L LAB
For VI Semester B.TECH.

Electronics and Communication Engineering


(As per KUK Syllabus)

VHDL MANUAL 1 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:2

SL.NO NAME OF THE EXPERIMENT


1 LOGIC GATES
2 ADDERS AND SUBTRACTORS
3 COMBINATIONAL DESIGNS
a.2 TO 4 DECODER
b.8 TO 3 ENCODER
c.8 TO 1 MULTIPLEXER
d.4 BIT BINARY TO GRAY CONVERTER
e. MULTIPLEXER, DE-MULTIPLEXER,
COMPARATOR

4 FULL ADDER(3 MODELING STYLES)


5 32 BIT ALU USING THE SCHEMATIC DIAGRAM
6 FLIP-FLOPS (SR, D, JK AND T)
7 4 BIT BINARY,BCD COUNTERS
SYNCHRONOUS & ASYNCHRONOUS COUNTERS
ADDITIONAL EXPERIMENTS
8 RING COUNTER
9 JHONSON COUNTER
INTERFACING
1 DC AND STEPPER MOTOR
2 EXTERNAL LIGHT CONTROL
3 WAVEFORM GENERATION USING DAC
4 SEVEN SEGMENT DISPLAY

VHDL MANUAL 2 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:3

EXPERIMENTS LIST

PROGRAMMING (using VHDL)

1.Write VHDL code to realize all the gates.


2.Write a VHDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, de-multiplexer, comparator.
3. Write a VHDL code to describe the functions of a full adder using three modeling
styles.
4. Write a model for 32 bit ALU using the schematic diagram shown below
A(31:0)

Opcode(3:0)

Enable

ALU should use the combinational logic to calculate an output based on the four
bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below.

VHDL MANUAL 3 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:4

OPCODE ALU OPERATION


1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XNOR B

5. Develop the VHDL code for the following flip-flop, SR, D, JK, T.
6. Design 4 bit binary , BCD counters (Synchronous reset and asynchronous reset) and
any sequence counters

INTERFACING (at least four of the following must be covered using VHDL)

1. Write VHDL code display messenger on the given seven segment display and
LCD and accepting Hex key pad input data.
2. Write VHDL code to control speed, direction of DC and stepper motor.
3. Write VHDL code to accept 8 channel analog signal, Temperature sensors and
display the data on LC panel or seven segment display
4. Write VHDL code to generate different waveforms (Sine, Square, Triangle,
Ramp etc.,)using DAC change the frequency and amplitude.
5. Write VH DL code to simulate Elevator operation
6. Write VHDL code to control external light using relays.
*******************

VHDL MANUAL 4 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:5

VHDL MANUAL

It is one of most popular software tool used to synthesize VHDL code. This tool
Includes many steps. To make user feel comfortable with the tool the steps are
given below:-
HDLnavigator.
Double click on Project MANUAL (Assumed icon is present on desktop).
Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\example
Top level module : HDL
In NEW PROJECT dropdown Dialog box, Choose your appropriate device
specification. Example is given below:
Device family : Spartan2
Device : xc2s200
Package : PQ208
TOP Level Module : HDL
Synthesis Tool : XST
Simulation : Modelsim / others
Generate sim lang : VHDL
In source window right click on specification, select new source
Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHDL source file. Click Next and finish the initial Project
preparation.

Double click on synthesis. If error occurs edit and correct VHDL code.
Double click on Lunch modelsim (or any equivalent simulator if you are using) for
functional simulation of your design.
Right click on sample.VHDL in source window, select new source
Select source : Implementation constraints file.
File name : sample
This will create sample. UCF constraints file.
Double click on Edit constraint (Text) in process window.
Edit and enter pin constraints with syntax:
NET NETNAME LOC = PIN NAME

VHDL MANUAL 5 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:6

Double click on Implement, which will carry out translate, mapping, place and route
of your design. Also generate program file by double clicking on it, intern which
will create .bit file.
Connect JTAG cable between your kit and parallel pot of your computer.
Double click on configure device and select mode in which you want to configure
your device. For ex: select slave serial mode in configuration window and finish
your configuration.
Right click on device and select program. Verify your design giving appropriate
inputs and check for the output.
Also verify the actual working of the circuit using pattern generator & logic
analyzer.

VHDL MANUAL 6 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:7

EXPERIMENT NO. 1

WRITE VHDL CODE TO REALIZE ALL LOGIC GATES

AIM: Simulation and realization of all logic gates.

COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.

Truth table with symbols

VHDL MANUAL 7 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:8

Black Box
VHDL MANUAL 8 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:9

c
a d
LOGIC e
GATES f
b g
h
i

Truth table Basic gates:


a b c d e f g h i
0 0 0 0 1 1 1 0 1
0 1 0 1 1 1 0 1 0
1 0 0 1 0 1 0 1 0
1 1 1 1 0 0 0 0 1

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gates is
Port ( a,b : in std_logic;
c,d,e,f,g,h,i : out std_logic);
end gates;

architecture dataflw of gates is

begin
c<= a and b;
d<= a or b;
e<= not a;
f<= a nand b;
g<= a nor b;
h<= a xor b;
i<= a xnor b;
end dataflw;

VHDL MANUAL 9 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:10

Procedure to view output on Model sim


1. After the program is synthesized create a Test bench, load the input.
2. Highlight the tbw file and click onto Modelsim Simulate behavioral model.
3. Now click the waveform and zoom it to view the result.
Modelsim Output

Output (c to i)

PROCEDURE TO DOWNLOAD ONTO FPGA


1) Create a UCF(User Constraints File).
2) Click on UCF file and choose assign package pins option as shown in the figure
below.

VHDL MANUAL 10 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:11

3)Assign the package pins as shown in fig below

VHDL MANUAL 11 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:12

3) save the file.


4) Click on the module and choose configure device option.
5) The following icon will be displayed.

VHDL MANUAL 12 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:13

6) Right click on the icon and select program option.


7) Program succeeded message will be displayed.
8) Make connections to main board and daughter boards( before configuring ) , give
necessary inputs from DIP SWITCH and observe the output on LEDs.

NET "a" LOC = "p74" ;


NET "b" LOC = "p75" ;
NET "c" LOC = "p84" ;
NET "d" LOC = "p114" ;
NET "e" LOC = "p113" ;
NET "f" LOC = "p115" ;
NET "g" LOC = "p117" ;
NET "h" LOC = "p118" ;
NET "i" LOC = "p121" ;

Repeat the above Procedure to all the Programs.

RESULT: The logic gates design have been realized and simulated using HDL codes.

VHDL MANUAL 13 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:14

EXPERIMENT NO.2
AIM: Write a VHDL code to describe the functions of Half adder, Half Subtractor and Full
Subtractor.

COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.

(a) HALF ADDER


TRUTH TABLE BASIC GATES

INPUTS OUTPUTS
A B S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

BOOLEAN EXPRESSIONS:
S=A B
C=A B

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HA is
Port ( a, b : in std_logic;
s, c : out std_logic);
end HA;

architecture dataflow of HA is

begin
s<= a xor b;
VHDL MANUAL 14 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:15

c<= a and b;
end dataflow;

(b)HALF SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:

INPUTS OUTPUTS D=A B


_
A B D Br Br = A B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

BASIC GATES

VHDL MANUAL 15 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:16

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity hs is
Port ( a, b : in std_logic;
d, br : out std_logic);
end hs;

architecture dataflow of hs is

begin
d<= a xor b;
br<= (not a) and b;

end dataflow;

VHDL MANUAL 16 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:17

(C)FULL SUBTRACTOR

TRUTH TABLE BOOLEAN EXPRESSIONS:


INPUTS OUTPUTS D= A B C
A B Cin D Br _ _
Br= A B + B Cin + A Cin
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
BASIC GATES

VHDL MANUAL 17 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:18

VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOG IC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fs is
Port ( a, b, c : in std_logic;
d, br : out std_logic);
end fs;

architecture dataflw of fs is
begin
d<= a xor b xor c;
br<= ((not a) and (b xor c)) or (b and c);
end datafolw;

RESULT: The half adder, half subtractor and full subtractor designs have been realized and
simulated using HDL codes.

VHDL MANUAL 18 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:19

EXPERIMENT NO.3
AIM: Write HDL codes for the following combinational circuits.

COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.

3.a) 2 TO 4 DECODER

BLACK BOX

Y0
Sel 0 2 to 4
Sel 1 Y1
Decoder Y2
E Y4

Truth Table of 2 to 4 decoder

E Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0

VHDL MANUAL 19 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:20

DATA FLOW
VHDL CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec2_4 is
port (a, b, en :in std_logic ;
y0, y1, y2, y3:out std_logic);
end dec2_4;

architecture data flow of dec2_4 is


begin
y0<= (not a) and (not b) and en;
y1<= (not a) and b and en;
y2<= a and (not b) and en;
y3<= a and b and en;
end dataflow;

NET "e" LOC = "p74";


NET "sel<0>" LOC = "p75";
NET "sel<1>" LOC = "p76";
NET "y<0>" LOC = "p112";
NET "y<1>" LOC = "p114";
NET "y<2>" LOC = "p113";
NET "y<3>" LOC = "p115";

Simulation is done using Modelsim


Waveform window : Displays output waveform for verification.

VHDL MANUAL 20 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:21

Output

3.b) 8 TO 3 ENCODER WITH PRIORITY

Black Box

i7 Z3

8:3 Z1
Parity Z0
Encoder
enx
i0 V

en

Truth table

VHDL MANUAL 21 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:22

En I7 I6 I5 I4 I3 I2 I1 I0 Z2 Z1 Z0 enx V
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 0 1 1 1 0 1
0 1 1 1 1 1 1 0 X 1 1 0 0 1
0 1 1 1 1 1 0 X X 1 0 1 0 1
0 1 1 1 1 0 X X X 1 0 0 0 1
0 1 1 1 0 x X X X 0 1 1 0 1
0 1 1 0 X X X X X 0 1 0 0 1
0 1 0 X X X X X X 0 0 1 0 1
0 0 X X X X X X X 0 0 0 0 1

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder8_3 is
Port ( i : in std_logic_vector(7 downto 0);
en : in std_logic;
enx,V : out std_logic;
z : out std_logic_vector(2 downto 0));
end enco2;

architecture behavioral of encoder8_3 is


begin

end behavioral ;

VHDL MANUAL 22 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:23

#PACE: Start of Constraints generated by PACE


#PACE: Start of PACE I/O Pin Assignments
NET "en" LOC = "p84";
NET "i<0>" LOC = "p85";
NET "i<1>" LOC = "p86";
NET "i<2>" LOC = "p87";
NET "i<3>" LOC = "p93";
NET "i<4>" LOC = "p94";
NET "i<5>" LOC = "p95";
NET "i<6>" LOC = "p100";
NET "i<7>" LOC = "p74";
NET "enx" LOC = "p112";
NET "V" LOC = "p114";
NET "z<0>" LOC = "p113";
NET "z<1>" LOC = "p115";
NET "z<2>" LOC = "p117";

Output

3.c) 8 TO 1 MULTIPLEXER

Black Box

b
c
d 8:1Mux Z
e
f
g
VHDL MANUAL 23 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:24

h
sel (2 to 0)

Truth table
Sel2 Sel1 Sel0 Z
0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
1 1 1 H

VHDL CODE
entity mux8_1 is
port(I: in std_logic_vector (7 downto 0);
S: in std_logic_vector (2 downto 0);
en: in std_logic; y: out std_logic);
end mux8_1;
architecture behavioral of mux8_1 is
begin
process (I,s,en) is
begin
if en=1 then
if S=000 then y<=I(0);
elsif S=001 then y<=I(1);
elsif S=001 then y<=I(2);
elsif S=001 then y<=I(3);
elsif S=001 then y<=I(4);
elsif S=001 then y<=I(5);
elsif S=001 then y<=I(6);
else y<=I(7);
end if;
VHDL MANUAL 24 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:25

else y<=0;
end if;
end process;
end mux8_1;

Output

3.d)4-BIT BINARY TO GRAY COUNTER CONVERTER

Black Box

clk 4 bit
en Binary to q(3 downto 0)
rst gray

Truth table
VHDL MANUAL 25 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:26

Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0
1 X 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0

VHDL MANUAL 26 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:27

VHDL CODE
entity bintogray is
Port ( rst,clk : in std_logic;
g : inout std_logic_vector(3 downto 0));
end bintogray;

architecture Behavioral of bintogray is


signal b: std_logic_vector( 3 downto 0);
begin
process(clk,rst)
begin
if rst='1' then b<="0000";
elsif rising_edge(clk) then
b<= b+1;
end if;
end process;
g(3)<= b(3);
g(2)<= b(3) xor b(2);
g(1)<= b(2) xor b(1);
g(0)<= b(1) xor b(0);
end Behavioral;

Binary to gray Output

PACE: Start of Constraints generated by PACE

VHDL MANUAL 27 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:28

#PACE: Start of PACE I/O Pin Assignments


NET "b<0>" LOC = "p84";
NET "b<1>" LOC = "p85";
NET "b<2>" LOC = "p86";
NET "b<3>" LOC = "p87";
NET "g<0>" LOC = "p112";
NET "g<1>" LOC = "p114";
NET "g<2>" LOC = "p113";
NET "g<3>" LOC = "p115";

3.e)MULTIPLEXER(4 TO 1)

Black Box
a

b 4:1 Z
c Mux
d
sel (1 to 0)

Truth Table
Sel1 Sel0 Z
0 0 a
0 1 b
1 0 c
1 1 d

VHDL CODE
entity mux1 is
Port ( en,I : in std_logic;
sel:in std_logic_vector(1downto 0);
y : out std_logic);

end mux1;
architecture dataflow of mux1 is
begin
z<= I0 when sel= "00" else
VHDL MANUAL 28 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:29

I1 when sel= "01" else


I2 when sel= "10" else
I3;

end dataflow;

( 4:1)Multiplexer Output

3.f) DE-MULTIPLEXER ( 1 TO 4)

Black Box

a
en 1:4 Y(3 downto 0)
Demux
sel(1 downto 1)

Truth table
a en Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 0

VHDL MANUAL 29 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:30

0 1 X X 0 0 0 0

VHDL CODE
entity demux is
Port ( I,en : in std_logic;
sel: in std_logic_vector(1 downto 0);
y:outstd_logic_vector(3downto0));
end demux;
architecture dataflow of demux is
signal x: std_logic_vector( 1 downto 0);
begin
x<= en & a;
y <="0001" when sel="00" and x="01" else
"0010" when sel="01" and x="01" else
"0100" when sel="10" and x="01" else
"1000" when sel="11" and x="01" else
"0000";
end dataflow;

output

NET "a" LOC = "p84";


NET "en" LOC = "p85";
NET "sel<0>" LOC = "p86";
NET "sel<1>" LOC = "p87";
NET "y<0>" LOC = "p112";
NET "y<1>" LOC = "p114";
NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

VHDL MANUAL 30 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:31

Outp

3.g)1-BIT COMPARATOR (STRUCTURAL)

Black Box

a L
1bit E
b Comparat
or G

Truth table

a b L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

VHDL MANUAL 31 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:32

VHDL CODE
entity b_comp1 is
port( a, b: in std_logic;
L,E,G: out std_logic);
end;

architecture structural of b_comp1 is


component not_2 is
port( a: in std_logic;
b: out std_logic);
end component;

component and_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;

component xnor_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;
signal s1,s2: std_logic;
begin
X1: not_2 port map (a, s1);
X2: not_2 port map (a, s2);
X3: and_2 port map (s1, b, L);
X4: and_2 port map (s2, a, G);
X5: xnor_2 port map (a, b, E);
end structural;

VHDL MANUAL 32 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:33

output
NET "a" LOC = "p74" ;
NET "b" LOC = "p75" ;
NET "E" LOC = "p86" ;

NET "G" LOC = "p85" ;


NET "L" LOC = "p84" ;

1-BIT COMPARATOR(DATA FLOW)

VHDL CODE
entity bcomp is
port( a, b: in std_logic;
c, d, e: out std_logic);
end bcomp;

architecture dataflow of bcomp is


begin
c<= (not a) and b;
d<= a xnor b;
e<= a and (not b);
end dataflow;

3.h)4-BIT COMPARATOR

Black Box

a(3 to 0) x

4bit y
Comparato
b(3 to 0) r z

VHDL MANUAL 33 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:34

VHDL CODE
entity compart4bit is
Port ( a,b : in std_logic_vector(3 downto 0);
aeqb,agtb,altb: out std_logic);

end compart4bit;

architecture Behavioral of
compart4bit is
begin
process (a,b)
begin
if a > b then aeqb<='1';agtb<=0;altb<=0;
elsif a < b then agtb<='1';aeqb<=0;altb<=0;
else altb<='1'; aeqb<=0; agtb<=0;
end if ;
end process;
end Behavioral;

output
Greater than Equal to Less than

RESULT: Combinational designs have been realized and simulated using HDL codes.

VHDL MANUAL 34 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:35

EXPERIMENT NO.4
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.

COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply.

DATA FLOW Black box

a
FULL Sum
b ADDER

Cout
c

Truth table

INPUTS OUTPUTS
a b cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VHDL MANUAL 35 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:36

VHDL CODE
entity fulladder is
Port ( a,b,c : in std_logic;
s,cout : out std_logic);
end fulladr;

architecture data of fulladr is


begin
sum<=a xor b xor cin;
cout<= ( a and b) or ( b and cin) or ( cin and
a);
end data;

BEHAVIORAL STYLE

VHDL CODE
entity fulladder beh is
Port ( a,b,c : in std_logic;
sum,carry : out std_logic);
end fulladrbeh;

architecture Behavioral of fulladrbeh is


begin
process( a,b,c)
begin

if(a='0' and b='0' and c='0') then sum<='0';


carry<='0';
elsif(a='0' and b='0' and c='1') then sum<='1';
carry<='0';
elsif(a='0' and b='1' and c='0') then sum<='1';
carry<='0';
elsif(a='0' and b='1' and c='1') then sum<='0';
carry<='1';
elsif(a='1' and b='0' and c='0') then sum<='1';
carry<='0';
VHDL MANUAL 36 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:37

elsif(a='1' and b='0' and c='1') then sum<='0';


carry<='1';
elsif(a='1' and b='1' and c='0') then sum<='0';
carry<='1';
else
sum<='1'; carry<='1';
end if;
end process;
end Behavioral;

STRUCTURAL STYLE

VHDL CODE
entity fullstru is
Port ( a,b,cin : in std_logic;
sum,carry : out std_logic);
end fullstru;

architecture structural of fullstru is

signal c1,c2,c3:std_logic;
component xor_3
port(x,y,z:in std_logic;
VHDL MANUAL 37 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:38

u:out std_logic);
end component;

component and_2
port(l,m:in std_logic;
n:out std_logic);
end component;

component or_3
port(p,q,r:in std_logic;
s:out std_logic);
end component;

begin
X1: xor_3 port map ( a, b, cin,sum);
A1: and_2 port map (a, b, c1);
A2: and_2 port map (b,cin,c2);
A3: and_2 port map (a,cin,c3);
O1: or_3 port map (c1,c2,c3,carry);

end structural;

Supporting Component Gates for Stuctural Full Adder

VHDL MANUAL 38 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:39

//and gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and2 is
Port ( l,m : in std_logic;
n : out std_logic);
end and2;
architecture dataf of and2 is
begin
n<=l and m;
end dataf;

//or gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or3 is
Port ( p,q,r : in std_logic;
s : out std_logic);
end or3;
architecture dat of or3 is
begin
s<= p or q or r;
end dat;

//xor gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xor3 is
Port ( x,y,z : in std_logic;
u : out std_logic);
end xor3;

architecture dat of xor3 is


begin
u<=x xor y xor z;
end dat;

VHDL MANUAL 39 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:40

Full adder data flow i/o pins

NET "a" LOC = "P74";


NET "b" LOC = "P75";
NET "cin" LOC = "P76";
NET "cout" LOC = "P84";
NET "sum" LOC = "P85";

Sum output carryoutput


RESULT: Three modeling styles of full adder have been realized and simulated using HDL.
codes.

VHDL MANUAL 40 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:41

EXPERIMENT NO. 5

AIM: Write a model for 32 bit ALU using the schematic diagram shown below.

COMPONENTS REQUIRED:FPGA/CPLD board, FRCs, jumper and power supply.

OPCODE ALU OPERATION


1 A+B
2 A-B
3 A Complement
4 A*B
5 A and B
6 A or B
7 A nand B
8 A xor B
9 Right shift
10 Left Shift
11 Parallel load

Black box

A1(3 to 0)

B1(3 to 0)
ALU Zout (7 downto 0)

opcode (2 to 0)

Truth table
Operation Opcode A B Zout
A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
VHDL MANUAL 41 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:42

A1*B1 101 1111 1111 11100001


A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

VHDL CODE
entity alunew is
Port( a1,b1:in std_logic_vector(3 downto 0);
opcode : in std_logic_vector(2 downto 0);
zout : out std_logic_vector(7 downto 0));
end alunew;

architecture Behavioral of alunew is


signal a: std_logic_vector( 7 downto 0);
signal b: std_logic_vector( 7 downto 0);
begin

a<= "0000" & a1;


b<= "0000" & b1;

zout<= a+b when opcode ="000" else


a-b when opcode ="001" else
a or b when opcode ="010" else
a and b when opcode ="011" else
not a when opcode ="100" else
a1 * b1 when opcode ="101" else
a nand b when opcode ="110" else
a xor b;

end Behavioral;

VHDL MANUAL 42 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:43

RESULT: 32 bit ALU operations have been realized and simulated using HDL codes.

EXPERIMENT NO.6

AIM: Develop the HDL code for the following flipflop: T, D, SR, JK.

COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.

T FLIPFLOP
Black Box

t
clk q
T ff
rst qb

VHDL CODE
entity tff is
Port ( t,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end tff;

VHDL MANUAL 43 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:44

architecture Behavioral of tff is


signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp:std_logic:='0';
begin
if rising_edge(clk) then
if (t='1') then
temp:=not temp;
else
temp:=temp;
end if;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;

Truth table
Rst T Clk q
1 0 1 q
1 1 1 qb
1 X No +ve edge Previous state
0 X X 0

Rising edge
Output
D FLIPFLOP
Black Box
VHDL MANUAL 44 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:45

d
q
D FF
clk qb

VHDL CODE
entity dff is
Port ( d,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process (clk)
variable temp: std_logic;
begin
if rising_edge(clk) then
temp:=d;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;

Truth table
clk d q qb
X 1 1 0
1 1 1 0
1 0 0 1

VHDL MANUAL 45 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:46

Output at rising edge

NET "clk" LOC = "P18";


NET "d" LOC = "P74";
NET "q" LOC = "P84";
NET "qb" LOC = "P85";

SR FLIPFLOP

Black Box

clk

s q
r SR FF
rst qb
pr

Truth table
rst pr Clk s r q qb
1 X X X X 0 1
0 1 X X X 1 0
0 0 1 0 0 Qb Qbprevious
0 0 1 0 1 0 1
0 0 1 1 0 1 0
0 0 1 1 1 1 1

VHDL MANUAL 46 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:47

VHDL CODE
entity srff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end srff;

architecture Behavioral of srff is


signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;

process(clk,rst)
variable sr:std_logic_vector(1 downto 0);
variable temp1,temp2:std_logic:='0';
begin
sr:=s&r;
if (rst ='0')then
if rising_edge(clk) then
case sr is
when "01"=> temp1:='0'; temp2:='1';

when "10"=> temp1:='1'; temp2:='0';


when "11"=> temp1:='1'; temp2:='1';
when others=> null;
end case;
end if;
else temp1:='0'; temp2:='1';
end if;
q<=temp1;qb<=temp2;
end process;
end Behavioral;

VHDL MANUAL 47 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:48

S R
output

JK FLIPFLOP

Black Box

j
k q
JK FF
clk qb

rst

VHDL MANUAL 48 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:49

VHDL CODE
entity jkff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jkff;
architecture Behavioral of jkff is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clkd)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clk,rst)
variable jk:std_logic_vector(1 downto 0);
variable temp:std_logic:='0';
begin
jk:=j&k;
if (rst ='0')then
if rising_edge(clk) then
case jk is
when "01"=> temp:='0';

when "10"=> temp:='1';


when "11"=> temp:=not temp;
when others=> null;
end case;
end if;
else temp:='0';
end if;
q<=temp;
qb<=not temp;
end process;

end Behavioral;

VHDL MANUAL 49 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:50

Truth table
Rst Clk J K Q Qb
1 1 0 0 Previous state
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Qb Q
1 No+ve egde - - Previous state
0 - - - 0 1

Output(when input 00 and rising edge)

NET "clk" LOC = "p18";


NET "j" LOC = "p84";
NET "k" LOC = "p85";
NET "rst" LOC = "p86";
NET "q" LOC = "p112";
NET "qb" LOC = "p114";

RESULT: Flip-flop operations have been realized and simulated using HDL codes

VHDL MANUAL 50 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:51

EXPERIMENT NO.7

AIM: Design 4 bit Binary, BCD counter ( Synchronous reset and Asynchronous reset and
any sequence counters.

COMPONENTS REQUIRED:FPGA board, FRCs, jumper and power supply.

a)BCD COUNTER

Black Box

clk
q(3 downto 0)
Bcd
rst counter

Truth table
Rst Clk Q
1 X 0000
0 1 0001
0 1 0010
0 1 0011
0 1 0100
0 1 0101
0 1 0110
0 1 0111
0 1 1000
0 1 1001

VHDL MANUAL 51 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:52

VHDL CODE
entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3
downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
VHDL MANUAL 52 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:53

if(dir='1' and temp="1010") then


temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;

end Behavioral;

b)GRAY COUNTER

Black Box

clk 4 bit
en Binary to q(3 downto 0)
rst gray

VHDL MANUAL 53 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:54

VHDL CODE
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2
downto 0));
end gray;
architecture Behavioral of gray is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
end process;
end Behavioral;

VHDL MANUAL 54 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:55

Truth table
Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0
1 X 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0

BINARY COUNTER(UP/DOWN)

Black Box

clk

Binary qout(3 dt 0)
rst counter

Truth table
Clk Rst Qout
X 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
VHDL MANUAL 55 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:56

1 0 0111
1 0 1000
1 0 1001
1 0 1010
1 0 1011
1 0 1100
1 0 1101
1 0 1110
1 0 1111

VHDL CODE
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3
downto 0));
end bin_as;

architecture Behavioral of bin_as is


signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;

process(clkd)
variable temp:std_logic_vector(3 downto
0):="0010";
begin

if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
VHDL MANUAL 56 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:57

end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;

end Behavioral;

Output 0000 Output 1111

RESULT: Asynchronous and Synchronous counters have been realized and simulated using
HDL codes.

VHDL MANUAL 57 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:58

INTERFACING PROGRAMS
1.WRITE A HDL CODE TO CONTROL THE SPEED, DIRECTION
OF DC & STEPPER MOTOR

DC MOTOR
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dcmotr is
Port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;

architecture Behavioral of dcmotr is


signal countr: std_logic_vector(7 downto 0);
signal div_reg: std_logic_vector(16 downto 0);
signal ddclk,tick: std_logic;
signal duty_cycle:integer range 0 to 255;

begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
VHDL MANUAL 58 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:59

when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
process(ddclk, rst)
begin
if rst='0'then countr<=(others=>'0');
pwm<="01";
elsif(ddclk'event and ddclk='1') then
countr<= countr+1;
if countr>=duty_cycle then
pwm(1)<='0';
else pwm(1)<='1';
end if;
end if;
end process;
rly<='1' when dir='1' else '0';

end Behavioral;

2. DC MOTOR
NET "CLK" LOC="p18";
NET "RESET" LOC="p74";
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141";
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";

VHDL MANUAL 59 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:60

PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor
connector of VTU card 2
2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4) Connect the down loading cable and power supply to FPGA board.
5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6) Make the reset switch on.
7) Press the Hex keys and analyze speed changes for dc motor.

RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.

STEPPER MOTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;

architecture Behavioral of steppermt is


signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15
signal shift_reg:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div+'1';
end if;
end process;
process(rst,clk_div(15)) -- speed is maximum at 15
begin
VHDL MANUAL 60 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:61

if rst='0' then shift_reg<="0001";


elsif rising_edge (clk_div(15)) then
if dir='1' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout<= shift_reg;

end Behavioral;

NET "clk" LOC = "p18"; NET "dir" LOC = "p85";


NET "rst" LOC = "p84";
NET "dout<0>" LOC = "p7"; NET "dout<1>" LOC = "p5";
NET "dout<2>" LOC = "p3"; NET "dout<3>" LOC = "p141";

PROCEDURE:1) Make connection between FRC 9 and FPGA board to the stepper motor
connector of
VTU card 1
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Visualize the speed variation of stepper motor by changing counter value in the
program.

RESULT: The stepper motor runs with varying speed by changing the counter value

VHDL MANUAL 61 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:62

2.WRITE A HDL CODE TO CONTROL EXTERNAL LIGHTS USING


RELAYS
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity externallc is
Port ( cnt : in std_logic;
light : out std_logic);
end externallc;

architecture Behavioral of externallc is

begin
light<=cnt;

end Behavioral;

NET "cnt" LOC = "p74";


NET "light" LOC = "p7";

PROCEDURE:
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
3.Connect the Downloading cable and power supply to fpga board.
1. Then open the xilinx impact software select the slave serial mode and select
respective bit file and click program
2. Make the reset switch on and listen to the tick sound.

RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.

VHDL MANUAL 62 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:63

3.WRITE VHDL CODE TO GENERATE DIFFERENT


WAVEFORMS(SAWTOOTH, SINE WAVE, SQUARE, TRIANGLE,
RAMP ETC) USING DAC CHANGE THE FREQUENCY AND
AMPLITUDE.

SAWTOOTH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sawtooth is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end sawtooth;

architecture Behavioral of sawtooth is


signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;

VHDL MANUAL 63 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:64

SQUARE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;

architecture Behavioral of squarewg is


signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector(0 to 7);
signal en: std_logic;

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;

process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
VHDL MANUAL 64 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:65

end if;
end process;
end Behavioral;

TRIANGLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;

architecture Behavioral of triangwg is


signal temp: std_logic_vector( 3 downto 0);
signal cnt: std_logic_vector(0 to 8);
signal en:std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+1;
end if;
end process;
process( temp(3))
begin
if rst='1' then cnt<="000000000";
elsif rising_edge(temp(3)) then
cnt<=cnt+1;
if cnt(0)='1' then
dac<=cnt(1 to 8);
else
dac<= not(cnt( 1 to 8));
end if;
end if;
end process;

end Behavioral;
VHDL MANUAL 65 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:66

RAMP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;

architecture Behavioral of rampwg is


signal temp:std_logic_vector(3 downto 0);
signal cnt:std_logic_vector( 0 to 7);

begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+15;
end if;
end process;
dac<=cnt;

end Behavioral;

SINE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

VHDL MANUAL 66 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:67

entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic; 4.DAC
begin NET "CLK" LOC="p18";
process(clk) is NET "dac_out<0>" LOC="p27";
begin NET "dac_out<1>" LOC="p26";
if rising_edge (clk) then NET "dac_out<2>" LOC="p22";
temp<= temp+'1'; NET "dac_out<3>" LOC="p23";
end if; NET "dac_out<4>" LOC="p21";
end process; NET "dac_out<5>" LOC="p19";
process(temp(3)) is NET "dac_out<6>" LOC="p20";
begin NET "dac_out<7>" LOC="p4";
if rst='1' then counter<="00000000";
NET "rst" LOC="p74";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;

end Behavioral;
PROCEDURE:
1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU
card 2.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
4) Make the reset switch on.

RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.

VHDL MANUAL 67 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:68

4. WRITE A HDL CODE TO DISPLAY MESSAGES ON THE GIVEN


SEVEN SEGMENT DISPLAY
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 5. KEY BOARD TO 7 SEGMENT DISPLAY
NET "CLK" LOC="p18";
entity sevkeybrd is NET "disp_cnt<0>" LOC="p30";
Port ( read : in std_logic_vector(3 downto 0); NET "disp_cnt<1>" LOC="p29";
clk : in std_logic; NET "disp_cnt<2>" LOC="p31";
scan : inout std_logic_vector(3 downto 0); NET "disp_cnt<3>" LOC="p38";
disp_cnt : out std_logic_vector(3 downto 0); NET "disp<0>" LOC="p26";
disp1 : out std_logic_vector(6 downto 0)); NET "disp<1>" LOC="p22";
end sevkeybrd;
NET "disp<2>" LOC="p23";
NET "disp<3>" LOC="p21";
architecture Behavioral of sevkeybrd is
signal cnt_2bit:std_logic_vector(1 downto 0); NET "disp<4>" LOC="p19";
begin NET "disp<5>" LOC="p20";
process(clk) NET "disp<6>" LOC="p4";
begin NET "read_l_in<0>" LOC="122";
if clk='1' and clk'event then NET "read_l_in<1>" LOC="124";
cnt_2bit<= cnt_2bit+1; NET "read_l_in<2>" LOC="129";
end if; NET "read_l_in<3>" LOC="126";
end process; NET "scan_l<0>" LOC="132";
process(cnt_2bit) NET "scan_l<1>" LOC="136";
begin NET "scan_l<2>" LOC="134";
case cnt_2bit is
NET "scan_l<3>" LOC="139";
when "00" => scan<= "0001";
when "01"=> scan<="0010";
when "10"=>scan<="0100";
when "11"=>scan<="1000";
when others=> null;
end case;
end process;
disp_cnt<="1110";
process(scan,read)
VHDL MANUAL 68 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:69

begin
case scan is
when "0001"=>case read is
when "0001"=>disp1<="1111110";
when "0010"=>disp1<="0110011";
when "0100"=>disp1<="1111111";
when "1000"=>disp1<="1001110";
when others =>disp1<="0000000";
end case;

when "0010"=> case read is


when "0001"=>disp1<="0110000";
when "0010"=>disp1<="1011011";
when "0100"=>disp1<="1111011";
when "1000"=>disp1<="0111101";
when others=>disp1<="0000000";
end case;

when "0100"=> case read is


when "0001"=>disp1<="1101101";
when "0010"=>disp1<="1011111";
when "0100"=>disp1<="1110111";
when "1000"=>disp1<="1001111";
when others=>disp1<="0000000";
end case;

when "1000"=> case read is


when "0001"=>disp1<="1111001";
when "0010"=>disp1<="1110000";
when "0100"=>disp1<="0011111";
when "1000"=>disp1<="1000111";
when others=>disp1<="0000000";
end case;
when others=> null;
end case;
end process;
end Behavioral;

PROCEDURE:
1) Make connection between FRC 5 and FPGA board to the seven segment connector of

VHDL MANUAL 69 ECE Dept, JMIT


Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:70

VTU card 1.
2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Change the pressing of Hex Keys to watch the display on LCDs ranging from 0000 to
FFFF.
RESULT:The values from 0 to F were displayed on all 4 LCDs with the respective Hex
Key being pressed.

I/O Pin Assignments

FOR DC & Stepper


Xilinx FPGA MOTOR
FRC FRC1 FRC2 FRC3 FRC4 FRC6 FRC7 Xilinx FPGA
1 74 84 112 122 40 58 FRC FRC9
2 75 85 114 124 41 60 1 7
3 76 86 113 129 42 63 2 5
4 78 87 115 126 48 64 3 3
5 77 93 117 132 50 65 4 141
6 80 94 118 136 51 66 9 5V
7 79 95 121 134 56 67 10 GND
8 83 100 123 139 57 28
9 VCC VCC VCC VCC VCC VCC
10 GND GND GND GND GND GND
FOR LCD & DAC FOR ADC
FRC FRC5 FRC8 FRC10
1 4 96 62
2 20 99 59
3 19 101 49
4 21 102 47
5 23 103 46
6 22 116 4
7 26 120 43
8 27 131 13
9 30 133 12
10 29 137 11
VHDL MANUAL 70 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:71

11 31 138 10
12 38 140 6
13 5V 5V 5V
14 -5v -5v -5v
15 3.3 3.3 3.3
16 GND GND GND

Constrints file
1. External Light Controller
NET "cntrl" LOC="p74"; => FRC1
NET "light" LOC="p7"; => FRC9

2. DC MOTOR
NET "CLK" LOC="p18";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141"; FRC9
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
FRC7
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
3. STEPPER MOTOR
NET "CLK" LOC="p18";
NET "dout<0>" LOC="p7";
NET "dout<1>" LOC="p5";
FRC9
NET "dout<2>" LOC="p3";
NET "dout<3>" LOC="p141";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
4.DAC
NET "CLK" LOC="p18";
NET "dac_out<0>" LOC="p27"; FRC5
NET "dac_out<1>" LOC="p26";
VHDL MANUAL 71 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:72

NET "dac_out<2>" LOC="p22";


NET "dac_out<3>" LOC="p23";
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74"; FRC1

5. KEY BOARD TO 7 SEGMENT DISPLAY


NET "CLK" LOC="p18";
NET "disp_cnt<0>" LOC="p30";
NET "disp_cnt<1>" LOC="p29";
NET "disp_cnt<2>" LOC="p31";
NET "disp_cnt<3>" LOC="p38";
NET "disp<0>" LOC="p26";
NET "disp<1>" LOC="p22"; FRC5
NET "disp<2>" LOC="p23";
NET "disp<3>" LOC="p21";
NET "disp<4>" LOC="p19";
NET "disp<5>" LOC="p20";
NET "disp<6>" LOC="p4";
NET "read_l_in<0>" LOC="122";
NET "read_l_in<1>" LOC="124";
NET "read_l_in<2>" LOC="129";
NET "read_l_in<3>" LOC="126";
FRC4
NET "scan_l<0>" LOC="132";
NET "scan_l<1>" LOC="136";
NET "scan_l<2>" LOC="134";
NET "scan_l<3>" LOC="139";

Procedure to download the program on to FPGA


Create new source
Implementation constraints file
User constraints
Create Timing constraints: Give the input and output ports from the port number
look up table(pin assignment) and then save.
VHDL MANUAL 72 ECE Dept, JMIT
Doc:
Seth Jai Parkash Mukand lal Institute of JMIT/ECE/ECE-316E
Engineering & Technology, Radaur

VHDL LAB Page:73

Edit constraints to check the specified ports

Click on the source file

Implement design

Configure device (impact)after switching on power supply

Select the slave serial mode


Select the source file
Right click on xilinx and select program

Connect input port to dip switch and output port to leds.


Vary the inputs and view the corresponding outputs.

VHDL MANUAL 73 ECE Dept, JMIT

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