The MOS Transistor (Chapter-3) The NMOS Transistor Cross Section

n areas have been doped with donor ions

Polysilicon (arsenic) of concentration ND - electrons
are the majority carriers
Aluminum Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L

p substrate
p+ stopper

Bulk (Body)

p areas have been doped with acceptor

ions (boron) of concentration NA - holes
are the majority carriers

Switch Model of NMOS Transistor Switch Model of PMOS Transistor

| VGS |
Gate
| VGS | Gate

Source Drain Source Drain

(of carriers) (of carriers) (of carriers) (of carriers)

Open (off) (Gate = 0) Closed (on) (Gate = 1) Open (off) (Gate = 1) Closed (on) (Gate = 0)
Ron Ron

| VGS | < | VT | | VGS | > | VT | | VGS | > | VDD | VT | | | VGS | < | VDD |VT| |
 Threshold Voltage Concept MOS gate Structure

First electrode - Gate :
G
VGS Consists of low-resistivity
+ material such as highly-doped
S D
polycrystalline silicon,
- aluminum or tungsten

n+ n+

Second electrode -
Substrate or Body: n- or p-
depletion type semiconductor
n channel p substrate region

Dielectric - Silicon dioxide:

B stable high-quality electrical
insulator between gate and
substrate.
The value of VGS where strong inversion occurs is called
the threshold voltage, VT

Gate and Substrate Conditions for Different Biases

Accumulation Depletion
VG << VTN
VG < VTN

Inversion
VG > VTN
The Threshold Voltage The Body Effect

0.9
VT = VT0 + (|-2F + VSB| - |-2F|) 0.85  VSB is the substrate
0.8 bias voltage (normally
where positive for n-channel
0.75
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the 0.7 devices with the body
manufacturing process tied to ground)
0.65
 Difference in work-function between gate and substrate
material, oxide thickness, Fermi voltage, charge of impurities 0.6
trapped at the surface, dosage of implanted ions, etc. 0.55  A negative bias

0.5 causes VT to increase

VSB is the substrate-bias voltage
0.45 from 0.45V to 0.85V
F = -Tln(NA/ni) is the Fermi potential (T = kT/q = 26mV at 300K is
0.4
the thermal voltage; NA is the acceptor ion concentration; ni
1.5x1010 cm-3 at 300K is the intrinsic carrier concentration in pure -2.5 -2 -1.5 -1 -0.5 0
silicon) VBS (V)
= (2qsiNA)/Cox is the body-effect coefficient (impact of changes in
VSB) (si=1.053x10-10F/m is the permittivity of silicon; Cox = ox/tox is
the gate oxide capacitance with ox=3.5x10-11F/m)
 Transistor in Linear Mode MOSFET Current Voltage Characteristics (Linear region)

Assuming VGS > VT

VGS
VDS
The applied gate voltage
S G
needed to create an
D ID inversion charge layer in the
semiconductor substrate is
n+ - V(x) + n+ called threshold voltage (VTN
or Vt).

x

At Vt the charge density is
equal to the concentration of
B majority carriers in the
semiconductors substrate.

The current is a linear function of both VGS and VDS

NMOS Transistor: Triode Region Characteristics Concept of Asymmetric Channel

It is to be noted that the VDS measured relative to the source increases from 0
to VDS as we travel along the channel from source to drain. This is because the
voltage between the gate end points along the channel decreases from VGS at the
source end to VGS-VDS at the drain end.

When VDS is increased to the value that reduces the voltage between the gate and
channel at the drain end to Vt that is ,

VGS-VDS=Vt or VDS= VGS-Vt or VDS(sat) VGS-Vt
 MOSFET Current Voltage Characteristics (Saturation Region) Transistor in Saturation Mode

Assuming VGS > VT

When VDS is increased to the value
that reduces the voltage between
the gate and channel at the drain
end to Vt that is , VGS VDS > VGS - VT
VDS
VGS-VDS=Vt or S G
VDS= VGS-Vt D ID
At this point the channel depth at the
drain end decreases to almost zero, n+ n+
and the channel is said to be pinched
off. Increasing VDS beyond this value
has no effect on the channel shape.
The MOSFET is said to have entered
the saturation region, the drain - V -V +
current is essentially independent of GS T Pinch-off
VDS for constant VGS.
VDSsat= VGS-Vt
B
Obviously, for every value of VGSVt,
there is a corresponding value of VDSsat The current remains constant (saturates).

NMOS Transistor: Saturation Region

'
K W
iD = n vGS VTN 2 for vDS vGS VTN
2 L

vDSAT = vGS VTN is called the saturation or pinch-off voltage

 MOSFET Current Voltage Relationships
MOSFET Current Voltage Relationships (Non saturation Region) (Saturation Mode)
The region for which VDS< VDS(sat) is known as the nonsaturation

In saturation mode VDS VGS-Vt .


region. The ideal current voltage characteristics in this region are
describe by the equation

The expression for saturation mode can

iD= Kn[(VGS-VTN)VDS-VDS2/2]
be obtained by substituting VDS = VGS-Vt
resulting in
Where the parameter Kn is called the conduction parameter or gain
factor for the n-channel device and is given by
iD (Sat)= Kn/2(VGS-VTN)2
Kn= nCoxW/L
This expression indicates that the
Where Cox is the oxide capacitance per unit area. The capacitance is saturation drain current has no
given by
dependence on VDS.
Cox= ox/tox

Where tox is the oxide thickness and ox is the oxide permittivity. The
parameter n is the mobility of the electron in the inversion layer.

Process Tranconductance parameter Channel-Length Modulation

It is to be noted that in the above
As vDS increases above vDSAT, the

length of the depleted channel
expressions the parameter nCox is a constant beyond pinch-off point, L,
increases and actual L
determined by the processing technology decreases.
used to fabricate the MOS technology. It is
known as the process transconductance

iD increases slightly with vDS
parameter, and is denoted by instead of being constant.

K' n= nCox

We can rewrite the conduction parameter in
the form,
Transistor design variable.
Kn= K'nW/L '
K W 2
= channel length modulation iD = n v VTN 1+ v DS
GS
parameter 2 L
Current Determinates p-Channel MOSFET

For a fixed VDS and VGS (> VT), IDS is a function
In p-channel enhancement
of device. A negative gate-to-
source voltage must be
 the distance between the source and drain L applied to create the
inversion layer, or channel
 the channel width W region, of holes that,
connect the source and
 the threshold voltage VT drain regions.
 the thickness of the SiO2 tox
The threshold voltage VTP
for p-channel enhancement
 the dielectric of the gate insulator (SiO2) ox load device is always negative
and positive for depletion-
 the carrier mobility mode PMOS.
- for n: n = 500 cm2/ V-sec
Cross-section of p-channel enhancement mode MOSFET

- for p: p = 180 cm2/ V-sec

The operation of the p-channel is same as the n-channel device , except that the
iD= Kn[(VGS-VTN)VDS-VDS2/2] hole is the charge carrier, rather than the electron, and the conventional current
direction and voltage polarities are reversed.

Summary of the MOSFET

Current-Voltage relationship

Table 5.1
 Example Secondary effects

Given that for n-channel enhancement mode MOSFET, VTN=1.2V and VGS=2V
Short-channel effects:
Determine the region of the operation when:
i) VDS=0.4V  Short channel device has channel length
ii) VDS= 1V comparable to depth of drain and source
iii) VDS=5V junctions and depletion width
Sol: We know at the saturation,
VDS(sat)=VGS-VTN= 2-1.2=0.8V  Causes threshold voltage and I/V curve
Case1: when VDS=0.4V variations
VDS < VDS(sat) transistor is in nonsaturation region
CaseII: when VDS=1V
Narrow-channel effects:
VDS > VDS(sat) transistor is in saturation mode
CaseIII: when VDS=5V  Narrow channel device has small channel
VDS > VDS (sat) transistor is in saturation mode width

Subthreshold conduction (leakage current)

Short-channel effects Carrier velocity saturation

0 Vgs

Short-channel device: channel length is Vds

comparable to depth of drain and source N+ N+

source L drain
junctions and depletion width
P
 In general, visible when L ~ 1m and
below

Electric field Ey exists along channel
 As channel length is reduced, electric field increases (if voltage

Short-channel effects: is constant)

 Carrier velocity saturation
Electron drift velocity vd is proportional to electric field

 only for small field values
 Mobility degradation  for large electric field, velocity saturates

 Threshold voltage variation

 Effects of High fields Carrier velocity saturation

Vertical field
The vertical field occurs in the y-direction from the gate to
the channel (EY=VDD/tox
1980 1995 2001
EY=5V/1000Ao =50 x 104V/cm EY=3.3.V/75Ao=4.4 x 106V/cm Ey=1.2V/22AO=5.5 x 106
V/cm

Horizontal field
The horizontal field occurs in the x-direction from the drain
to the source (EY=VDS/L
1980 1995 2001
Ex=5V/5m =104V/cm Ex=3.3.V/0.35m=9.4 x 104V/cm Ex=1.2V/0.1m=1.2 x 105 V/cm

Carrier velocity saturation Velocity Saturation Effects

Effect of velocity saturation:
 Current saturates before saturation region
10 For short channel devices
 VDSAT = voltage at which saturation occurs and large enough VGS VT
 Drain current is reduced:
 VDSAT < VGS VT so
the device enters
saturation before VDS
I D ( sat ) = Wvd ( sat )Cox (VGS VT 12 VDSAT ) reaches VGS VT and
0 operates more often in
(no longer quadratic function of VGS) saturation

 Saturation region is extended:  IDSAT has a linear dependence wrt VGS so a reduced
VDSAT < VGS-VT amount of current is delivered for a given control
voltage
 Short Channel I-V Plot (NMOS) MOS ID-VGS Characteristics
X 10-4
2.5 X 10-4  Linear (short-channel)
Early Velocity 6
Saturation
VGS = 2.5V versus quadratic (long-
2 5 channel) dependence of
VGS = 2.0V 4 ID on VGS in saturation
1.5
3
 Velocity-saturation
Linear Saturation
1 VGS = 1.5V 2 causes the short-
1 channel device to
0.5 VGS = 1.0V saturate at substantially
0
smaller values of VDS
0 0 0.5 1 1.5 2 2.5 resulting in a substantial
0 0.5 1 1.5 2 2.5 VGS (V) drop in current drive
VDS (V)
NMOS transistor, 0.25m, Ld = 0.25m, W/L = 1.5, VDD = 2.5V, VT = 0.4V (for VDS = 2.5V, W/L = 1.5)

Short-channel and long channel comparison Mobility degradation

Long-channel Short-channel
MOS I/V equations depend on surface mobility
n (or p)

In short-channel devices, n and p are not
constant
 As vertical electric field EY increases, surface
mobility decreases

Both devices have same effective W/L ratio I/V curves should be  0 = low-field mobility, is empirical constant
similar
 As VGS increases, surface mobility decreases

Short-channel device has ~ 40% less current at high VDS 0
=

Note linear dependence on VGS in short-channel device
1 + (VGS VT )
 Threshold voltage variation Threshold voltage variation
Short-channel effects cause threshold voltage

Until now, threshold voltage assumed variation:
constant
 VT changed only by substrate bias VSB

VT roll off

In threshold voltage equations, channel  As channel length L decreases, threshold
depletion region assumed to be created by voltage decreases
gate voltage only

Drain-induced barrier lowering

Depletion regions around source and drain
 As drain voltage VDS increases, threshold
neglected: valid if channel length is much
voltage decreases
larger than depletion region depths

Hot-carrier effect

In short-channel devices, depletion regions
from drain and source extend into channel  Threshold voltages drift over time

Threshold voltage variation Threshold voltage variation

Change in VT0:
 xdS, xdD: depth of depletion regions at S, D
N+ N+ Drain  xj: junction depth
source drain depletion
Source
depletion region
1 x j 2x 2x
region Gate-induced VT 0 = 2q Si N A 2 F 1 + dS 1 + 1 + dD 1
depletion region Cox 2 L xj
xj

Even with VGS=0, part of channel is already depleted

VT0 is proportional to (xj/L)

Bulk depletion charge is smaller in short-channel device VT is
smaller For short channel lengths, VT0 is large
For large channel lengths, term approaches 0
 Threshold voltage variations Drain-induced barrier lowering (DIBL)
Graphically: VT0 versus channel
Drain-induced barrier lowering (DIBL)
length L
 Drain voltage VDS causes change in threshold
VT voltage
VT0 Long-channel VT  As VDS is increased, threshold voltage decreases
Low VDS threshold

Cause: depletion region around drain
Threshold as a function of
As a function of length (for low VDS)  Depletion region depth around drain depends on
drain voltage
VDS
 As VDS is increased, drain depletion region gets
Lnom L deeper and extends further into channel
Drain-induced barrier lowering
(for low L)  For very large VDS, source and drain depletion
VT Roll-off:
regions can meet punch-through!
VT decreases rapidly with channel length

Issue: results in uncertainty in circuit design

Threshold voltage variation

Hot-carrier effect
 increased electric fields causes
increased electron velocity
 high-energy electrons can tunnel into
gate oxide
 This changes the threshold voltage
(increases VT for NMOS)
 Can lead to long-term reliability
problems
Threshold voltage variation

Hot electrons
 High-velocity electrons can also impact
the drain, dislodging holes
 Holes are swept towards negatively-
charged substrate cause substrate
current-
 Called impact ionization
 This is another factor which limits the
process scaling voltage must scale
down as length scales
Narrow-channel effects

Narrow-channel device:
 Channel width W is comparable to
maximum depletion region thickness xdm

Narrow-channel effect:
 Threshold voltage of narrow-channel
device is larger than threshold of
conventional device
Threshold voltage variations

Summary of threshold variations in short-
channel devices
 VT rolloff: threshold voltage reduces as
channel length L reduces
 DIBL: threshold voltage reduces as VDS
increases
 Hot-carrier effect: threshold voltage
drifts over time as electrons tunnel into
oxide
Narrow-channel effect

Cause of narrow-channel effect
 Edges of gate metal are over field oxide (FOX)
 This field oxide causes a small depletion region
Gate voltage must support this additional depletion region charge

Narrow-channel effect Subthreshold conduction

Change in threshold voltage:
When VGS < VT, transistor is off
 However, small drain current ID still flows

VT 0 (narrow channel) = VT 0 + VT 0  Called subthreshold leakage current

1 xdm
Model for subthreshold current:

VT 0 = 2q Si N A 2 F q
( AVGS + BVDS )
Cox W I D ( subthreshold ) = I SWe kT

 is empirical parameter: depends on shape of the fringe depletion  Increases as VGS increases (potential barrier lowered)
region
 Increases as VDS increases (DIBL)
 Change in VT0 proportional to (xdm/W)

Subthreshold Channel Conduction: Physical Origin Subthreshold conduction

Exponential relationship to VGS

Subthreshold current conduction is mainly caused by carrier diffusion, while above-

threshold is mostly carrier drift. log IDS(sub)

This transport mechanism is actually similar to BJT, and the channel current has an
exponential dependence on VGS. subthreshold slope
(mV/decade of current)

The slope of log10(ID) vs. VGS, or required VGS to reduce ID for one decade, is called the
subthreshold slope S, which is larger than 60mV for classical devices.

VT VGS
log10(ID) Subthreshold slope:
Shift in VGS required to reduce leakage by
VDS=0.1V
drift factor of 10
diffusion
Typical values: 80-120 mV/decade
VGS
Subtrhreshold current Leakage current (subthreshold)

Effect of leakage current
 Wasted power: power consumed even when
circuit is inactive
 Leakage power raises temperature of chip

 Can cause functionality problem in some

circuits: memory, dynamic logic, etc.

Reducing transistor leakage
 Long-channel devices

 Small drain voltage

 Large threshold voltage VT

Leakage current issues Future Perspectives

Leakage vs. performance trade-off:
 For high-speed, need small VT and L

 For low leakage, need high VT and large L (to

reduce DIBL and VT roll-off)

Process scaling
 VT reduces with each new generation technology
(historically)
 Leakage increases ~10X!

One solution: dual-VT process

 Low-VT transistors: use in critical paths for high
speed
 High-VT transistors: use to reduce power
25 nm FINFET MOS transistor