A New Loadless 4-Transistor SRAM Cell with a 0.

18 m CMOS Technology
Jinshen Yang Li Chen
Department of Communication Engineering Department of Electrical and Computer Engineering
Tianjin University University of Saskatchewan
Tianjin, P. R. China Saskatoon, Canada
jsyang@tju.edu.cn li.chen@usask.ca

Abstract-This paper introduces a new four transistor (4T) shown in Fig.1 (b). A pair of PMOS transfer transistors is
SRAM cell for very high density embedded SRAM used to store and retain full-swing signals in the cell without
applications. Compared to a 4T cell introduced previously, the a refresh cycle. The memory cell size is 35% smaller than a
new cells have the bitlines precharged to ground rather than 6T cell using the same design rule with CMOS 0.18 micron
Vdd. The cell is new stable operating at 1.8V. A comparative
technology [4]. This cell can remain stable at 1.8 V with its
analysis of the new 4T cell with other 4T loadless SRAM cells
and conventional 6T SRAM cells is performed. Using a 0.18- cell ratio of 1.0. However the threshold voltage difference
m CMOS technology, this cell consumes less power with less between NMOSFET and PMOSFET has to be controlled
area. from 0.2 to 0.4 V, which causes barriers to the applications
of this technique [5, 6, 7].
Keywords-SRAM Cells; 4-T; high density; low-power.
This paper proposes a loadless 4T SRAM cell which uses
I. INTRODUCTION NMOS transistors as access transistors. In addition, the
bitlines are precharged to ground (0volts) instead of Vdd
The existing SRAM cells can be divided into two groups
(1.8 volts) with a 0.18 m CMOS technology. The goal of
in terms of transistor numbers: standard six-transistor (6T)
introducing this loadless 4T cell is to achieve a smaller cell
shown in Fig. 1 (a), and four-transistor (4T) SRAM with
size than conventional 4T-cell, with the same stability and
resistive load. In a 6T SRAM cell, the transistors connected
the same compatibility with CMOS logic processes as 6T-
to the bitlines are called access transistors. The transistors
SRAM cells.
pull the cell values (Q and Q) to Vdd are called load
transistor, and the ones connected to ground are called
driver transistors. The traditional 4T-SRAM with two load-
resistors instead of two load transistors dominates the
standalone SRAM market since they have much less cell
area than 6T-SRAM cells. However, for on-chip storage in
microprocessors and other logic circuits, the 4T-SRAMs
have not been used, because they need a complex process to
form a load element [1]. In addition, the transconductance
ratios of the drive transistors to the transfer transistors
becomes large to achieve a sufficient Static-Noise-Margin
(SNM) of 200 mV for megabit scale SRAMs. The cell size
becomes larger with the cell ratio and has no more Fig. 1: Schematic for a 6-transistor SRAM cell.
advantage over 6T-SRAMs when it is as large as 6.5. This is
why the conventional 4T-SRAM disappears from the
quarter-micrometer generation [2].

The basic idea of the loadless 4T-SRAM was proposed in

1987 [3]. This was the first report of a 4T-SRAM fabricated
in a CMOS logic process, but it described mainly a
specialized circuit to hold the cell data. In this field,
concepts on layout or fabrication technology have not been
discussed to reduce the area of the 4T-SRAM cell until
another loadless 4T-SRAM cell was introduced by Noda [2, Fig. 2: Schematic of a loadless 4-transistor SRAM cell [3].
4, 7] (referred as Noda cell hereafter). Its schematic is

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 II. CELL DESIGN AND OPERATION
Figure 3 shows our new loadless 4T SRAM cell. In the
cell, two NMOS transistors are used as pass transistors to
access the cell. The bitlines are precharged to ground
instead of Vdd. Two PMOS transistors are used as drivers
for the cell.
Fig.3: The new loadless 4T cell.
A. Write/Read Operation
Firstly the write operation of the cell is described as
follows. In order to store a logic 1 to the cell, BL is
charged to Vdd and BL is charged to ground and vise verse
for storing a logic 0. Then the wordline voltage is
switched to Vdd to turn on the NMOS access transistors.
When the access transistors are turned on, the values of the
bitlines are written into Q and Q. The node that is storing
the logic 1 will not go to full Vdd because of a voltage
drop across the nMOS access transistor. After the write
operation the wordline voltage is reset to ground to turn
off the nMOS access transistors. The node with the
logic1 stored will be pulled up to full Vdd through the
PMOS driver transistors.
The read operation of the cell is different from that of
the 6T transistors. To read from the cell the bitlines are
charged to ground in stead of Vdd and the wordline voltage
is set to Vdd to turn on the nMOS access transistors. The
node with logic 1 stored will pull the voltage on the
corresponding bitline up to a high (not Vdd because of the
voltage drop across the Nmos access transistor) voltage
level. The other bitline is pulled to ground. The sense
amplifier will detect which bitline is at a high voltage and
which bitline is at ground. If the cell was storing a logic 0
the voltage level of BL will be lower than BL so the sense
amplifier will output a logic 0. If the cell was storing
logic 1 then the voltage level of BL will be higher than
BL then the sense amplifier will output a logic 1.
B. Standby Cycle
Before discussing our loadless 4T-SRAM, operations of
the previously introduced Noda cell will be reviewed to
clarify the difference between them. The Noda 4T cell in
Fig. 2 shows that when the cell is in a standby cycle the
PMOS access transistors are turned off by keeping
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wordline at Vdd. The bitlines are precharged to Vdd in the
standby cycle. In order for the cell to retain its data the
leakage currents of the PMOS access transistor must be
greater than the NMOS transistors. This is why the
threshold voltages of the PMOS transistors are controlled
lower than the NMOS to obtain the higher leakage current.
Fig. 4: Cell waveforms for WRITE/READ operation
Our loadless 4T cell uses NMOS access transistors and
PMOS driver transistors. In standby cycle (precharge stage)
the worlline which connects to the gate of the NMOS access
transistors is set to low and the access transistors are off.
Assuming that Q has been written with a logic high and Q a
logic low during the write operation, then the logic low in
Q is week (actually floating) during the standby period
compared to the logic high in Q. Eventually the voltage
level of Q will be determined by the voltage divider of the
off resistances for the PMOS and NMOS connecting to
Q. In another word, the ratio of leakage currents of the
NMOS and PMOS will determine the voltage of Q. The
gate-induced leakage current becomes more significant for
nanometer ranger transistors compared to less advanced
technologies. The leakage through the NMOS access
transistor is much greater than the leakage current through
the PMOS storage transistor. With this effect, the voltage
level of the floating Q can be kept relatively low, 0.2 V,
which is acceptable for normal operation.
III. SIMULATIONS FOR OPERATION AND STABILIT
Figure 4 shows the proposed cell operates correctly for
WRITE/READ operations. A write operation is performed
followed by a read operation. During the standby period the
cell voltage for a logic high is 1.8 V. The complement value
of the cell, the logic low is kept in 0.1 to 0.25 V.
After the functionality of the cell is proven, simulations
are performed to determine the stability of the cell during
read operation which is the most vulnerable period during
all the operations. A minimum of 200mV static noise
margin (SNM) is needed for stable operation [6, 7] for
mega-bit level SRAMs. SNM is the maximum noise voltage
that will not cause the stored value to change and is a
measurement of stability. The SNM can be measured
graphically from the butterfly graph. The butterfly graph is a
plot of the inverter characteristics of the SRAM cell. The
SRAM cell can be modeled as two inverters connected in
series with each other (as a positive feedback loop). The
positive feedback loop forces the output of one inverter to
be logic 0 and the output of the other inverter to be logic
1. The outputs of the two inverters are Q and Q. To
obtain the butterfly graph for the cell, Q versus Q and Q
versus Q are plotted on the same graph. The butterfly graph
shows the input/output characteristics of both inverters.

Figure 5 shows the butterfly curves for the proposed 4T

cell for cell ratios r from 2.5 to 4. Cell ratio r are defined as
the ratio of drvier to access (driver is the
transconductance of the storage transistors and access is
the transconductance of the access transistors). SNM are Fig. 6(b): SNM = 446 mV when cell ratio r = 3
extracted from each pair of the butterfly curves. The SNM is
graphically represented as the diagonal length of the largest
square that can fit inside the butterfly graph. The extracted
SNMs with different r from figures 5 are shown in figure 6.
The results show that the SNM increases with larger cell
ratios, which is clearly shown in Table 1. There is a tradeoff
between the cell size and its stability. When cell ratio r
equals 3, it can provide a relatively high SNM margin
(SNM = 446 mV) and keep the cell size small.

Fig. 6(c): SNM = 513 mV when r = 3.5

Figure 5: Butterfly curves for various cell ratios

Fig. 6(d): = 565 mV when cell ratio r = 4

Table 1: Extracted SNM with different cell ratio r

Cell ratio r 2 2.5 3 3.5 4

SNM (mV) 190.5 339 446 513 565
Fig. 6(a): SNM = 190.5 mV when cell ratio r = 2.0

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 IV. PERFORMANCE
Now that the proposed 4T loadless SRAM cell has been
optimized, its power and area performance can then be
evaluated. The Noda 4T cell has a SNM of 435mV and the
conventional 6T cell has a SNM of 410mV when
implemented with a 0.18m CMOS technology. With the
cell ratio r of 3, our cell has a SNM of 446 mV and its size
of the cell layout is 15% smaller than that of the standard 6T
SRAM cell. It also consumes less power than the Noda 4T
cells and conventional 6T cells, as its bitlines are precharged
to ground instead of Vdd.
One drawback of the proposed cell is that the node
storing the logic high can not retain its full swing value as it
is floating. It will become unstable against radiation
particles or noise from peripheral circuits because of less
critical charge. One solution is to control the threshold
voltage of NMOS and PMOS transistors as described in the
Noda cell. Another approach is error correcting codes,
which should effectively mitigate this problem.
The proposed cell can further evaluated with a modified
sense amplifier which accommodate the architecture of this
cell. Then the overall power performance can be further
investigated. In addition, more advanced technologies, e.g.
0.13m or 0.090m CMOS technology can be used to
implement this cell. It is predicted these technologies should
further improve the performance in terms of power, size and
stability.
V. CONCLUSION
A new loadless 4T transistor is developed with a 0.18m
CMOS technology. The cell operates with high stability
using a cell ratio of 3. The most significant feature of this
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new cell is that there is no need to modify any of the
fabrication process. It is promising for high-speed and high-
density SRAMs embedded in any logic devices, as well as
for stand-alone SRAM applications.
ACKNOWLEDGMENT
The authors would like to thank Jim Sprage and Edvin
Hjortlan for the help on the simulation and layout of the
circuits.
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