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ASICs

i will miss you always

The term 'ASIC' stands for 'application-specific integrated

circuit'.
An ASIC is basically an integrated circuit designed specifically
for a special purpose or application.
Strictly speaking, this also implies that an ASIC is built only for
one and only one customer.

ASIC'S CLASSIFICATION

ASIC's are usually classified into one of two categories:

1full-custom ASIC
2 semi-custom ASIC

1 FULL-CUSTOM ASICS
. Full-custom ASIC can not be modified to suit different
applications, and is generally produced as a single, specific
product for a particular application only.
, Full-custom design offers the highest performance and lowest
part cost (smallest die size) for a given design
2 SEMI-CUSTOM ASICS
- Semi-custom ASIC's, on the other hand, can be partly
customized to serve different functions within its general area
of application.
- Unlike full-custom ASIC's, semi-custom ASIC's are designed to
allow a certain degree of modification during the
manufacturing process.
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FPGA

-FPGA stands for Field Programmable Gate Array.

-An FPGA is an integrated circuit designed to be configured by
the customer or designer after manufacturinghence "field-
programmable".
-The FPGA configuration is generally specified using a Hardware
Description language (HDL).
-FPGAs can be used to implement any logical function that an
ASIC could perform.

FPGA ARCHITECTURE

#The most common FPGA architecture consists of

I. Logic blocks-
called Configurable Logic Block (CLB) or Logic Array Block
(LAB) depending on vendor.
ii. I/O pads
Multiple I/O pads may fit into the height of one row or the width
of one column in the array.
iii.Interconnect (routing channels)
Generally, all the routing channels have the same width (number
of wires.

FPGA
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ARCHITECTURE

i.CLB or LAB

-- The multiplexer requires an associated configuration cell to

specify which input is to be selected.
- The register requires associated cells whether is to act as a
edge triggered flip-flop or level sensitive latch.
-4-input LUT is itself based on 16 configuration cells.

FPGA ARCHITECTURE

i.CLB or LAB- Look Up Table (LUT)

-we can program the LUTs to be whatever type of gate is needed by the
design.
-There are a finite number of LUTs within a given FPGA (also called
"resources").
-A LUT (Lookup table) is a one bit wide memory array.
-A 4-input AND gate is replaced by a LUT that has four address inputs and
one single bit output with 16 one bit locations.
-Location 15 would have a logic value 1 stored, all others would be zero

FPGA ARCHITECTURE

iii.Programmable Interconnect (Routing

Channels)

-In Xilinx routing, connections are made from logic block into the
channel through a connection block,
-A logic block is surrounded by connection blocks on all four sides.
-The logic block pins connecting to connection blocks can then be
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connected to any number of wire segments through switching

blocks/boxes.

FPGA ARCHITECTURE

ii. Programmable Interconnect- Switching

i

Box
- Whenever a vertical and a horizontal channel intersect there is
a switch box.
- When a wire enters a switch box, there are three
programmable switches that allow it to connect to three other
wires in adjacent channel segments.
- The pattern, or topology, of switches used in this architecture
is the planar or domain-based switch box topology.

BASIC

PRO

CES

S/PROGRAMMING TECHNOLOGIES OF AN

FPGA

Three major circuit technologies used for configuration an

FPGA.
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-SRAM
Can be programmed many times.
Must be programmed at power-up.
-Antifuse
Programmed once.
-Flash
Similar to SRAM but using flash memory.

SRAM Based FPGA

-SRAM Based FPGA old their configuration in static memory.

-Program logic functions, interconnect using SRAM.
-Advantages:
. Re-programmable
dynamically reconfigurable
The circuits use in FPGA can be fabricated with standard
VLSI processes.
Disadvantages:
SRAM burns power.
Possible to steal, disrupt configuration bits.

Antifuse-Based FPGA

-Permanently programmed.
-Make a connection with electrical signal.
-More reliable than breaking a connection.
-Logic Interconnect via metal-to-metal antifuse elements
between Metal-1 & Metal-2 as shown in figure
-Resides in a high-impedance state and
Can be programmed into low impedance or "fused" state
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FLash-Based FPGA

Flash memory is a high programmable read only memory

Flash uses a floating gate structure in which a low-leakage
capacitor holds a voltage that controls a transistor gate.
One cell control the two transistor as shown in figure.
FLash-Based FPGA

Advantages
Can be programmed without external storage of configuration
Disadvantages
HARDWARE DESCRIPTION LANGUAGE (HDL)
A hardware Description Language (HDL) is any language for
description and design of electronic circuits, and most
commonly, digital logic.
It can describe the circuit's operation, its design and
organization, and tests to verify its operation by means
of simulation.

HDL Types
The most widely used and well-supported HDLs are
1. Verilog- Verification Logics
2. VHDL-VHSIC Hardware description language
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VHDL

-VHDL is an acronym of VHSIC Hardware Description Language

-VHSIC is an acronym of Very High Speed Integrated Circuits
-VHDL is a programming language that allows one to model and develop
complex digital systems in a dynamic environment.
-VHDL is intended for circuit synthesis as well as circuit simulation.
-VHDL enables hardware modeling from the gate to system level.

FUNDAMENTAL UNITS OF VHDL CODE

VHDL code is composed of at least three fundamental sections

1. Library/Package Declaration:
Contains a list of all libraries and respective packages to be used in
the design. For example: ieee, std, work, etc.
2. Entity
Specifies the mainly I/O ports of the circuit, plus (optional) generic
constants.

3. Architecture
Contains the VHDL code proper, which describes how the circuit
should behave (function).

Library Declarations
A LIBRARY is a collection of commonly used pieces of code.
Placing such pieces inside a library allows them to be
reused or shared by other designs.
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General Syntax is

LIBRARY library_name;
USE library_name.package_name.pakage_parts;

2ENTITY

The main part of an Entity is port , which is a list with

specification of all input and output ports(pins) of the
circuit.
A simplified sytax is shown below.

ENTITY entity_name IS
PORT( port_name: signal_mode signal_type;
port_name: signal_mode signal_type;
..);
END [ENTITY] [entity_name];
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All members of the PORT field in the syntax above are SIGNALS
Signal_mode can be IN, OUT, INOUT, or BUFFER.
Signal_type can be BIT, INTEGER, STD_LOGIC, and so on.

3 ARCHITECTURE

The ARCHITECTURE is a description of how the circuit should

behave.
architecture has two parts:
a declarative part (optional), where signals and constants (among
others) are declared
the code part
ARCHITECTURE architecture_name OF entity_name IS
[declarative_part ]
BEGIN
[Code_part]
END [ARCHITECTURE] [architecture_name] ;

VHDL OBJECTS

An object is a named item of a specific type that has a value.

For example all GENERIC and PORT items are objects.
VHDL objects are
-SIGNAL
- VARIABLE
- CONSTANT
1

SIGNAL

SIGNAL serves to pass values in and out of the circuit as well as

between its internal units.
A signal represents circuit interconnects (wires).
All ports of an Entity are signals by default.
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Signal declaration can be made in the declarative part of

ENTITY, ARCHITECTURE, PACKAGE ,GENERATE.
Signal declarations are not allowed in sequential code (i.e.,
PROCESS and subprograms) but signal can be used there.
Must be declared before use

VARIABLE

-VARIABLE represents only local information because it can be

only seen and modified inside the sequential unit (inside
Process).
-VARIABLE is also declare inside the Process.
-VARIABLE update immediately, so the new value can be
promptly used in the next line of code.
-We can assign the multiple values to the same VARIABLE.
Assignment is done with :=

Concurrent versus Sequential code

-VHDL code is inherently concurrent (parallel).

-Only statements placed inside a PROCESS, FUNCTION, or
PROCEDURE are sequential. Still, though within these blocks
the execution is sequential, the block, as a whole, is
concurrent with any other (external) statements.
- Concurrent code is also called dataflow code.
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A VHDL architecture contains a set of

concurrent statements.

Each concurrent statement defines one of the interconnected

blocks or processes that describe the overall behavior or
structure of a design.
Concurrent statements in a design execute continuously.
The concurrent statements in VHDL are
-WHEN
-GENERATE
Only Arithmetic & Logical Operators can be used with these
Concurrent statements to create a combinational circuits.

WHEN is one of the fundamental concurrent statements

(along with operators and GENERATE).

Two types of WHEN statements

WHEN/ELSE (Simple WHEN)

WITH/SELECT/WHEN (Selected WHEN)

-The syntax for Simple WHEN is shown below.
assignment WHEN condition ELSE
assignment WHEN condition ELSE
.
assignment;
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