FPGA

1
Inside the FPGA

2
Downloading a code

3
Basic constructs of
VHDL
HDL :
Has semantics and syntax
Not a traditional PL
Describes Hardware

4
Construction of an
HDL code
Encapsulate the concepts of entity, connectivity, concurrency, and timing
Incorporate propagation delay and timing information
Consist of constructs for structural implementation
Incorporate constructs for behavioral description (sequential execution of
traditional PL)
Describe the operations and structures in gate level and RT level.
Consist of constructs to support hierarchical design process

--Verilog and VHDL ?

5
Entity and architecture
Entity defines a model
Architecture implements the
model
Example 2.1 : Even parity
detector

6
Even parity detector

Gives one if the number of '1's is even

Pseudo code a(2) a(1) a(0) out
count = 0 0 0 0 1
loop on the input bits { 0 0 1 0
if bit =1 then 0 1 0 0
count =count+1
0 1 1 1
}
1 0 0 0
out = 0
1 0 1 1
If count%2 =0 then
1 1 0 1
out =1
1 1 1 0

7
Entity

a0

a1 even
even_detector
a2

8
Architecture

9
Even parity detector
SOP :
Even = a(0)'a(1)'a(2)' +
a(0)a(1)a(2)'+ a(0)a(1)'a(2)+
a(0)'a(1)a(2)

10
Even parity detection
using XOR
Examples 2.2: XOR parity
detection
Conceptual interpretation
Structural interpretation
Behavioral interpretation

11
Structural description

12
Behavioral description

13