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LIBRARY ieee;
USE ieee.std_logic_1164.all;
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ENTITY reg_mux IS
PORT (a, b, c, d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
clk: IN STD_LOGIC;
x, y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY;
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ARCHITECTURE reg_mux OF reg_mux IS
SIGNAL mux: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
mux <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel="10" ELSE
d;
x <= mux;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
y <= mux;
END IF;
END PROCESS;
END ARCHITECTURE;
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
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ENTITY reg_mux_tb IS
END ENTITY;
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ARCHITECTURE testbench OF reg_mux_tb IS
----DUT declaration:--------
COMPONENT reg_mux IS
PORT (a, b, c, d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
sel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
clk: IN STD_LOGIC;
x, y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
----Signal declarations:----
SIGNAL a_tb: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
SIGNAL b_tb: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
SIGNAL c_tb: STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
SIGNAL d_tb: STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
SIGNAL sel_tb: STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
SIGNAL clk_tb: STD_LOGIC := '0';
SIGNAL x_tb: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL y_tb: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
---DUT instantiation:-------
dut: reg_mux PORT MAP (
a => a_tb,
b => b_tb,
c => c_tb,
d => d_tb,
clk => clk_tb,
sel => sel_tb,
x => x_tb,
y => y_tb);
---Stimuli generation:------
clk_tb <= NOT clk_tb AFTER 40ns;
a_tb <= "0011" AFTER 80ns, "0000" AFTER 640ns;
b_tb <= "0101" AFTER 240ns;
c_tb <= "0111" AFTER 400ns;
d_tb <= "1001" AFTER 560ns;
sel_tb <= "01" AFTER 160ns,
"10" AFTER 320ns,
"11" AFTER 480ns,
"00" AFTER 640ns;
END ARCHITECTURE;
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