Verilog

Advantages of HDL based Design Technique

HDL based design technique offers the following advantages over
conventional design approaches.
1.It is technology independent.
2.HDL shortens the design cycle of a chip by efficiently describing and
simulating the behavior of the chip.
3. A complex circuit can be designed using a few lines of HDL code
4. It lowers the cost of design of an IC
5. It improves design quality of a chip.
6. It can optimize area and timing of the chip and analyze in different
stages of design of a chip.
Types of Verilog Coding Style
There are three types of Verilog coding style.
RTL Verilog Code: RTL is the acronym of Register transfer Level
which is a type of representation style for digital circuit.
Any complex digital system can be partitioned into different modules.
each
module consists of registers and gates.
Information is stored in the registers and specific operation is
performed using the information, and then it is transferred among the
registers.
Hence the said representation style is known as RTL.
Example of RTL code of a 2/1 Mux
module mux_21(A, B, S, Y);
input A, B, S;
output Y;
reg Y;
always @ (S or A or B) begin
if (S= =1) Y=A;
else Y=B;
endmodule

RTL Verilog code of a digital design can be written in two ways.

One is using continuous assignment structures. It is also named as
modeling digital circuit at data flow level. The keyword ‘assign’ is used
to write a continuous assignment.
Another is using procedural assignment structure.

-Continuous assignment structure requires higher level of abstraction

than
structural Verilog coding.
-RTL coding using continuous assignment is more complex than can be
handled by structural modeling.
-the assignments written in RTL coding using continuous assignment
procedure are evaluated continuously whereas in procedural
assignment structure execution of a statement waits for the clock or
other parameters.

Structural Verilog Code: It describes the components and

interconnections present in a design.
Electronic Design Automation (EDA) tool compiles and synthesizes the
RTL code of a design and produces the netlist of the design in the form
of structural code.
Example of Structural Code Showing a 2/1 Mux

module mux (A, B, S, Out);

input A, B, S;
output Out;
wire M, N, P;
and g1 (N, B, S);
and g2 (P, M, A);
not g3 (M, S);
or g4 (Out, N, P);
endmodule

Behavioral Verilog code: Behavioral code describes the functionality

and behavior of the functional block diagram of a design.
It is often used for system level modeling and simulation of a design.

Digital System Design and Implementation

To realize the design of a semiconductor device into physical
hardware, it can be downloaded into Programmable Logic Device (PLD)
or Field Programmable
Gate Array (FPGA).
There are many steps for fabrication of a semiconductor device. The
most important step of a design is system idea or specification. It is
said that specification is 1/3 of total IC design project.
It requires extensive experience to define the best compromise
between what is wanted and what can be made.
There are two approach for a Semiconductor System Design.
1. Bottom-up process
2. Top-down process
Design approach depends on the nature of application of the design.
Bottom-up process
When performance, reliability and accuracy are prime importance then
bottom-up approach is followed.
example: space application, scientific application etc

advantages
performance – performance is high.
Reliability – it is reliable.
Accuracy – Accuracy is high.

Disadvantages
-Labor intensive and burdened with high cost
-long design time

Top-down process
When relatively short turn-around time and moderate area
performance are
required then top-down approach is well suited for purely digital
design.
advantages
short design time
Labor cost is low
Disadvantages
Accuracy is not so high
Performance is moderate

Steps
-HDL code of a design is written using software provided editor
-it is compiled and simulated to test the expected functionality using
EDA tool.
-Once the functional simulation of a design is completed then the RTL
code of ----the design is synthesized into logic gates using EDA tool.
Syntax used in Verilog HDL are very much similar to those in C
Programming
language.
Identifiers: Identifiers are the names used to give for an object such
as input, output, module etc in the design.
It must start with a letter or underscore (a-z, A-Z, _ ).
Identifiers may contain alphabetic characters, numeric characters, the
underscore, and the dollar sign (a-z, A-Z, 0-9, _ $).
Identifiers can be up to 1024 characters long.
Never use the Verilog keywords as identifier.
Examples of identifiers are: input In1, In2, Out_1, i386A.
Keywords: Verilog has a number of keywords or reserved words
All keywords are used in lower case in the Verilog code.

module - To start Verilog coding of a design

endmodule - To end the Verilog code of a module

and - To declare primitive AND gate

nand – To declare primitive NAND gate
or - To declare primitive OR gate
xor - To declare primitive XOR gate
nor – To declare primitive NOR gate
xnor - To declare primitive XNOR gate

input – To declare input ports

output - To declare output ports
inout - To declare bidirectional ports

begin – To start a block of statements

end – To terminate a block of statements

always – To describe the behavior of a circuit i.e. what the circuit

always do.
assign – To assign a value from RHS to LHS

Logic Values: Logic values normally take two levels:

1 signifies high or true
0 signifies low or false
But there are four logic levels.
High – 1
Low – 0
Unknown – X
High impedance state – Z
Structural Verilog Code of a Digital Circuit
To write structural Verilog code of a circuit:
Start Verilog coding using the keyword module
Give an arbitrary name for the circuit that we want to design
Write all the inputs and outputs within a first bracket. Sequence is
not matter.
Declare which are inputs (that we have listed in the first bracket). If
bit width is more than 1 bit then it needs to be shown.
Declare which are outputs including number of bits
Declare the internal signals of the circuit
Instantiate the logic gates that we have used in the design (or, not,
and)
 Specify the output and inputs of the logic gate within a first bracket
(after the instantiation name). Sequence is name of the output and
then input
for example

Verilog Code of the Circuit

module exampl_ckt (A, B, C, D);
input A, B, C;
output D;
wire M, N;
or g1 (M, A, B);
not g2 (N, C);
and g3 (D, M, N);
endmodule

7 segment

Ans:
This code will take a four bit number and decode it into the seven individual segments to
drive a seven segment display. nIn is the four bit number to be decoded and ssOut is the
array of segments for the display going from a, being the LSB, to g being the MSB.

module SevenSegmentDisplayDecoder(ssOut, nIn);

output reg [6:0] ssOut;
input [3:0] nIn;
// ssOut format {g, f, e, d, c, b, a}
always @(nIn)
case (nIn)
4'h0: ssOut = 7'b0111111;
4'h1: ssOut = 7'b0000110;
4'h2: ssOut = 7'b1011011;
4'h3: ssOut = 7'b1001111;
4'h4: ssOut = 7'b1100110;
4'h5: ssOut = 7'b1101101;
4'h6: ssOut = 7'b1111101;
4'h7: ssOut = 7'b0000111;
4'h8: ssOut = 7'b1111111;
4'h9: ssOut = 7'b1100111;
4'hA: ssOut = 7'b1110111;
4'hB: ssOut = 7'b1111100;
4'hC: ssOut = 7'b0111001;
4'hD: ssOut = 7'b1011110;
4'hE: ssOut = 7'b1111001;
4'hF: ssOut = 7'b1110001;
endcase
endmodule