Tl3695 Differential Bus Transceiver

TL3695
DIFFERENTIAL BUS TRANSCEIVER

SLLS044D NOVEMBER 1988 REVISED DECEMBER 1999
D Bidirectional Transceiver D OR P PACKAGE
D Meets or Exceeds the Requirements of

(TOP VIEW)
TIA/EIA-422-B, TIA/EIA-485-A, and ITU R 1 8 VCC

Recommendation V.11
RE 2 7 B
D High-Speed Advanced Low-Power Schottky DE 3 6 A
Circuitry D 4 5 GND
D Low Skew . . . 6 ns Max
D Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D Low Supply-Current Requirements . . .
30 mA Max
D Wide Positive and Negative Input/Output
Bus-Voltage Ranges
D Driver Output Capacity . . . 60 mA
D Thermal-Shutdown Protection
D Driver Positive and Negative Current
Limiting
D Receiver Input Impedances . . . 12 k Min
D Receiver Input Sensitivity . . . 200 mV Max
D Receiver Input Hysteresis . . . 120 mV Typ
D Fail Safe . . . High Receiver Output With
Inputs Open
D Operates From a Single 5-V Supply
D Glitch-Free Power-Up and Power-Down
Protection
D Interchangeable With National DS3695 and
DS3695A
description
The TL3695 differential bus transceiver is designed for bidirectional data communication on multipoint
bus-transmission lines. It is designed for balanced transmission lines and meets TIA/EIA-422-B,
TIA/EIA-485-A, and ITU Recommendation V.11.
The TL3695 combines a 3-state differential line driver and a differential input line receiver, both of which operate
from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively,
which can be externally connected together to function as a directional control. The driver differential outputs
and the receiver differential inputs are connected internally to form a differential input/output (I/O) bus port that
is designed to offer minimum loading to the bus when the driver is disabled or VCC = 0. This port features wide
positive and negative common-mode voltage ranges, making the device suitable for party line applications.
The TL3695 is characterized for operation from 0C to 70C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

TL3695
AVAILABLE OPTIONS
PACKAGED DEVICES
TA SMALL OUTLINE PLASTIC DIP
(D) (P)
0C to 70C TL3695D TL3695P
The D package is available taped and reeled. Add the suffix R
to device type (e.g., TL3695DR).
Function Tables
DRIVER
INPUT ENABLE OUTPUTS
D DE A B
H H H L
L H L H
X L Z Z
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
AB RE R
VID 0.2 V L H
0.2 V < VID < 0.2 V L ?
VID 0.2 V L L
X H Z
Inputs open L H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
logic symbol logic diagram (positive logic)

3 3
DE EN1 DE
2
RE EN2
4
D
6
4 1 A
D 7 2
1 B RE 6
A
1
1 R 7 Bus
R 2 B
This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

TL3695
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT
VCC VCC VCC
R(eq) 180 k 85
NOM NOM
Connected
on A Port
Input
3 k
A or B NOM
18 k
NOM Output
180 k
Driver Input: R(eq) = 3 k NOM
NOM
Enable Inputs: R(eq) = 8 k NOM 1.1 k
Connected
R(eq) = equivalent resistor NOM
on B Port
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V to 15 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.

TL3695
recommended operating conditions

MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
12
Voltage at any bus terminal (separately or common mode),
mode) VI or VIC V
7
High-level Input voltage, VIH D, DE, and RE 2 V
Low-level Input voltage, VIL D, DE, and RE 0.8 V
Differential input voltage, VID (see Note 3) 12 V
Driver 60 mA
High level output current,
High-level current IOH
Receiver 400 A
Driver 60
Low level output current
Low-level current, IOL mA
Receiver 8
Operating free-air temperature, TA 0 70 C
NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.

TL3695
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIK Input clamp voltage II = 18 mA 1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 5 V
1/2 VOD1
RL = 100 ,
See Figure 1 V
|VOD2| Differential output voltage or 2
RL = 54 , See Figure 1 1.5 2.5 5 V
VOD3 Differential output voltage Vtest = 7 V to 12 V, See Figure 2 1.5 5 V
Change in magnitude of differential output
|VOD| 0.2 V
voltage
VOC Common-mode output voltage RL = 54 , See Figure 1 3 V
Change in magnitude of common-mode
|VOC| 0.2 V
output voltage
Output disabled,, VO = 12 V 1
IO Output current mA
See Note 4 VO = 7 V 0.8
IIH High-level input current VI = 2.4 V 20 A
IIL Low-level input current VI = 0.4 V 200 A
VO = 6 V 250
VO = 0 150
IOS Short circuit output current#
Short-circuit mA
VO = VCC 250
VO = 8 V 250
Outputs enabled 23 50
ICC Supply current No load mA
Outputs disabled 19 35
The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
All typical values are at VCC = 5 V and TA = 25C.
The minimum VOD2 with a 100- load is either 1/2 VOD1 or 2 V, whichever is greater.
|VOD| and |VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
# Duration of the short circuit should not exceed one second for this test.
NOTE 4: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a
combined driver and receiver terminal.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
td(OD) Differential-output delay time 8 22 ns
Skew (|td(ODH) td(ODL)|) CL1 = CL2 = 100 pF, RL = 60 , See Figure 3 1 8 ns
tt(OD) Differential output transition time 8 18 ns
tPZH Output enable time to high level CL = 100 pF, RL = 500 , See Figure 4 50 ns
tPZL Output enable time to low level CL = 100 pF, RL = 500 , See Figure 5 50 ns
tPHZ Output disable time from high level CL = 15 pF, RL = 500 , See Figure 4 8 30 ns
tPLZ Output disable time from low level CL = 15 pF, RL = 500 , See Figure 5 8 30 ns

TL3695
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A
VO Voa, Vob Voa, Vob
|VOD1| Vo Vo
|VOD2| Vt (RL = 100 ) Vt (RL = 54 )
Vt (test termination
|VOD3|
measurement 2)
Vtest Vtst
|VOD| | |Vt| |Vt| | | |Vt| |Vt| |
VOC |Vos| |Vos|
|VOC| | Vos Vos | | Vos Vos |
IOS | Isa |, | Isb |
IO | Ixa |, | Ixb | Iia, Iib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply

voltage, and operating free-air temperature range (unless otherwise noted)
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = 0.4 mA 0.2 V
VIT Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA 0.2 V
Vhys Hysteresis voltage (VIT+ VIT) VOC = 0 70 mV
VIK Enable-input clamp voltage II = 18 mA 1.5 V
VID = 200 mV or inputs open,,
VOH High level output voltage
High-level 24
2.4 V
IOH = 400 A, See Figure 6
VID = 200 mV,, IOL = 16 mA 0.5
VOL Low level output voltage
Low-level V
See Figure 6 IOL = 8 mA 0.45
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V 20 A
Other input = 0,, VI = 12 V 1
II Line input current mA
See Note 5 VI = 7 V 0.8
IIH High-level enable-input current VIH = 2.7 V 20 A
IIL Low-level enable-input current VIL = 0.4 V 100 A
rI Input resistance 12 k
IOS Short-circuit output current VO = 0 15 85 mA
Outputs enabled 23 50
ICC Supply current No load mA
Outputs disabled 19 35
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
Duration of the short circuit should not exceed one second for this test.
NOTE 5: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.

TL3695
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, CL = 15 pF
tPLH Propagation delay time, low- to high-level output VID = 1.5 V to 1.5 V,, 14 37 ns
tPHL Propagation delay time, high- to low-level output See Figure 7 14 37 ns
tPZH Output enable time to high level 7 20 ns
See Figure 8
tPZL Output enable time to low level 7 20 ns
tPHZ Output disable time from high level 7 16 ns
See Figure 8
tPLZ Output disable time from low level 8 16 ns
PARAMETER MEASUREMENT INFORMATION
R
L
2
VOD2
R
L VOC
2
Figure 1. Driver VOD and VOC
375
VOD3 60
Vtest
375
Figure 2. Driver VOD3
3V
Input 1.5 V 1.5 V
CL1 = 100 pF 0V
(see Note A) Output
td(ODH) td(ODL)
RL = 60
Generator 50 CL 2 = 100 pF 2.5 V
(see Note B) 90%
(see Note A) Output 50% 50%
10% 2.5 V
3V
tt(OD) tt(OD)
TEST CIRCUIT VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.

B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 6 ns, tf 6 ns,
ZO = 50 .
Figure 3. Driver Differential-Output Test Circuit and Voltage Waveforms

TL3695
S1
3V
0 V to 3 V Output Input 1.5 V 1.5 V
0V
CL RL = 500
Generator (see Note A) tPZH 0.5 V
(see Note B) 50 VOH
Output 2.3 V
tPHZ Voff 0 V

B. The input pulse is supplied by a generator having the following characteristics: PRR 1 MHz, 50% duty cycle, tr 10 ns,
tf 10 ns, ZO = 50 .
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
RL = 500 3V
Input 1.5 V 1.5 V
S1 Output
3 V or 0 V 0V
tPZL tPLZ
CL
Generator (see Note A) 5V
(see Note B) 50 2.3 V 0.5 V
Output
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT

tf 10 ns, ZO = 50 ..
Figure 5. Driver Test Circuit and Voltage Waveforms

TL3695
VID
VOH
+ IOL IOH
VOL
Figure 6. Receiver VOH and VOL
5V
1 k 2.5 V
Input 0V 0V
Output
Generator 2.5 V
51
(see Note B)
CL = 15 pF 1N916 tPLH tPHL
(see Note A) or
1 k Equivalent VOH
Output 1.5 V 1.5 V
0V
VOL

tf 10 ns, ZO = 50 .
Figure 7. Receiver Test Circuit and Voltage Waveforms

TL3695
5V
S2
1.5 V S1 2 k
1.5 V Output
CL = 15 pF 1 k 1N916 or Equivalent
(see Note A)
Generator
(see Note B) 50
S3
TEST CIRCUIT
3V 3V S1 to 1.5 V
Input S1 to 1.5 V
1.5 V Input 1.5 V S2 Closed
S2 Open
0V S3 Closed 0V S3 Open
tPZH tPZL
VOH
4.5 V
Output 1.5 V Output 1.5 V
0V VOL
3V S1 to 1.5 V 3V S1 to 1.5 V
Input 1.5 V S2 Open Input 1.5 V S2 Closed
0V S3 Closed 0V S3 Open
tPHZ tPLZ
0.5 V
VOH 1.3 V
Output Output 0.5 V
1.3 V VOL
VOLTAGE WAVEFORMS

tf 10 ns, ZO = 50 .
Figure 8. Receiver Test Circuit and Voltage Waveforms

TL3695
TYPICAL CHARACTERISTICS
DRIVER DRIVER
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
5 5
VCC = 5 V VCC = 5 V
4.5 TA = 25C 4.5 TA = 25C
VOL Low-Level Output Voltage V

OH High-Level Output Voltage V
4 4
3.5 3.5
3 3
2.5 2.5
2 2
1.5 1.5
VOL
1 1
VV0H
0.5 0.5
0 0
0 20 40 60 80 100 120 0 20 40 60 80 100 120
IOH High-Level Output Current mA IOL Low-Level Output Current mA
Figure 9 Figure 10
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
VCC = 5 V
TA = 25C
3.5
VOD Differential Output Voltage V
2.5
1.5
1
VOD
0.5
0
0 10 20 30 40 50 60 70 80 90 100
IO Output Current mA
Figure 11
Operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

TL3695
RECEIVER RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE
vs vs
HIGH-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
5 5
VCC = 5 V
VID = 0.2 V
VID = 200 mV
TA = 25C
IOH = 440 A

4 4
3 3
VCC = 5.25 V
2 2
VCC = 5 V
VCC = 4.75 V
1 1
VV0H
VV0H
0 0
0 10 20 30 40 50 40 20 0 20 40 60 80 100 120
IOH High-Level Output Current mA TA Free-Air Temperature C
Figure 12 Figure 13
RECEIVER RECEIVER
LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs
LOW-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE
0.6 0.6
VCC = 5 V VCC = 5 V
TA = 25C VID = 200 mV
IOL = 8 mA
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
VOL
VOL
0.1 0.1
0 0
0 5 10 15 20 25 30 40 20 0 20 40 60 80 100 120
IOL Low-Level Output Current mA TA Free-Air Temperature C
Figure 14 Figure 15

TL3695
RECEIVER
RECEIVER
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
ENABLE VOLTAGE
ENABLE VOLTAGE
5
VID = 0.2 V 6
Load = 8 k to GND VID = 0.2 V VCC = 5.25 V
TA = 25C Load = 1 k to VCC
VCC = 5.25 V 5 TA = 25C
4
VCC = 4.75 V
O Output Voltage V
O Output Voltage V
4
3 VCC = 4.75 V VCC = 5 V
VCC = 5 V
3
2
2
VV)
VV)
1
1
0
0
0 0.5 1 1.5 2 2.5 3
0 0.5 1 1.5 2 2.5 3
VI Enable Voltage V VI Enable Voltage V
Figure 16 Figure 17
APPLICATION INFORMATION
TL3695 TL3695
RT RT
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept
as short as possible.
Figure 18. Typical Application Circuit

IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL
APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMERS RISK.
In order to minimize risks associated with the customers applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TIs publication of information regarding any third
partys products or services does not constitute TIs approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated

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TL3695

DIFFERENTIAL BUS TRANSCEIVER

D Bidirectional Transceiver D OR P PACKAGE

D Meets or Exceeds the Requirements of

TIA/EIA-422-B, TIA/EIA-485-A, and ITU R 1 8 VCC

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

logic symbol logic diagram (positive logic)

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

schematic of inputs and outputs

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3

recommended operating conditions

4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5

electrical characteristics over recommended ranges of common-mode input voltage, supply

6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 1. Driver VOD and VOC

Figure 2. Driver VOD3

NOTES: A. CL includes probe and jig capacitance.

Figure 3. Driver Differential-Output Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

Figure 4. Driver Test Circuit and Voltage Waveforms

NOTES: A. CL includes probe and jig capacitance.

Figure 5. Driver Test Circuit and Voltage Waveforms

8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 6. Receiver VOH and VOL

NOTES: A. CL includes probe and jig capacitance.

Figure 7. Receiver Test Circuit and Voltage Waveforms

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9

PARAMETER MEASUREMENT INFORMATION

NOTES: A. CL includes probe and jig capacitance.

Figure 8. Receiver Test Circuit and Voltage Waveforms

10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

VOL Low-Level Output Voltage V

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11

OH High-Level Output Voltage V

12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Figure 18. Typical Application Circuit

POST OFFICE BOX 655303 DALLAS, TEXAS 75265 13

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

Copyright 2000, Texas Instruments Incorporated

Datasheets for electronics components.

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