Processor register

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In computer architecture, a processor register is a small amount of storage available as part of a

CPU or other digital processor. Such registers are (typically) addressed by mechanisms other
than main memory and can be accessed more quickly. Almost all computers, load-store
architecture or not, load data from a larger memory into registers where it is used for arithmetic,
manipulated, or tested, by some machine instruction. Manipulated data is then often stored back
in main memory, either by the same instruction or a subsequent one. Modern processors use
either static or dynamic RAM as main memory, the latter often being implicitly accessed via one
or more cache levels. A common property of computer programs is locality of reference: the
same values are often accessed repeatedly and frequently used values held in registers improves
performance. This is what makes fast registers (and caches) meaningful.

Processor registers are normally at the top of the memory hierarchy, and provide the fastest way
to access data. The term normally refers only to the group of registers that are directly encoded
as part of an instruction, as defined by the instruction set. However, modern high performance
CPUs often have duplicates of these "architectural registers" in order to improve performance via
register renaming, allowing parallel and speculative execution. Modern x86 is perhaps the most
well known example of this technique.[1]

Allocating frequently used variables to registers can be critical to a program's performance. This
register allocation is either performed by a compiler, in the code generation phase, or manually,
by an assembly language programmer.

Contents
1 Categories of registers
2 Some examples
3 Register usage
4 See also
5 References

Categories of registers
Registers are normally measured by the number of bits they can hold, for example, an "8-bit
register" or a "32-bit register". A processor often contains several kinds of registers, that can be
classified accordingly to their content or instructions that operate on them:

User-accessible registers The most common division of user-accessible registers is

into data registers and address registers.
Data registers can hold numeric values such as integer and floating-point values, as well
as characters, small bit arrays and other data. In some older and low end CPUs, a special
data register, known as the accumulator, is used implicitly for many operations.
Address registers hold addresses and are used by instructions that indirectly access
primary memory.
o Some processors contain registers that may only be used to hold an address or
only to hold numeric values (in some cases used as an index register whose value
is added as an offset from some address); others allow registers to hold either kind
of quantity. A wide variety of possible addressing modes, used to specify the
effective address of an operand, exist.
o The stack pointer is used to manage the run-time stack. Rarely, other data stacks
are addressed by dedicated address registers, see stack machine.
Conditional registers hold truth values often used to determine whether some instruction
should or should not be executed.
General purpose registers (GPRs) can store both data and addresses, i.e., they are
combined Data/Address registers.
Floating point registers (FPRs) store floating point numbers in many architectures.
Constant registers hold read-only values such as zero, one, or pi.
Vector registers hold data for vector processing done by SIMD instructions (Single
Instruction, Multiple Data).
Special purpose registers (SPRs) hold program state; they usually include the program
counter (aka instruction pointer) and status register (aka processor status word). The
aforementioned stack pointer is sometimes also included in this group. Embedded
microprocessors can also have registers corresponding to specialized hardware elements.
o Instruction registers store the instruction currently being executed.
In some architectures, model-specific registers (also called machine-specific registers)
store data and settings related to the processor itself. Because their meanings are attached
to the design of a specific processor, they cannot be expected to remain standard between
processor generations.
Control and status registers There are three types: program counter, instruction
registers and program status word (PSW).
Registers related to fetching information from RAM, a collection of storage registers
located on separate chips from the CPU (unlike most of the above, these are generally not
architectural registers):
o Memory buffer register
o Memory data register
o Memory address register
o Memory Type Range Registers (MTRR)

Hardware registers are similar, but occur outside CPUs.

Some examples
Integer FP The table shows the number of registers of several
Architecture
registers registers mainstream architectures. Note that in x86-compatible
x86-32 8 8 processors the stack pointer (ESP) is counted as an
integer register, even though there are a limited
x86-64 16 16 number of instructions that may be used to operate on
IBM/360 16 4 its contents. Similar caveats apply to most
z/Architecture 16 16 architectures.
Itanium 128 128
SPARC 32 32 x86 FPUs have 8 80-bit stack levels in legacy mode,
and at least 8 128-bit XMM registers in SSE modes.
IBM Cell 4~16 1~4
IBM POWER 32 32 Although all of the above listed architectures are
Alpha 32 32 different, almost all are a basic arrangement known as
6502 3 0 the Von Neumann architecture, first proposed by the
Hungarian mathematician John von Neumann.
W65C816S 5 0
PIC microcontroller 1 0
AVR microcontroller 32 0
Register usage
ARM 32-bit[2] 16 varies The number of registers available on a processor and
[3]
ARM 64-bit 31 32 the operations that can be performed using those
registers has a significant impact on the efficiency of code generated by optimizing compilers.
The Strahler number of an expression tree gives the minimum number of registers required to
evaluate that expression tree.

See also
Computer science portal

Shift register
Register allocation
CPU cache

References
1. ^ Since around 1995 and the Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
2. ^ "Procedure Call Standard for the ARM Architecture". ARM Holdings. 16 October
2009. Retrieved 2012-04-24.
3. ^ "Procedure Call Standard for the ARM 64-bit Architecture". ARM Holdings. 25
November 2011. Retrieved 2012-04-24.

[hide]
 v
t
e

CPU technologies
ISA : CISC
EDGE
EPIC
MISC
OISC
RISC
VLIW
NISC
ZISC
Harvard architecture
von Neumann architecture
1-bit
4-bit
8-bit
Architecture
12-bit
16-bit
18-bit
24-bit
31-bit
32-bit
33-bit
36-bit
48-bit
60-bit
64-bit
128-bit
Comparison of CPU architectures

Instruction pipelining
In-order & out-of-order execution
Register renaming
Pipeline
Speculative execution
Hazards
Parallelism
Bit
Instruction
Level
Superscalar
Data
 Task

Multithreading
Simultaneous multithreading
Threads Hyperthreading
Superthreading

SISD
SIMD
Flynn's taxonomy MISD
MIMD

Digital signal processor

Microcontroller
Types System on a chip
Vector processor

Arithmetic logic unit (ALU)

Barrel shifter
Floating-point unit (FPU)
Back-side bus
Multiplexer
Demultiplexer
Registers
Components Memory management unit (MMU)
Translation lookaside buffer (TLB)
Cache
Register file
Microcode
Control unit
Clock rate

APM
ACPI
Dynamic frequency scaling
Power management
Dynamic voltage scaling
Clock gating

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This page was last modified on 15 July 2012 at 21:15.

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