Phase Lock Loop and Its Applications

(Note : Slides are prepared from book : Digital Integrated Circuit by

J. M. Rabey)

Dr. Amit M. Joshi

Assistant Professor
Malaviya National Institute of Technology
Jaipur (Rajasthan)

1
Contents

Phase Lock Loop (PLL) Basics

PLL Elements
PLL as a Frequency (clock) Synthesizer
PLL as a Clock Generator
Power Consumption

2
 Phase Lock Loop
PLL is a circuit that synchronize an output signal with a reference
or input signal in frequency as well as in phase.
PLL is an Electronic Module(Circuit) that locks the phase of the
output to the input.
PLL is a non linear feedback system that detects the phase error
and then adjusts the phase of the output.

Phase Difference
 Basic elements of PLL

UP
Reference Vcont
Clock Phase Detector Charge Pump Loop Filter VCO
Down
Local
Clock

Divided by N

System Clock
 Phase Detector
It determines the relative phase difference between two incoming
signals and outputs a signal that is proportional to this phase
difference.
One of the inputs to the phase detector is a reference clock that is
typically generated off chip while the other clock input is a divided
version of the VCO

UP
Reference Vcont
Phase Detector Charge Pump Loop Filter VCO
Clock
Down
Local
Clock

Divided by N
System Clock
 Phase Detector
It detects which of the two input signal arrives earlier and
produces the appropriate output signal
The local clock and reference clock are compared using a
phase detector that compares the phase difference between the
signals and produces an Up or Down signal when the local
clock lags or leads the reference signal.
 Phase Detector
Two basic types of phase detectors are commonly
used.
1. XOR gate and
2. phase frequency detector (PFD).
 XOR Phase Detector
ref
ref
Output local
clock
local Output
clock
(a) (b)
Output (Low pass filtered)
VDD

-180 -90 90 180 phase error (deg)

(c)
Drawback of the XOR phase detector
It may lock to a multiple of the clock frequency. If the
local clock is a multiple of the reference clock
frequency, the output of the phase detector will still
be a square wave of 50% duty cycle, albeit at a
different frequency.

The filtered version of this signal will be identical to

that of the truly locked state and thus the VCO will
operate at the nominal frequency.
XOR Behavior
 Phase-Frequency Detector

B A
Rst UP
D Q B

A UP = 0 UP = 0 UP = 1
A
DN = 1 DN = 0 DN = 0
Rst
D Q
DN
A B
B
(a) schematic (b) state transition diagram

A A

B B

UP UP

DN DN

(c) Timing waveforms

 Phase-Frequency Detector
PFD is dependent both on the phase and frequency difference of the
applied signals

The PFD takes two clock inputs and produces two outputs, UP and
DOWN.

The PFD is a state machine with 3 states. Assume that both UP and DN
outputs are initially low.

When input A leads B, UP output is asserted on the rising edge of input A.

The UP signal remain in this state until a low-to-high transition occurs on

input B.

At that time, the DN output is asserted, causing both flip-flops to reset

through the asynchronous reset signal.
 Charge Pump
Up and Down signals are fed into a charge pump, which translates
the digital encoded control information into an analog voltage.
Up signal increases value of control voltage thus speeds up VCO
that causes local clock to catch up with reference to clock
Down signal slows down the VCO and eliminates the phase lead
of local clock
Reference
Clock UP
Vcont
Phase Detector Charge Pump Loop Filter VCO
Down
Local
Clock

Divided by N

System Clock
 Charge Pump
The UP/DN pulses must be converted
to an analog voltage that controls the
VDD VCO.

A pulse on the UP signal adds a charge

to capacitor proportional to the width
UP To VCO Control Input of the UP pulse, and a pulse on the DN
signal removes a charge proportional
DN to the DN pulse.

If the width of the UP pulse is large

than the DN pulse, then there is a net
increase in the control voltage. This
effectively increases the frequency of
the VCO.
 Loop Filter(Low pass filter)
This low-pass filter removes the high-frequency components
from the VCO control voltage and smooth out its response,
which results in a reduction of the jitter.

UP
Reference Vcont
Phase Detector Charge Pump Loop Filter VCO
Clock
Down
Local
Clock

Divided by N

System Clock
 Loop Filter(Low pass filter)

The output of charge pump can not be given directly into VCO
because of presence of jitter

Clock jitter is highly undesirable because it reduces the local

computational logic time, therefore it should be kept within a
given percentage of the clock period
 Voltage Controlled Oscillator (VCO)
A VCO generates a periodic signal, whose frequency is a linear
function of the input control voltage Vcont.
VCO generates the output frequency such a manner that error is
minimized
VCO frequency is being compared with input frequency and adjusted
until it is equal to input frequency
Reference
Clock UP
Vcont
Phase Detector Charge Pump Loop Filter VCO
Down
Local
Clock

Divided by N

System Clock
Voltage Controlled Oscillator (VCO)
VCO is Characterized By

The phase is time integral of frequency

 PLL Applications
As a Clock (Frequency) Synthesis

As a Clock Synchronizer
 PLL based Clock Synthesis
Synthesizer: A special kind of circuit that contains one or more
PLLs. It receives a stimulus, usually a low frequency signal from a
crystal, and generates multiple outputs with different (integer or
fractional) frequencies.
 PLL based Clock Synthesis
The reference is derived from a precision XTAL oscillator. The
divider brings down the high frequency of the VCO signal to
the range of the reference frequency.
The PD compares the phase and produces an error signal,
which is smoothed out by the loop filter and applied to the
VCO.
When the system locks, the output phase of the VCO is locked
to the XTAL. That means that the frequency is also locked.
The output frequency fout is therefore an integer multiple of
the reference fref = fout/N or fout = N fref.
 PLL-Based Synchronization

Chip 1 Chip 2

Data
Digital Digital
System System

reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer

fcrystal 200<Mhz

Crystal
Oscillator

A PLL, using feedback, can be align (i.e., de-skew) the output of

the clock buffer with respect to the data.
 PLL Based Synchronization
PLLs are also used to perform synchronization of communication
between chips.
A reference clock is sent along with the parallel data being
communicated
Since chip-to-chip communication occurs at a lower rate than the
on-chip clock rate, the reference clock is a divided but in-phase
version of the system clock. The reference clock synchronizes all
input flip-flops on chip 2; this can present a significant clock load
for wide data busses.
Introducing clock buffers to deal with this problem unfortunately
introduces skew between the data and sample clock.
A PLL, using feedback, can be align (i.e., de-skew) the output of
the clock buffer with respect to the data.
PLL can multiply the frequency of the incoming reference clock,
allowing the reference clock to be a fraction of the data rate.
PLL based Synchronizing Example 2
Phase-lock looping is an extremely powerful synchronization technique
when performing data acquisition because it allows multiple acquisition
modules to lock to a shared reference signal.
As a result, these boards can synchronize the phase of their internal time
base and thus, their sample clocks. Because the phase of each sample clock
is synchronized.
Each board (acquisition modules ) can take a measurement at precisely the
same instant.
EXAMPLES
 Timing Diagrams
Contamination and
Propagation Delays
A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk->Q Prop. Delay

Flop
D Q D
tccq Latch/Flop Clk->Q Cont. Delay tpcq
Q tccq
tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay clk tsetup thold

clk
tccq tpcq

tsetup Latch/Flop Setup Time

Latch

D Q D tpdq
tcdq
thold Latch/Flop Hold Time Q

11: Sequential Circuits 26

 Max-Delay: Flip-Flops
t pd Tc tsetup t pcq
clk clk

Q1 D2
Combinational Logic

F1

F2
sequencing overhead

Tc

tsetup
clk
tpcq

Q1 tpd

D2

11: Sequential Circuits 27

 Min-Delay: Flip-Flops
clk

tcd thold tccq Q1

CL

F1
clk

D2

F2
clk

Q1 tccq tcd

D2 thold

11: Sequential Circuits 28

 Skew: Flip-Flops
clk clk

t pd Tc t pcq tsetup tskew

Q1 D2
Combinational Logic

F1

F2
Tc

sequencing overhead
clk

tcd thold tccq tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1
CL

F1
clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd

11: Sequential Circuits 29

 Example 1
For each of the following sequencing styles, determine the maximum logic
propagation delay available within a 500 ps clock cycle. Assume there is
zero clock skew and
no time borrowing takes place.
a) Flip-flops

Use the timing parameters in Table 1 for solving the problem

Repeat if the clock skew between any two

elements can be up to 50 ps.

11: Sequential Circuits 30

 Solution
When skew is zero tpcq 50 ps
1 (a) tpd = 500 - (50 + 65) = 385 ps;
tccq 35 ps
.
tpdq 40ps
When skew is 50ps
tcdq 35ps
2 (a) tpd = 500 - (50 + 65 + 50) = 335 ps;
tsetup 65 ps /25ps

thold 30ps

11: Sequential Circuits 31

 Example 2
For each of the following sequencing styles, determine the minimum
logic contamination delay in each clock cycle (or half-cycle, for two-
phase latches). Assume there is zero clock skew.
a) Flip-flops

Repeat Exercise if the clock skew between

any two elements can be up to 50 ps.

11: Sequential Circuits 32

 Solution
3 (a) tcd = 30 - 35 = 0; tpcq 50 ps

tccq 35 ps

When skew is 50ps tpdq 40ps

tcdq 35ps
4 (a) tcd = 30 - 35 + 50 = 45 ps;
tsetup 65 ps /25ps

thold 30ps

11: Sequential Circuits 33

 References
1. Rabaey, J. M., Chandrakasan, A. P., & Nikoli, B. (2003). Digital
integrated circuits: A design perspective. Upper Saddle River, N.J:
Pearson Education

2. Neil Weste and David Harris. 2010. CMOS VLSI Design: A Circuits and
Systems Perspective (4th ed.). Addison-Wesley Publishing Company, ,
USA.

3. [online]http://www.ti.com/lit/an/scaa035b/scaa035b.pdf