Parallel Processing Machine Vision System
for Bare PCB Inspection
Ji-joong Hong, Kyung-ja Park, Kyung-gu Kim
LG Production Engineering Research Center
19-1 Cheongho-R Pyungtaik-City Kyunggi-Do, 45 1-713, Korea
E-mail :jhong@lge.co.kr
Abstract - In this paper, new real time bare PCB
inspection system and the inspection methods are
presented. After a brief introduction of classical
inspection methods, the outline of our new automatic
optical inspection(A0I) system configurations and
inspection methods are described.
The goal of our inspection system is the real time
inspection without a lot of computing power
consumption. Because the design-rule verification
process directly to the image patterns is a time
consuming process, its not appropriate to get real time
inspection speed. Instead of that, we chose the
reference comparison method and overcame the
disadvantages of it. This makes the inspection system
more cheaper, practical and efficient to realize the
real time inspection system. The design and
development of our prototype of new A01 system is
discussed and the test results are presented to show the
effectiveness of the developed inspection algorithm.
I. INTRODUCTION
The bare PCB means the printed circuit board before
the insertion or placement of components and the
soldering process, Following a material from Siemens
(Fig.l), the cost of bare PCB is just less than 8.7 ?LOof a
electrical goods. If a PCB having some faults is assembled
with many other components to complete a electric
product which is surely judged to inferior goods by final
electrical test, we should waste the total spent cost. So, its
by all means required to inspect the bare PCB at the
foremost step to produce electrics goods.
Wound
DPD Compon
lntegrat
ed
Circuits
Consum
able
Material s ,5.90%
S 6.50%
Fig. 1 Cost constitution of electrical products
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During etching process, the anomalies occuring on bare
PCB could be largely classified in two categories : the one
is excess of copper and the other one is missing copper.
The incomplete etching process leaves unwanted
conductive materials and forms defects like short, extra
hole, protrusion, island, small space and so on. And the
excessive etching makes open, pin hole, nick(mousebite),
thin pattern and something like that. In addition to the
defects metioned above, some other defects may exist on
bare PCB, for example, missing holes (due to tool break),
scratch (due to handling mistake), cracks and so forth. In
Fig.2. (b), there are shown some kinds of defects. In recent
years, the pattern width and space become smaller and
smaller to increase the integration rate of electrical
components per unit area of PCB. This means the size of
defect is also minute and actually may be less than 30
micron. This defects are not easily detected by the human
eyes and takes too much inspection time even though it is
possible. In this reason, the automatic optical inspection
systems are needed.
So far, many approaches for automatic bare PCB
inspection have been tried and proposed in the
literature[11. Below, a brief advantages and disadvantages
of those methods are described and compared each other.
A . DRC(Design Rule Checking)
As a kind of automatic inspection algorithm for bare
PCB, the design rule checking has been proposed and well
known to the A01 system manufacturers. DRC method
checks if all patterns and spaces of PCB surface meet or
violate common knowledge which is called the design
rule. Because a simple algorithm is applied directly to
achieved image, the implementation of this algorithm is
comparatively easy. This means it does not require severe
alignment and adjustment of a mechanical part to get non-
distorted image. However, this method is very time
consuming process and a great computing power is needed
to meet users requirement of inspection time. And much
time is taken to register the proper rules in every model
changing time.
Fig.2 is to show the concept of the morphological
inspection which is one of the representative DRC
algorithm. Fig.2 (b) is the artificially made bitmap image
which some kinds of defects are added on. Fig.2 (a) is the
original good image. If erosion and dilation of image (b)
is carried out alternately, then the result image subtracted
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from original image (a) represents the defect image (d). At
a glance, the defect image (d) may be seen as a good
result. But, even when we applied this algorithm to the
good image (a), some unwanted defects are detected at the
sharp edge of semi circle pattern and we call this false
alarm. This false alarms exist also on image (d). This is a
critical disadvantage of morphological inspection method
because a few of sharp patterns which exist on inner layer
can not be inspected correctly.
a ) Good Image b) D e f e c t s I m a g e
d) Defects i n c l u d i n g
c ) False Alarm by
F a l s e A l a r m by
Morphological
Morphological
Processing
Processing
Fig.2 Design Rule Checking PCB inspection method by
morphological processing
B. Reference comparison method
This method is very simple in aspect of idea. As shown
in Fig.3, a target image (b) is subtracted from good
reference image (a) to generate the difference image (c). It
means the point-to-point comparison. The reference data
is achieved from a good board which is sometimes called a
golden board or from CAD data[2] generated in the
former process. Because the algorithm is very simple, we
can get high inspection speed compared to DRC method.
However, as the amount of bitmap reference data is
hundreds of megabytes per each layer, to be compared
with multi layer boards, the inspection system is troubled
to store the reference data. Besides, as shown in Fig.3 (c),
we cant avoid from too many small differences between
the reference image and the target image on account of the
etching factor, misalignment of vision grabbing system,
the distortion of optical lens and so on. So, there must be a
special algorithm to distinguish these differences from
defects.
C. Hybrid methods
Nowadays, considering the state of affairs of a
inspection system, the combined inspection methods are
used. This hybrid type merged the advantages of the
reference comparison method and the DRC method to
overcome the weakeness of each methods. But, because
this is just focused on the reliability of detecting
capability, it is also a time consuming and hardware
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depending method requiring a great computing power and
cost..
a) R e f e r e n c e I m a g e b) T a r g e t PCB Image
c ) S u b t r a c t e d Image dl
( D e c i r ion A p p l i e d )
Fig.3 Reference comparison method
11. AUTOMATIC INSPECTION SYSTEM
The inspection system proposed in this paper is
basically adapting a reference comparison method. Three
main goals that we are pursueing are 1) the just on time
processing which means the total inspection would be
finished simultaneously as the scanning is finished to
attain the real time inspection and the efficiency of
memory, 2) the single pass processing system not refering
the past information of PCB image to save the inspection
time and 3) to allow some misalignment which makes the
mechanism cheaper and easer. To overcome the several
disadvantages arising in the reference comparison
method, some unique methods are proposed as described
below.
A . Overview of proposed parallel processing bare PCB
inspection system
In Fig.4, there is shown the block diagram of the
proposed bare PCB inspection system. From the CAD data
(here Gerber Data) which is output of artwork for PCB
patterns, the reference data is generated in the form of
MRL,C(Modified Run-Length Code) which is special
compressed data type of image. Each layer of MLB(mu1ti
layer board) is produced by exposure, developing, and
etching processes. A number of digital line scan cameras
grab and send the PCB images to frame grabbers and the
machine vision hardwares. Then, after certain pre-
processings like shading compensation, thresholding and
MRLC generation, the comparison between reference data
and target data is processed. And then, the decision if
clustered defect candidates are real defects or not.
This camera and vision hardware units are multiply
used condidering the maximum resolution and the PCB
size. Now maximum 8 cameras are established and the
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maximum inspection area is 600 x 600 mm2 for the
resolution of 10 micron. The defects of each cameras are
gathered and sent to the verification system to necessarily
identify the defect and repair the faults.
P W
3 Fig.6 The concept of Run-Length Code
Fig.4 Block diagram of proposed bare PCB inspection
system
Linear camera has 4096 pixels and maximum line rate
of 7.4 KHz. The vision hardware were developed by
ourselves using TI C40 processors. It is constituted with 4
modules : the digital line image grabber module to achieve
an image and store to SRAM (static random access
memory), the preprocessing module for thresholding,
shading compensation and run-length coding, the power
processing module for the main inspection, and display
module to show the result image on a monitor and
communicate with PC host. Especially, the pre-processing
hardware was developed by Arcobel Graphics Japan using
Imagin Chips. More detail data flow are shown in Fig.5.
. .
Fig.5 Vision hardware
B. MRLC (1ModiJiedRun-Length Code)
As described at the introduction of the reference
comparison inspection methods, the amount of bitmap
reference data is over hundreds of megabytes. The
reference data must be stored to S R A M for high access
speed not on the hard disk. If we consider the 500 x 600
mm area of PCB to be inspected and the resolution of 10
micron, though the image is binarized and compressed to
1 bit for 1 pixel, the size of memory to store reference
image is over 375 Mbytes. It increases the system cost too
high. Besides, if we compare pixel-to-pixel, due to the
redundant parts of small difference at edge of patterns, we
should suffer from the increase of inspection time and too
many false alarms.
By these reason, the run-length code is used to store the
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referece and target data. The conventional run-length code
has a value information -white or black- and the length
that how long the value runs (Fig.6).
A n
1 1 1 W
To be utilized at the comparison of inspection, several
flag informations like end of line, direction of patterns and
hole flags are inserted to the conventional run-length
code. The 2 bytes form of proposed modified run-length
code is shown in Fig.7.
value of run unused
2Bytes
end of line flag directionflag Length
(1bit) (1bit) (12 bits)
Fig.7 Modified Run-Length Code
As shown in Fig.8, the experimental result shows that
120 Mhytes bitmap image data can be compressed to only
4 Mbytes by means of MRLC method.
(16bits format)
120 Mbyte Data 4 Mbyte Data
Fig8 Compressingbitmap image data to MRLC
C. Generation of Reference data
The reference data which is compressed MRLC form is
getting by the CAD interface program. This program
converts the CAD output data like RS-274X or Gerber to
MRLC. To do so, at first it generate bitmap or vector
image to analyse the plotting information of CAD data
and then calculate the lengths of values. The flags
described at the above section are found in this step.
After the original Gerber or RS-274X file is converted
to bitmap image, considering the optimal manufacturing
condition, many operations change the original CAD data
to dispose the unit PCBs on the panel. So the last output
after panel editting must be converted to the MRLC
reference data. Fig.9 shows the editting process to be
modified in manufacturing site.
 I Original Data I
Panel
Editing
Fig.9 CAD data editting process
D.Real-time inspection algorithm
The inspection process is devided into two steps : the
one is clustering of defect candidates and the second one
is decision of the clustered candidates.
Step 1 : Clustering of defect candidates
The lines in the Fig.10 are representing the profiles of
reference and target patterns. The thick line A is the
reference profile which is type of MRLL!. The line A and
A are indivisually the profiles of expanded and reduced
target patterns. The light part (yellow) is indicating
copper pattern and the dark part (gray) is substrate. The
direct comparison of reference and target will leave the
marginal differences which are represented by dashed
rectangles. But, if we compare the length of them, the
small differences in edge part can be ignored because it is
not a defect but just expansion or contraction due to
etching conditions. Of course, the large differences to
violate the defect specifications would be classified into a
candidate of defects like B in Fig. 11.
expanded target
1 reduced target
Fig. 10 Small difference of patterns in edge
As in Fig. 11, when the target profile is compared to the
reference profile, the differences B and C are classified
into the candidates of defects. In contrast with the defects
on patterns, the defects on space could be applied to the
same situation. In this case, the value of space profiles are
converted to 0 and the defects would be 1.
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m reference
a
C
I target
Fig. 11 Defect candidates arising in pattern
Step 2 : Decision of defect candidates
When a MRLC difference is registered to defect
candidates, it generates a descriptor structure which
includes several informations, for example, length and
size, pointing index of the previous and next descriptors.
So, if the defect candidates were arised in vertical
patterns or spaces (Fig.12 a), the left and right MRLC are
examined to judge if the candiates are real defects or not.
In the same way, the defect candidates on the horizontal
patterns or spaces (Fig.12 b) are judged from the upper
and lower relationships.
dl
Fig. 12 Defects candidates on Vertical(a) and
Horizontal@)patterns
111. RESULTS AND CONCLUSION
In Fig.2, there was shown the inspection result using
morphological DRC method. There, we found the
unwanted defects, false alarms. In contrast with the result,
the inspection result using MRLC comparison method,
shown in Fig.13, has no false alarm. Red rectangles are
surrounded to the found defects to display the inspection
results. T h s image was artificially made with size of 512
x 512 pixels. The inspection times is only 10 msec while
the time for morphological processing is 2.8 sec for the
same size image. Of course, this image is so simple and
clean that makes the processing time short.
The result that same MRLC comparison method was
applied to the real image is shown in Fig.14. To be seen
clearly, the parts were cut out from the whole image. In
the normal patterns, no defect is not found although the
target pattern thickness (white) is slightly differenct from
the reference pattern (orange color).
 Fig. 13 Defects detected by MRLC comparison
(simulation)

1lil
ROTRUSIOI
NICK

Fig. 14 Inspection result of MlUC comparison algorithm

(real image)

The experimental results are found to be very effective.

This approach is found to handle all kinds of defects that
normally exist in bare printed circuit boards. Currently
there is no single full scale automated inspection system
that successfully inspects all kinds of defects that can exist
in a PC board. The method presented here is by no means
limited to this particular application or defect types.

IV. REFERENCES

[l] M.Moganti, F.Erca1, C.H.Dagli, and Shou

Tsunekawa, Automatic PCB Insection Algorithms:
A Survey, Computer Vision and Image
Understanding, Vol. 63, No.2, March 1996.

[2] Hideaki Doi, Yasuhiko Hara, Automated Inspection

of Printed Circuit Board Patterns Referenced to CAD
data, IAPR Workshop in Machine Vision
Applications, Dec.7-9, 1992

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