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Available Microchip PIC Assembler Source Code
Two independent RS232 interfaces, with display of received ASCII characters and corresponding decimal values on the dot matrix LCD.
ASCII values entered on one terminal window are transmitted by the first RS232 link to the controller, displayed on the LCD, and further
transmitted across the second RS232 link to the other terminal window. The microcontroller sends feedback of received characters back to
the issueing terminal window. When the PIC terminal is idle, it sends a status message '@' to both terminals every 2.75 seconds.
This program incorporates two independent RS232 interfaces, one hardware-based and one software-based. The HW-based RS232
interface uses the PIC-internal USART (and interrupts), configured to standard 9600 baud @ 4 MHz PIC clock. The SW-based RS232
interface is based on the module file m_rs096.asm, which performs interrupt-based RS232 reception on PortB0 (INTCON,INTF) at 9600
baud @ 4 MHz PIC clock.
The program shows the implementation and function of the modules m_bank.asm, m_wait.asm, m_lcd.asm, m_lcdv08.asm, and m_rs096.
asm on the PIC16F77.
The above program needs additional include files (modules) to get successfully assembled: m_bank.asm, m_wait.asm, m_lcd.asm
For those, who are not familiar with interfacing a PIC to the RS232 using a MAX232: RS232-Interface.pdf (9.7 kB)
[Toc] [Top]
;***************************************************************************
;
; Dual RS232 Software Interface for PIC 16F77 V1.00
; =================================================
;
; written by Peter Luethi, 15.01.2005, Urdorf, Switzerland
; http://www.electronic-engineering.ch
; last update: 16.01.2005
;
; V1.00: Initial release (16.01.2005)
;
; This code and accompanying files may be distributed freely and
; modified, provided this header with my name and this notice remain
; intact. Ownership rights remain with me.
; You may not sell this software without my approval.
;
; This software comes with no guarantee or warranty except for my
; good intentions. By using this code you agree to indemnify me from
; any liability that might arise from its use.
;
;
; SPECIFICATIONS:
; ===============
; Processor: Microchip PIC 16F77 (16C74A)
; Clock Frequency: 4.00 MHz (HS mode)
; Throughput: 1 MIPS
; RS232 Configuration: 9600 with BRGH = 1
; RS232 Baud Rate: 9600 baud, 8 bit, no parity, 1 stopbit
; Required Hardware: two MAX 232 for two RS232 interfaces,
; dot matrix LCD display
; Code Size of entire Program: approx. 733 instruction words
; Acquisition Methodology: SW-based RS232: Interrupt-based RS232
; data acquisition
; HW-based RS232: Preemptive,
; interrupt-based RS232 data acquisition
; with LCD display output and RS232 echo
; during normal operation
;
;
; ABSTRACT:
; =========
; Dual RS232 terminal: Two independent RS232 interfaces, with
;
;***************************************************************************
PROCESSOR 16F77
#include "p16f77.inc"
;PROCESSOR 16C74A
;#include "p16c74a.inc"
#include "..\..\m_bank.asm"
#include "..\..\m_wait.asm"
#include "..\..\m_rs096.asm" ; standard SW-based RS232
#include "..\..\m_lcd.asm" ; standard version (fixed delay)
;#include "..\..\m_lcd_bf.asm" ; fast, bi-directional version (busy flag)
#include "..\..\m_lcdv08.asm" ; 8 bit to decimal conversion for LCD
SEND2w macro
call _RSxmit
endm
COUNTERinit ; *** Initialize 24 bit counter for status message wait interval ***
clrf LOcnt ; init counter
clrf MEDcnt ; init counter
movlw d'6'
movwf HIcnt ; init counter
RETURN
RSservice ; *** RS232 echo & LCD display routine for received RS232 characters ***
; display on LCD
LCD_DDAdr 0x07
movfw RXD
LCDw ; ascii character output on LCD
LCD_DDAdr 0x0D
movfw RXD
movwf LO
LCDval_08 ; numeric ascii value output
; send echo back to PC
SEND TAB
SEND 't'
SEND 'r'
SEND 'a'
SEND 'n'
SEND 's'
SEND 'm'
SEND 'i'
SEND 't'
SEND 't'
SEND 'e'
SEND 'd'
SEND ' '
movfw RXD ; get received RS232 data
SENDw ; transmit across RS232 line
movfw RXD ; get received RS232 data
SEND2w ; transmit across other RS232 line
SEND ' '
SEND 't'
SEND 'o'
SEND ' '
SEND 'l'
SEND 'i'
SEND 'n'
SEND 'k'
SEND ' '
SEND '2'
SEND CR ; Carriage Return
SEND LF ; Line Feed
; end of RS232 service (echo & display)
bcf RSflagSW ; reset RS232 data reception flag
bsf INTCON,INTE ; re-enable RB0/INT interrupt
RETURN
RSservice2 ; *** RS232 echo & LCD display routine for received RS232 characters ***
SEND2 't'
SEND2 'e'
SEND2 'd'
SEND2 ' '
movfw RXtemp ; retrieve value
SEND2w ; transmit across RS232 line
movfw RXtemp ; retrieve value
SENDw ; transmit across other RS232 line
SEND2 ' '
SEND2 't'
SEND2 'o'
SEND2 ' '
SEND2 'l'
SEND2 'i'
SEND2 'n'
SEND2 'k'
SEND2 ' '
SEND2 '1'
SEND2 CR ; Carriage Return
SEND2 LF ; Line Feed
RETURN
ISR ;************************
;*** ISR CONTEXT SAVE ***
;************************
;**************************
;*** ISR MAIN EXECUTION ***
;**************************
; catch-all
goto ISRend ; unexpected IRQ, terminate execution of ISR
;***************************************
;*** SW-BASED RS232 DATA ACQUISITION ***
;***************************************
_ISR_RS232_SW
; first, disable interrupt source
bcf INTCON,INTE ; disable RB0/INT interrupt
; second, acquire RS232 data
RECEIVE ; macro of RS232 software reception
bsf RSflagSW ; enable RS232 data reception flag
goto _ISR_RS232end ; terminate RS232 ISR properly
;***********************************
;*** CLEARING OF INTERRUPT FLAGS ***
;***********************************
; NOTE: Below, I only clear the interrupt flags! This does not
; necessarily mean, that the interrupts are already re-enabled.
; Basically, interrupt re-enabling is carried out at the end of
; the corresponding service routine in normal operation mode.
; The flag responsible for the current ISR call has to be cleared
; to prevent recursive ISR calls. Other interrupt flags, activated
; during execution of this ISR, will immediately be served upon
; termination of the current ISR run.
_ISR_RS232error
bsf INTCON,INTE ; after error, re-enable IRQ already here
_ISR_RS232end
bcf INTCON,INTF ; clear RB0/INT interrupt flag
goto ISRend ; terminate execution of ISR
;***************************************
;*** HW-BASED RS232 DATA ACQUISITION ***
;***************************************
_ISR_RS232_HW
movfw RCREG ; get RS232 data (first RX FIFO entry)
movwf RXreg ; store first data byte
btfss PIR1,RCIF ; check flag for second RX FIFO entry
goto _ISR_RS232_HW_A ; no second byte received, branch
movfw RCREG ; get RS232 data (second RX FIFO entry)
movwf RXreg2 ; store second data byte
bsf RX2flag ; set flag to indicate second byte received
_ISR_RS232_HW_A
bsf RSflagHW ; enable RS232 data reception flag
BANK1 ; (for display routine)
bcf PIE1,RCIE ; disable USART reception interrupt
BANK0 ; (will be re-enabled in normal subroutine)
;goto _ISR_RS232end_HW ; exit ISR
_ISR_RS232end_HW
;bcf PIR1,RCIF ; cleared by hardware: USART RX interrupt flag
;goto ISRend ; terminate execution of ISR
;*****************************************
;*** ISR TERMINATION (CONTEXT RESTORE) ***
;*****************************************
MAIN
clrf INTCON ; reset interrupts (disable all)
LCDchar 'D'
LCDchar 'u'
LCDchar 'a'
LCDchar 'l'
LCDchar ' '
LCDchar 'R'
LCDchar 'S'
LCDchar '2'
LCDchar '3'
LCDchar '2'
LCDchar ' '
LCDchar 'R'
LCDchar 'e'
LCDchar 'c'
LCDchar 'e'
LCDchar 'p'
LCDline 0x2
LCDchar 't'
LCDchar 'i'
LCDchar 'o'
LCDchar 'n'
LCDchar ' '
LCDchar 'o'
LCDchar 'n'
LCDchar ' '
LCDchar 'P'
LCDchar 'I'
LCDchar 'C'
LCDchar '1'
LCDchar '6'
LCDchar 'F'
LCDchar '7'
LCDchar '7'
WAITX 0x1A, b'00000111' ; wait some time
LCDchar 'h'
LCD_DDAdr 0x49 ; goto specific LCD position
LCDchar 'V'
LCDchar 'a'
LCDchar 'l'
;******************************
_MLOOP ; first software-based RS232 link (no USART, just IRQs)
btfsc RSflagSW ; check RS232 data reception flag
call COUNTERinit ; reset 24 bit counter
btfsc RSflagSW ; check RS232 data reception flag
call RSservice ; if set, call RS232 echo & LCD display routine
WelcomeTable
addwf PCL,F ; add offset to table base pointer
retlw CR
retlw LF
DT "Dual RS232 Reception"
retlw CR
retlw LF
DT "===================="
retlw CR
retlw LF
DT "Microchip PIC16F77 connected and stand-by..." ; create table
retlw CR
WTableEND retlw LF
IF (HIGH (WelcomeTable) != HIGH (WTableEND))
ERROR "WelcomeTable hits page boundary!"
ENDIF
ReadyTable
addwf PCL,F ; add offset to table base pointer
DT "ready for transmission..." ; create table
retlw CR
RTableEND retlw LF
IF (HIGH (ReadyTable) != HIGH (RTableEND))
ERROR "ReadyTable hits page boundary!"
ENDIF
END
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PIC16F84 MAX232
D (Direction seen from controller) D
VDD
VDD
R1 XT1 VSS
C4
16k C3
4.000 MHz 10u
C1 C2 10u
S1 10p VDD 10p
16
2
6
SW-PB VSS VSS
14
U1
C5 13 12
V+
VCC
V-
IC_PIC1 RS232 TXD R1 IN R1 OUT PIC RXD
RS232 8 9 5V
16 15 RS232 DTR R2 IN R2 OUT 5V DTR
VDD
VSS 4n7 OSC1/CLKIN OSC2/CLKOUT 11 14
4 7 PIC TXD T1 IN T1 OUT RS232 RXD
MCLR RB1 5V 10 7 RS232
17 8 5V DSR T2 IN T2 OUT RS232 DSR
C PIC TXD RA0 RB2 1 4 C
GND
18 9 C1+ C2+
RA1 RB3 3 5
5V DSR 1 10 C1 - C2 -
RA2 RB4
2 11
RA3 RB5 C6 MAX232CPE(16) C7
5V DTR 3 12
RA4/T0CKI RB6 10u 10u
VSS
15
6 13
PIC RXD RB0/INT RB7
PIC16F84-04/P(18)
5
VSS
VDD
VDD VSS
VDD
C8
DSR and DTR signals are not used in
100n
B VSS RS232 my RS232 routines, but are drawn for
completion. These signals are necessary C9
B
VSS
(Direction seen from host) for hardware handshaking, whilst my 100n
routines perform no handshaking. The
RS232 DTR MAX232 has two output and two input VSS
RS232 TXD VSS channels, specified to transmit up to 120
kbps depending on the type used.
RS232 RXD
RS232 DSR
1
6
2
7
3
8
4
9
5
Title
PIC-RS232 Interface using MAX232
A A
Written by Date
SUB1 20-Aug-2003
Peter Luethi
DB9 Revision Page
Dietikon, Switzerland 1.01 1 of 1
1 2 3 4
ASCII Character Map
32 00100000 20 90 Z 01011010 5A
33 ! 00100001 21 91 [ 01011011 5B
34 " 00100010 22 92 \ 01011100 5C
35 # 00100011 23 93 ] 01011101 5D
36 $ 00100100 24 94 ^ 01011110 5E
37 % 00100101 25 95 _ 01011111 5F
38 & 00100110 26 96 ` 01100000 60
39 ' 00100111 27 97 a 01100001 61
40 ( 00101000 28 98 b 01100010 62
41 ) 00101001 29 99 c 01100011 63
42 * 00101010 2A 100 d 01100100 64
43 + 00101011 2B 101 e 01100101 65
44 , 00101100 2C 102 f 01100110 66
45 - 00101101 2D 103 g 01100111 67
46 . 00101110 2E 104 h 01101000 68
47 / 00101111 2F 105 i 01101001 69
48 0 00110000 30 106 j 01101010 6A
49 1 00110001 31 107 k 01101011 6B
50 2 00110010 32 108 l 01101100 6C
51 3 00110011 33 109 m 01101101 6D
52 4 00110100 34 110 n 01101110 6E
53 5 00110101 35 111 o 01101111 6F
54 6 00110110 36 112 p 01110000 70
55 7 00110111 37 113 q 01110001 71
56 8 00111000 38 114 r 01110010 72
57 9 00111001 39 115 s 01110011 73
58 : 00111010 3A 116 t 01110100 74
59 ; 00111011 3B 117 u 01110101 75
60 < 00111100 3C 118 v 01110110 76
61 = 00111101 3D 119 w 01110111 77
62 > 00111110 3E 120 x 01111000 78
63 ? 00111111 3F 121 y 01111001 79
64 @ 01000000 40 122 z 01111010 7A
65 A 01000001 41 123 { 01111011 7B
66 B 01000010 42 124 | 01111100 7C
67 C 01000011 43 125 } 01111101 7D
68 D 01000100 44 126 ~ 01111110 7E
69 E 01000101 45 127 01111111 7F
70 F 01000110 46 128 10000000 80
71 G 01000111 47 129 10000001 81
72 H 01001000 48 130 10000010 82
73 I 01001001 49 131 10000011 83
74 J 01001010 4A 132 10000100 84
75 K 01001011 4B 133 10000101 85
76 L 01001100 4C 134 10000110 86
77 M 01001101 4D 135 10000111 87
78 N 01001110 4E 136 10001000 88
79 O 01001111 4F 137 10001001 89
80 P 01010000 50 138 10001010 8A
81 Q 01010001 51 139 10001011 8B
82 R 01010010 52 140 10001100 8C
83 S 01010011 53 141 10001101 8D
84 T 01010100 54 142 10001110 8E
85 U 01010101 55 143 10001111 8F
86 V 01010110 56 144 10010000 90
87 W 01010111 57 145 10010001 91
88 X 01011000 58 146 10010010 92
89 Y 01011001 59 147 10010011 93
148 10010100 94 202 11001010 CA
149 10010101 95 203 11001011 CB
150 10010110 96 204 11001100 CC
151 10010111 97 205 11001101 CD
152 10011000 98 206 11001110 CE
153 10011001 99 207 11001111 CF
154 10011010 9A 208 11010000 D0
155 10011011 9B 209 11010001 D1
156 10011100 9C 210 11010010 D2
157 10011101 9D 211 11010011 D3
158 10011110 9E 212 11010100 D4
159 10011111 9F 213 11010101 D5
160 10100000 A0 214 11010110 D6
161 10100001 A1 215 11010111 D7
162 10100010 A2 216 11011000 D8
163 10100011 A3 217 11011001 D9
164 10100100 A4 218 11011010 DA
165 10100101 A5 219 11011011 DB
166 10100110 A6 220 11011100 DC
167 10100111 A7 221 11011101 DD
168 10101000 A8 222 11011110 DE
169 10101001 A9 223 11011111 DF
170 10101010 AA 224 11100000 E0
171 10101011 AB 225 11100001 E1
172 10101100 AC 226 11100010 E2
173 - 10101101 AD 227 11100011 E3
174 10101110 AE 228 11100100 E4
175 10101111 AF 229 11100101 E5
176 10110000 B0 230 11100110 E6
177 10110001 B1 231 11100111 E7
178 10110010 B2 232 11101000 E8
179 10110011 B3 233 11101001 E9
180 10110100 B4 234 11101010 EA
181 10110101 B5 235 11101011 EB
182 10110110 B6 236 11101100 EC
183 10110111 B7 237 11101101 ED
184 10111000 B8 238 11101110 EE
185 10111001 B9 239 11101111 EF
186 10111010 BA 240 11110000 F0
187 10111011 BB 241 11110001 F1
188 10111100 BC 242 11110010 F2
189 10111101 BD 243 11110011 F3
190 10111110 BE 244 11110100 F4
191 10111111 BF 245 11110101 F5
192 11000000 C0 246 11110110 F6
193 11000001 C1 247 11110111 F7
194 11000010 C2 248 11111000 F8
195 11000011 C3 249 11111001 F9
196 11000100 C4 250 11111010 FA
197 11000101 C5 251 11111011 FB
198 11000110 C6 252 11111100 FC
199 11000111 C7 253 11111101 FD
200 11001000 C8 254 11111110 FE
201 11001001 C9 255 11111111 FF