IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO.
10, OCTOBER 2015 5983
Performance of Three-Phase Asymmetric
Cascaded Bridge (16 : 4 : 1) Multilevel Inverter
Sumit K. Chattopadhyay, Student Member, IEEE, and Chandan Chakraborty, Fellow, IEEE
AbstractAvailability of more number of levels for the
same number of switching devices has made asymmetrical
topologies superior over symmetrical structures. While the
16 : 4 : 1 conguration is reported as an optimal asymmetry,
a detailed performance is not available in literature. This
paper presents the performance and control of the 16 : 4 : 1
asymmetrical topology. A new analytical approach is in-
troduced to nd the complete information of the available
combination of space vectors for any asymmetric ratio. A
limit chart is introduced, which represents the number of
ways to generate a particular space vector. Asymmetrical
hexagonal decomposition technique is used to select the
switching devices from the high-, medium-, and low-voltage
cells to realize a space vector. The converter is simulated
in MATLAB/Simulink. Supporting results from a laboratory
prototype have conrmed the usefulness of the 16:4:1
asymmetrical conguration.
Index TermsAsymmetric multilevel inverter, asymmet-
rical hexagonal decomposition, cascaded H-bridge, limit
chart, overmodulation, power quality, space vector modu-
lation technique.
I. I NTRODUCTION
O WING to nonavailability of high-voltage and high-power
switches, topological innovation, modulation techniques,
and exploration of new control strategies led to the development
of different viable multilevel converters (MLCs) [1][21]. The
whole idea is to use low- or medium-voltage devices to develop
converters that can process higher power at high voltage. MLCs
are presently used in many different applications such as mo-
tor drives, HVDC and FACTS, renewable-energy integration,
etc., [22][25]. Extensive investigations have unearthed many
topological variations such as diode clamped, flying capacitor,
cascaded H-bridge, and many hybrid versions [1], [2]. Of these,
the cascaded H-bridge MLC (CHBMLC) is one of the most
popular topologies due to its simple structure and easy control
requirement. Capacitor balancing is an important issue for most
of the other topologies [3], except for the hybrid topological
concept introduced in [4] and [5]. However, the proposed topol-
ogy in [5] will not be able to operate satisfactorily in nonunity
power factor, and device current stress will be excessively high.
Modular multilevel converter (MMC) was first introduced in
Manuscript received September 20, 2014; revised January 28, 2015
and March 9, 2015; accepted March 12, 2015. Date of publication
April 17, 2015; date of current version September 9, 2015.
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology Kharagpur, Kharagpur 721 302, India (e-mail:
sumitkc1981@gmail.com; chakraborty@ieee.org).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2015.2424191
0278-0046 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
[6]. This topology suffers from circulating current problem.
A complicated closed-loop control and arm inductance are
required to balance the submodule capacitors and to restrict the
circulating current. Moreover, a high-resolution MMC demands
a large number of power semiconductors. As a result, practical
use of high-resolution MMC is limited to high-voltage applica-
tions only. HVDC using MMC [7] is one of such examples.
CHBMLCs and their hybrid topologies can be developed
with asymmetric structure to increase the number of levels/
resolution of the output voltage. However, it demands different
bridges to handle different amounts of power. Therefore, var-
ious power sources are required to feed the cascaded bridges.
The power distribution ratio (PDR) of these different sources
are the highly nonlinear function of the modulation index as
shown in [8] for trinary voltage ratio. Auxiliary sources (i.e.,
sources with lower voltage) are usually fed by a higher voltage
source (through an efficient high-frequency link as presented
in [9] and [10]). About 19% of total power is handled by the
high-frequency link at near-unity modulation index for trinary
asymmetry. Power handling at high frequency is a major con-
tributor for losses in this converter. To reduce the contribution
of power of the high-frequency link, the converter topology is
operated in a fixed modulation index in [8], where the link will
be handling about 2% of the total power. This is achieved at the
cost of slightly reducing the number of levels (from 27 levels to
23 levels at phase voltage) and placing a buck converter be-
tween the dc power supply and the inverter. This forces the
buck converter to handle the entire input power (with corre-
sponding increase in switching losses), making such topology
suitable only for low-power applications. To solve these issues,
a complex algorithm following the nonlinear model predictive
controller is used in [11]. A reasonable common-mode voltage
is superposed in all phases, such that the lower voltage cells will
not contribute any active power. However, this is also at the ex-
pense of reduction in the number of levels and increasing con-
troller complexity. Such algorithms may not be possible for im-
plementation beyond trinary asymmetry in case of three-phase
CHBMLC [12]. The algorithms suggested in [11] and [12] may
become difficult to implement (due to huge computational load
for the processor to handle) for topologies having more than two
H-bridges cascaded per phase. Therefore, the number of levels
at the output phase voltage cannot exceed 9 (considering two
cascaded bridges per phase with trinary asymmetry) at any
condition. Hence, this will not be able to operate the inverter
in staircase modulation for a wide variation of the modulation
index. In literature, while 16 : 4 : 1 is described as the optimal
asymmetrical ratio [13], a detailed performance study for such
a configuration is not available. This investigation brings out
5984 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 10, OCTOBER 2015

Fig. 1. Location of unreachable levels of a CHBMLC with two cascaded

cells maintaining a voltage ratio a : b = r.

the merits and limitation of the topology for a wide range of

modulation index. A simple method to find the number of ways
to realize a space vector is reported. Asymmetrical hexagonal
decomposition technique is used to control such converter.
This paper is organized in seven sections. A general intro-
duction followed by a survey of different publications on high-
resolution multilevel topologies is presented in Section I. The Fig. 2. Space vectors of sector 1 for an N + 1 level inverter.
objective of this investigation is also clearly stated. Section II
provides a general framework to investigate different asymmet-
ric configurations for three-phase inverters. An analytical ap- where [SV ] is an upper triangular matrix. Any element inside
proach is proposed to explore the potential of a topology with a this matrix SVxy0 indicates the number of ways to generate a
given ratio of asymmetry. Section III deals with various perfor- space vector svxy0 ; x, and y will be within the range 0 to N for
mance indexes such as PDR, THD, etc., for 16 : 4 : 1 asymmetry. an N + 1 level in phase voltage. The SV matrix is given in (3).
The performance of the converter at different modulation The elements of the matrix [SV ] can be located in Fig. 2
indexes is investigated. Section IV presents the details of the al-
gorithm to implement asymmetrical hexagonal decomposition. SV000 SV110 SV(N 1)(N 1)0 SVN N 0
Sections V and VI illustrate the simulation and experimental SV100 SV210 SVN (N 1)0 0

results, respectively. Section VII concludes this paper. .. . .. . ..
[SV ] = . .. . .. .

SV(N 1)00 SVN 10 0 0
II. A SYMMETRIC R ATIO FOR T HREE -P HASE SVN 00 0 0 0
M ULTILEVEL I NVERTERS (3)
Most of the asymmetric cascaded H-bridge topologies re-
a0 a1 a(N 1) aN
ported in literature use binary (1 : 2 : : 2N ) or trinary (1 : a1 a a 0
3 : : 3N ) ratio for the dc buses of the cascaded bridges. If 2 N
.. . . . ..
[A] = . .. .. .. . (4)
the ratio of asymmetry goes beyond trinary, the converter will
not be able to generate few levels in between its maximum and a(N 1) aN 0 0
minimum output voltages. This is given as aN 0 0 0
 m 
r 1 b0 0 0 0
Lu = 2 3m + 1 (1) 0 b1 0 0
r1
.. . .. . ..
[B] = . .. . .. . (5)

where Lu is the number of unachievable levels and m is the 0 0 b(N 1) 0
number of H-bridges cascaded with a ratio of asymmetry r. 0 0 0 bN
This is illustrated in Fig. 1 with two cascaded cells maintaining
a ratio of asymmetry given by r. c0 0 0 0
If a three-phase MLC is considered, many of the space c1 c0 0 0

vectors can be generated by several alternate ways. This is .. .. .. .. .. .
[C] = . . . . . (6)
possible by adding a common-mode voltage to each phase. The
c(N 1) c(N 2) c0 0
number of alternative ways to generate a space vector is reduced
cN c(N 1) c1 c0
if r is increased.
If the ratio r is increased beyond 4, then there will be
unachievable space vectors at the inner space and also at the In (4)(6), any element in these matrices ax , bx , or cx indi-
periphery in the space vector plane. The following matrix equa- cates the number of ways to generate the xth level for phases
tion helps in analyzing the number of possible ways to form a A, B, and C, respectively, where the zeroth level corresponds to
space vector in sector 1 with a given asymmetric structure. Due the minimum (i.e., negative maximum) phase voltage and the
to symmetry in the space vector plane, this will also be valid for N th level corresponds to the positive maximum voltage. Since
other sectors all phases are identical

[SV ] = [A][B][C] (2) ax = b x = cx . (7)

CHATTOPADHYAY AND CHAKRABORTY: ASYMMETRIC CASCADED BRIDGE (16:4:1) MULTILEVEL INVERTER 5985

Fig. 4. Circuit diagram of the asymmetric CHBMLI considered for

the work.

Fig. 3. Level-tree of various asymmetric multilevel inverter structures

(two bridges cascaded) to find the coefficients a0 to aN shown in (4). Therefore

[SV ] = [A][B]c0 + [A][B][C1]. (10)

Note that ax , bx , and cx will differ if the bridges in all phases
are not identical, e.g., on the occurrence of fault condition. Now, Fig. 4 shows the asymmetric CHBMLC topology with three
these sets of equations may be used to analyze the feasibility of H-bridges per phase with VH : VM : VL = 16 : 4 : 1 explored
any given asymmetry. Fig. 3 shows the level-tree to find the in this paper. The corresponding matrix [SV ] may be found
coefficients a0 to aN for A-phase. A similar level-tree can also by putting the coefficients a0 a42 , b0 b42 , and c0 c42 in
be drawn for phases B and C to find the coefficients b0 to bN (2). The level-tree in Fig. 5 may be used to find the coefficients
and c0 to cN . a0 a4 2. Note that (7) holds as the three phases are identical.
A given space vector is generated by combination of three Fig. 6 shows a limit chart, which is a pictorial representation
phase voltages for a three-phase system. Therefore, redundancy of the available zone of operation for the asymmetrical MLC
to achieve a space vector is obtained either because of having corresponding to the topology in Fig. 4. Each point in this
redundancy to achieve a given voltage level (i.e., ax , bx , or chart indicates the number of ways to generate space vectors
cx > 1) or by adding an equal voltage (i.e., common-mode in sector 1. Therefore, this is a plot of different coefficients
voltage) to all phases. Therefore, the total redundancy of the of the matrix SV in a 2-D plane. This is an alternative to the
available space vectors is caused by redundancy due to available approach presented in [13][15] and is convenient for the three-
voltage levels and redundancy due to application of common- phase MLC with a high number of levels.
mode voltages.
Now, redundancy due to available voltage levels may be III. PDR AND THD FOR THE T HREE -P HASE
expressed as A SYMMETRIC CHBMLC
[A][B]c0 PDR: The ratio of power delivered/absorbed by the dc

a0 b 0 c0 a1 b 1 c0 a(N 1) b(N 1) c0 aN bN c0 busses of different bridges of an asymmetric CHBMLC is
a1 b 0 c0 a2 b 1 c0 aN b(N 1) c0 0 a highly nonlinear function of the modulation index, ratio

. .. .. .. .. of asymmetry, and number of cascaded bridges. This study
= .. . . . .
restricts the computation of PDR with three cascaded bridges
a(N 1) b0 c0 aN b1 c0 0 0 per phase. It is assumed that the rated current may flow at any
aN b 0 c0 0 0 0 modulation index. Therefore, the power handled by the inverter
(8) at any modulation index (ma ) is
and redundancy due to application of common-mode voltages Pout = Vrated Irated ma Power Factor. (11)
may be derived as
Considering unity power factor load (as the corresponding
[A][B][C1] power output will be maximum), the total power handled by
all auxiliary bridges (i.e., bridges with lower voltages) as a
where percentage of rated power (Pout ) can be found by summing

0 0 0 0 the absolute value of PDR as reported in [16]. Fig. 7 shows a
c1 0 0 0 plot of PDR for different modulation indexes. This will remain

.. .. .. .. .. . valid for any other power factor, as the PDR is independent of
[C1] = . . . . . (9)
the power factor [17]. The power handled by auxiliary sources
c(N 1) c(N 2) 0 0 with various asymmetry and modulation strategy is compared
cN c(N 1) c1 0 in Fig. 8.
5986 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 10, OCTOBER 2015
Fig. 5. Level-tree to find the coefficients a0 a42 for 16 : 4 : 1 ratio.
Fig. 6. Limit chart (ways to generate space vectors) of sector 1 for the
three-phase asymmetric CHBMLC with three H-bridges per phase with
16 : 4 : 1 ratio. The legend indicates the number of ways to generate a
space vector.
Fig. 7. Power handled by auxiliary sources of 16 : 4 : 1 asymmetry and
corresponding PDR of medium- and low-voltage cells as a percentage
of rated power.
Binary asymmetry is not considered as it has to handle in-
creased amount of power by the low-voltage bridges, while the
objective here is to minimize the same. Also, binary asymmetry
will have much lower number of levels compared to trinary
and quaternary asymmetries. In Fig. 8, it is shown that the
auxiliary bridges will handle much lower power compared
to trinary (with and without third harmonic injection). It is
Fig. 8. Power handled by auxiliary bridges at different modulation
indexes as a percentage of rated power for trinary and proposed
asymmetry.
Fig. 9. Space vectors generated by three-phase CHBMLC with 16 : 4 : 1
asymmetry are shown in the plane. Indicating the space vectors
corresponding to various levels in the line-to-line voltage.
important to note that the effective number of levels in the
line-to-line voltage corresponding to unity modulation index
is 77. However, up to 85 levels can be obtained by overmod-
ulation. This is illustrated in Fig. 9. The power handled by
auxiliary sources will be reduced if the converter is operated
at the overmodulation region (from 77 levels to 85 levels)
with a maximum value of ma (= 1.1). This will also increase
the range of modulation index for which staircase modulation
will be possible without a significant distortion in the output
voltage. It may be noted in Fig. 9 that, due to unachievable
space vectors in periphery, the space vectors corresponding to
85 levels (overmodulation) do not make an accurate circle (i.e.,
having discontinuities in the locus).
CHATTOPADHYAY AND CHAKRABORTY: ASYMMETRIC CASCADED BRIDGE (16:4:1) MULTILEVEL INVERTER
Fig. 10. Voltage output (line-to-line) versus modulation index for
16 : 4 : 1 (quaternary) and 9 : 3 : 1 (trinary) asymmetries.
Fig. 11. Comparison of %THD of the line-to-line voltage waveforms for
the 16 : 4 : 1 asymmetry and trinary asymmetry using different modula-
tion strategies.
Fig. 12. Harmonic components of the voltage waveform for the pro-
posed asymmetry as a percentage of fundamental (up to 65th-order
harmonics) for a modulation index range of 0.21.
Fig. 10 compares the relation between the rms of the fun-
damental component of the output voltage and the modulation
index. It can be clearly observed that the linearity will be lost
for a trinary ratio beyond ma = 1, while the same is maintained
for 16 : 4 : 1 asymmetry up to ma = 1.1.
THD and Harmonic Spectra: Fig. 11 shows the variation
of THD for different modulation indexes for different convert-
ers. The effect of unachievable space vectors on power quality
can now be observed. Even at low THD, the existence of low-
frequency harmonic components may demand larger power
j , and U
0 , U
k will be
filters. Considering this, up to 65th-order harmonic components
are plotted as a percentage of fundamental for a modulation
index range of 0.221.1 as shown in Fig. 12. In the modulation
z (z ranges from 0 to 6). Based on this logic,
index range 0.31, most of the harmonic components are less
5987
Fig. 13. Logic for selecting the nearest space vector for a two-level
inverter.
TABLE I
C ONDITIONS FOR N EAREST V ECTOR S ELECTION
FOR A T WO -L EVEL I NVERTER
than 1% of fundamental. This confirms low filtering require-
ments.
IV. N EAREST S PACE V ECTOR S ELECTION U SING
A SYMMETRIC H EXAGONAL D ECOMPOSITION
The simplest method of staircase modulation (nearest level
control) has a serious limitation for the asymmetrical ratio un-
der investigation. This requires injection of a variable common-
mode voltage to skip the unachievable levels in phase voltage.
This not only complicates the modulation technique but also
affects PDR. In literature, hexagonal decomposition technique
is reported for three-level inverters [19]. Fast schemes based
on repeated use of two-level space vector modulation are
also reported [20], [21]. An alternative scheme for the asym-
metric converter topologies using hexagonal decomposition is
reported here.
Fig. 13 illustrates the logic for selecting the nearest space
vector for a two-level inverter. In this figure, the centroid of any
equilateral triangle formed by vectors U
the common point of zone 0, j and k, where j and k range from
1 to 6 and j = k. Any vector lying in zone z will be nearest
to the vector U
conditions are listed in Table I to identify the zone, at which
5988 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 10, OCTOBER 2015

Fig. 14. Space vectors of a three-level (five levels in line-to-line voltage)

inverter observed as seven hexagons of a two-level inverter.

a given vector V 
= V + jV exists. For example, V will
belong to zone 1 in Fig. 13 if the following three equations 
Fig. 15. Method to converge toward the nearest space vector of V
by asymmetric hexagonal decomposition.
are simultaneously satisfied (resulting in the selection of space

1 ):
vector U
1
V > U (12)
2
1
V V (13)
3
1
V V . (14)
3
Similarly, the equations for other vectors can also be found
from Table I. The variable U is a scalar quantity and indicates
the distance between two adjacent space vectors of a two-level
inverter. The conditions in Table I are derived by considering
the equations of nine straight lines dividing the seven zones
(zone 0 to zone 6) as shown in Fig. 13.

z , the difference between V
After locating U

and Uz is
found as

V
 

= V Uz . (15)

Now, V  

can be replaced by V with its origin shifted to Uz .

The space vectors for a three-phase three-level inverter can
be decomposed into seven hexagons of the two-level three-
phase inverter as shown in Fig. 14 (H0H6 as shown in this

z found in the first iteration is lying on the hexagon
figure). U
Fig. 16. Comparison between nearest space vector modulation and
drawn by using a continuous bold line in Fig. 14. The nearest nearest level control. (a) Line-to-line voltage and corresponding phase
space vector corresponding to V 
z by
can again be found as U voltage achieved by nearest space vector modulation. (b) Line-to-line
using the conditions provided in Table I. voltage and corresponding phase voltage obtained by nearest level
control.
Therefore, the nearest space vector location for V will be

=U
U
z + U

 .
z (16) V . Following the same approach, the vector generated by
medium-voltage cells M
will be found. This process will be
A coarse convergence to the reference vector is made by continued further until it reaches the lowest voltage cells.
higher voltage cells, while a finer convergence is made by lower From the aforementioned discussion, it may be noted that
voltage cells. Table I will be applicable to both coarse conver- the requirement of computational/logical resource for imple-
gence and fine convergence. The value of U will be changed menting such modulation technique depends on the number of
accordingly. Fig. 15 illustrates the convergence process. Here, cascaded bridges per phase and not on the type of asymmetry.
an arbitrary vector V is considered as reference.
 is found. Note that U
Initially, H  in Table I is replaced by
 in V. S IMULATION R ESULTS AND D ISCUSSION
the dc bus voltage of the highest voltage bridges, i.e., H
 The reference for the medium-
Fig. 15. Therefore, (16) gives H. The usefulness of the 16 : 4 : 1 configuration is exam-
voltage cell is obtained by subtracting H  from the reference ined through simulation using MATLAB/Simulink. First, a
CHATTOPADHYAY AND CHAKRABORTY: ASYMMETRIC CASCADED BRIDGE (16:4:1) MULTILEVEL INVERTER
Fig. 17. Line-to-line voltage VA B and corresponding phase voltages
VA and VB for 16:4:1 asymmetry at different modulation indexes (oper-
ating at staircase modulation). (a) Modulation index of 1.1 (85 levels in
line-to-line voltage). (b) Modulation index of 0.66 (51 levels in line-to-line
voltage). (c) Modulation index of 0.22 (17 levels in line-to-line voltage).
comparison between the performances of asymmetrical hexag-
onal decomposition and nearest level control is presented.
Fig. 16 shows the line voltages and corresponding phase volt-
ages for unity modulation index (i.e., 77 levels in line voltage
for the three-phase converter shown in Fig. 4). The voltage
levels are considered as VH = 160 V, VM = 40 V, and VL =
10 V. The asymmetrical hexagonal decomposition detailed in
the previous section is implemented, and the corresponding
line and phase voltages using this technique are available in
Fig. 16(a). The modulation strategy using nearest level control
is also implemented, and Fig. 16(b) represents the correspond-
ing waveforms. In nearest level control, even if the numbers
of levels are the same, the line-to-line voltage waveform is
significantly inferior. This is due to unreachable levels in phase
voltages that cause prominent step-jump in line-to-line and
phase voltages. This also reduces the effective number of levels
in the line-to-line voltage waveform.
Fig. 17 shows the line-to-line voltage and corresponding
phase voltage (at different modulation indexes). Starting with
overmodulation (ma = 1.1) in Fig. 17(a), 85-level line-to-line
voltage is observed. It is important to note that there is a level-
jump in a regular interval of nearly 30 . This can be understood
by interpreting the space vectors corresponding to this converter
drawn in Fig. 9. The space vectors corresponding to 85 levels
(ma = 1.1) are having a large distance with an equal interval.
This is due to the unachievable space vectors at the periphery,
causing a level-jump in the line-to-line voltage. When the
5989
Fig. 18. Modulation index dependence of the switching frequency of
various power switches located at different H-bridges as a multiple of
fundamental frequency.
modulation index is reduced to unity, the corresponding circle
does not pass through the unachievable zone. Therefore, there
is no level-jump observed in the corresponding line voltage as
shown in Fig. 16(a).
Numbers of levels are reduced to 17 at a modulation index of
0.22 as shown in Fig. 17(c). The line-to-line voltage and corre-
sponding phase voltages for a modulation index of 0.66 (which
is half way in the range of 0.221.1, where staircase modulation
will be possible) are shown in Fig. 17(b). The effectiveness of
the asymmetrical hexagonal decomposition technique is clearly
demonstrated in Fig. 17. Note that there is always a level-jump
in phase voltage even if there is no level-jump observed in line
voltage. This is because the unachievable levels in the phase
voltage are skipped by the modulation technique by adding a
common-mode voltage to phase voltages. The corresponding
harmonic components may be observed in Fig. 12.
It may be noted that the phase voltage retains half-wave sym-
metry without any dc-offset. Unlike conventional pulsewidth
modulation with fixed frequency, the nearest space vector selec-
tion technique automatically changes the switching frequency
depending on the modulation index as shown in Fig. 18. The
highest voltage cell switches either at fundamental or close
to fundamental under all circumstance. As per expectation,
the lowest voltage cell switches at the maximum frequency.
Fig. 18 shows the switching frequencies for all of the three cells
in the entire operating range.
VI. E XPERIMENTAL R ESULTS
The experimental results are obtained using a scaled-
down laboratory prototype. The controller is implemented
using dSPACE1103. Fig. 19 shows the experimental setup.
Table II lists all of the major parameters. An induction motor
with a 190-V line-to-line voltage at 50 Hz (Marathon Electric
make) is used as load. Fig. 20 shows the line-to-line voltages
and corresponding phase voltages obtained for various mod-
ulation indexes. The following points may be noted in these
waveforms.
1) The line voltage is having level-jumps when the inverter
is operating at a modulation index of 1.1. This matches
well with the theory and simulation results shown in the
previous section.
5990 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 10, OCTOBER 2015

Fig. 19. Photograph of the experimental setup.

TABLE II
H ARDWARE S ETUP D ETAILS

Fig. 20. Line-to-line voltage and corresponding phase voltage for a

given asymmetry at different modulation indexes (operating at staircase
modulation). The modulation index and axis scales are indicated on the
waveform.

2) The phase voltages are skipping the unachievable levels,

but it does not affect the line-to-line voltage.
3) The switching delays during level transition are associ-
ated with small voltage spikes; those may be noted in the
expanded voltage waveform.
The voltage THD of this line voltage matches (with less than
5% difference) the THD calculated from the harmonic spectra
(limited to 65th order of harmonics only) shown in Fig. 12.
Fig. 21 is clearly indicating the level-jumps, as the rotating
vector is passing through zones with unachievable space vectors
at the periphery, as shown in Fig. 9. It is important to note Fig. 21. Line-to-line voltage during its transition from minima to maxima
that there are 12 unachievable space vector zones observed at overmodulation (ma = 1.1).
in Fig. 9, Fig. 21 also shows six step-jumps in a duration
of half time period. Fig. 22 shows the phase voltage and from reducing switching loss, a higher resolution in output
the voltages generated by high-, medium-, and low-voltage voltage (with staircase modulation) will also reduce the filter
H-bridges at different modulation indexes. PDR is measured for size, weight, and specific core loss compared to PWM [26].
different modulation indexes using the waveforms in Fig. 22, Fig. 23 illustrates the motor current for a very fast change
and it matches well with Fig. 8 (within 7% tolerance). Apart of speed reference using open-loop V /f control. The speed
CHATTOPADHYAY AND CHAKRABORTY: ASYMMETRIC CASCADED BRIDGE (16:4:1) MULTILEVEL INVERTER 5991

Fig. 23. Performance of an induction motor when fed from the con-
verter using V /f control. Top waveforms: three line-to-line voltages,
100 V/div. Bottom waveform: line current, 5 A/div.

PDR is a very important index for such topologies as it decides

the rating of the individual converters that are cascaded. The
PDRs for different modulation indexes are reported.
The availability of more levels of line-to-line voltages
(85 levels at a modulation index of 1.1 and 17 levels at a
modulation index of 0.22) has allowed the converter to operate
in an extended zone with staircase modulation technique. This
enables the converter bridges to operate at a reduced frequency
with corresponding reduced losses. This paper has shown that
the topology is useful to operate in the range of modulation
index from 0.31.1 with a voltage THD of less than 4%.
Linearity maintains for the modulation index up to 1.1. The
converter is simulated in MATLAB/Simulink, and an experi-
mental prototype is made in the laboratory using dSPACE1103.
The experimental results match well with the corresponding
simulation results, confirming the usefulness of 16:4:1 topolog-
Fig. 22. Phase voltage as a sum of high-, medium-, and low-voltage
ical variation.
cells at different modulation indexes. For all cases, the top (channel 1)
is the phase voltage waveform, second from the top (channel 2) is the R EFERENCES
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Sumit K. Chattopadhyay (S11) received the
B.E. degree in electrical engineering from
Burdwan University, Burdwan, India, in 2004
and the M.Tech. degree in industrial electrical
systems from the National Institute of Technol-
ogy Durgapur, Durgapur, India, in 2006.
From September 2006 to January 2010, he
was a Design Engineer of power electronic
system design with Larsen & Toubro Ltd., Navi
Mumbai, India, where he was responsible for
power electronic system design of multiple in-
dustrial and mission-critical naval projects executed for the first time
in India with foreign collaboration. From January 2010 to March 2015,
he was a full-time Research Scholar with the Department of Electri-
cal Engineering, Indian Institute of Technology Kharagpur, Kharagpur,
India. In March 2015, he joined ABB Global Industries Service Ltd.,
Chennai, India. His broad area of research includes multilevel converter
topologies, modulation, and control. His research interests also include
converter topologies, machine drives, FPGA-based embedded system
design, economic utilization of upcoming power electronic devices, and
power electronic converters.
Chandan Chakraborty (S92M97SM01
F15) received the B.E. and M.E. degrees in
electrical engineering from Jadavpur University,
Jadavpur, India, in 1987 and 1989, respectively,
and Ph.D. degrees from the Indian Institute of
Technology Kharagpur, Kharagpur, India, and
Mie University, Tsu, Japan, in 1997 and 2000,
respectively.
He is currently a Professor with the Depart-
ment of Electrical Engineering, Indian Institute
of Technology Kharagpur. His research interests
include power converters, motor drives, electric vehicles, and renewable
energy.
Dr. Chakraborty is a Fellow of the Indian National Academy of
Engineering. He was awarded the JSPS Fellowship to work at the
University of Tokyo in 20002002. He received the Bimal Bose Award
in power electronics from the IETE (India) in 2006. He has regularly
contributed to IEEE Industrial Electronics Society (IES) conferences
such as IECON, ISIE, and ICIT as technical program chair/track chair.
He is an AdCom member of the IES. He is one of the Associate
Editors of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS
and IEEE Industrial Electronics Magazine and an Editor of the IEEE
T RANSACTIONS ON S USTAINABLE E NERGY. He is the Founding Editor-
in-Chief of IE Technology News (ITeN), a Web-only publication for
the IES.