2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)

High Speed LVDS Driver for SERDES

Hari Shanker Gupta, RM Parmar and RK Dave
SPACE APPLICATIONS CENTRE, ISRO, JODHPUR TEKRA (P.O), AHMEDABAD-380015
E-mail: hari@sac.isro.gov.in, rmparmar@sac.isro.gov.in, rkdave@sac.isro.gov.in

critical when used with SERDES for high transmission rate.

Abstract: - Low Voltage Differential Signaling (LVDS) is a
method used for high-speed transmission of binary data over
copper cable. In the earlier remote sensing payload camera
electronics, the multi-port parallel data were provided to
spacecraft base-band system, requiring large number of I/O
connectors and associated harnesses. This multi-port parallel
data can be multiplexed, serialized and transmitted to other
subsystems using LVDS interface thereby reducing the number
of I/Os, cabling and associated weight of interface hardware. This
work presents the design, simulation and analysis of I/O interface
circuits for high speed operation which is fully compliant with the
IEEE STD 1596.3 (LVDS). A common mode feedback (CMFB)
circuitry is utilized in the LVDS transmitter to stabilize the
common mode voltage in a pre-defined range. In most of the
previous designs [1] output cells utilize voltage divider circuit
composed of two large resistors (M) between output pads and
center is taped as feedback. These resistors may be off-chip
discrete components (due to stringent stability and large die area
requirement). The modified common mode feedback circuit has
been designed and analyzed with appropriate transistor
geometry and evaluated. Its performance is also compared with
LVDS has become an attractive alternative as a standalone
driver or as I/O pad for high-speed devices like SerDes. The
low power and low voltage operation are the added
advantages. A modified LVDS driver design technique is
proposed and its performance is compared with the
conventional type in the following sections. It is envisaged
that LVDS driver would be low power and high speed (400
Mbps) device based on 0.8 CMOS technology and shall also
be fully compatible to IEEE STD 1596.3-1996[3]. Sections 2
and 3 respectively discuss LVDS driver topologies and typical
design along with the issues related to achieving required
performance. The expected performance and conclusions are
addressed in the last section.
VDD
D D

100
conventional CMFB design. Out

Receive
Vob Voa
Keywords: LVDS, CMFB, CMOS, IEEE STD 1596.3-1996,
D

r
D
1. INTRODUCTION:
Driver
Typical Low-Voltage Differential Signaling (LVDS)
Interface shown in Fig-1.1 consists of a current source VSS
(nominal 3.5 mA), which drives the differential lines Fig 1.1: Typical LVDS Interface
terminated with 100 load. The LVDS receivers have high 2. LVDS DRIVERS TOPOLOGIES:
input impedance and the drive current mainly flows through Table-1: Comparisons of LVDS driver topologies
the terminating resistor generating about 350 mV across the Topology Bridge Double current Switchable

receiver inputs. When the driver switches, it changes the Parameter Driver source current source
direction of current flow through the resistor, thereby creating Static power Low High Low
a valid one or zero logic state. Control on O/P More Less Less
The Serializer De-serializer devices popularly known as
LV Operation No Yes Yes
SerDes are used for high speed data transmission. They utilize
LVDS interface leading to lower power, better noise immunity Size Small Large Small
and reliable clock recovery. They also exhibit large bandwidth I/P Capacitance Small Large Small
for high speed data transmission. Circuit complexity low low high
A bottleneck in the digital transmission of signals via
Buffer requirement No No Yes
long wire is the I/O cells, which have to drive load at the
required rate, meeting the stringent voltage levels as per Speed High Low Low
applicable standards throughout the operating temperature
range. The I/O cells/pads are designed to supply sufficient The merits and demerits of popular LVDS driver topologies
current to drive load which results in large pad size and higher viz. Bridge driver, double current source and Switchable
power restricting the speed of operation, at larger loads. current source are compared in Table-1.
Most of the conventional CMOS I/O cells utilized very
large area to accommodate large driving transistors and
associated large passive elements [2]. This becomes more

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VOLTAGE V 1 25
However, the large value resistors demand large die area or
REFERENCE
TTL CMOS V 1.00 use of off-chip discrete components. The proposed driver
LEVEL LEVEL
Q D Dout
circuit uses a modified common mode feedback (CMFB)

DRIVER
BUFF
LEVEL
SHIFTE
PHASE
SPLITTE
(+) circuit scheme to resolve this problem. The CMFB
R R Q
BUFF
D
Dout (-
)
implemented in [4] for maintaining stable common mode
5.00
voltage of differential amplifier is employed in the proposed
2.40
LVDS design. The modified CMFB circuit does not require
Q D Dout(
1.42
high value resistors. Also, it occupies lesser area and has
1.08
minimum parasitics in the feedback circuit, thereby improving
0.00
the speed of operation and reduction in silicon area.
< 300 ps <200 < 500 ps < 1 ns Additionally this arrangement can be made less sensitive to
< 2 ns
temperature and process variations. The functional diagram of
Fig 2.1: Detailed block diagram of LVDS Driver
the modified CMFB concept is given in Fig-3.2.
Most of the constituent blocks of LVDS such as Level
Here M7 to M10 are matched transistors. The source
shifter, voltage reference, current sources feedback network
coupled pairs M7-M8 and M9-M10, together sense the common
and the buffer circuits and the differential driver are mixed
mode output voltage. Feedback proportional to the difference
signal designs. Fig- 2.1 shows detailed block diagram of a
between common mode voltage and VOCM is appropriately fed
typical LVDS device.
back to generate stable common mode voltage.
In order to have stable common mode and differential
output voltage over the entire temperature range from -55oC
to 125oC for space use, the design of current sources, type of Ia (V VOCM ) ------------ (3.2)
Id 8 = + gm8 * oa
feedback and temperature compensation are required to be 2 2
critically addressed. Bridge type topology uses less external
components, has precision feedback loop control and small Ia (V VOCM )
input capacitances. It meets all our requirements and hence is
Id10 = + gm10 * ob ----- (3.3)
2 2
discussed further. Where Id8, Id10 are drain currents and gm8, gm10 are
3. LVDS DRIVER CIRCUIT DESIGN: transconductance of M8 and M10 transistors respectively as
The bridge type LVDS driver circuit shown in Fig-3.1 shown in Fig-3.2. These currents are summed in diode
behaves as a current source with switched polarity. The connected current source I, to give common mode sensor
current switch constituted by M1, M2, M3, and M4 is output current. At steady state I, reach the current Ia when the
controlled by D and D. The transmitter output Vob and Voa are common mode voltage approaches VOCM.
the outputs coupled to the transmission lines. When D = 1,
M2 and M3 are turned on, while M1 and M4 are turned off.
V + V ob ----- (3.4)
Thus, Vob is pulled high and Voa is pulled down to LOW. In I = Ia + gm 10 * oa V OCM
2
other case, when D = 0, M2 and M3 are turned off, while M1
and M4 are turned on. Thus, Vob is pull-down, Voa is pulled
high, generating logic 1 and logic 0 conditions. VDD VDD VDD VDD
A stable common mode voltage (VOCM) is required as per I
LVDS standards [3]. To meet this requirement, a voltage
divider composed of two large value resistors between Vob and
VOCM
Voa is generally used. The reason for the large value resistors, D D Voa Vob
Ra and Rb is to minimize quiescent currents though feedback. Vob Voa M7 M8 M10 M9

(Voa + Vob ) D
VOCM = ------- (3.1) D
VDD 2
(5/3.3
Ia
Volt) V Ia
M U M10 M7
M8
IB
D
M1 M2
D Fig-3.2: Modified CMFB Approach for LVDS Driver
VOC
M5 M6
V Vob M

Ra Rb Transistorized circuit simulated is shown in Fig-3.3. The

M3 M4 operation of the feedback loop is as follows. As soon as Voa
D D I and Vob drops to cause common mode voltage to be smaller
ML than VOCM, the current via M8 and M10 are reduced which in
IB M9 VSS turn decreases the source current of LVDS driver pair, causing
VSS common mode voltage to increase. Similarly, when Voa and
VSS VSS
Vob increases to cause common mode voltage to be higher than
Fig- 3.1: Bridge driver circuit

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 2009 International Conference on Emerging Trends in Electronic and Photonic Devices & Systems (ELECTRO-2009)

VOCM, the current via M8 and M10 is increased, which in turn All the parameters are met with worst case conditions such
increases the source current of LVDS driver pair. as VDD (nominal 10%), total Mil temperature range and all
process corners. The proposed option though consumes
VDD (5/3.3 Volt) VDD(5/3.3
V l)
slightly more power compared to that of conventional design
M11 M M [1], but it offers significant advantages like 40% less area and
IB D
20-30% higher speed.
D D
I The eye opening of serial data at maximum rate (800
M1 M2
Vob Voa
VOCM Mbps) is reasonably good with horizontal eye opening more
Voa M10
Vob
than 0.95UI and vertical opening meeting LVDS threshold
D D M7 M8 M9
M3 M4
limits. The same driver core will be used for SERDES design
M12 M13 M14 planned for future mixed signal ASIC.
ML Vbias
Vbias
IB VDD = 5.0 V, VIN = TTL Clock,
VSS VSS Load = 100 ,, CL =5 pF

Fig-3.3: LVDS driver with Modified CMFB circuit

The targeted process of the proposed design is 0.8

CMOS with 5V operation. The VOCM is to be derived from
VREF along with other biases. As the feedback is in the form of 240 mV

UI = 0.95
current, suitable current gain of 20 is chosen to mirror 3.5 mA
driver current and accordingly current through the feed back
circuit is fixed as 172.5A for minimum power dissipation.
The geometry of all the transistors in the driver has been
computed based on following relations and listed in Table-2.
1. (W/L)Mu = f ( IB, A)
2. (W/L)ML = f ( IB, A) Time (ns) Vert : 40mV / Div
Hor : 0.1 nS/Div
3. (W/L)M1 = (W/L)M2 = f ( IB, fall time)
4. (W/L)M3 = (W/L)M4 = f ( IB, rise time)
Fig-4.1: EYE Pattern of Output Data
5. (W/L)M5 = (W/L)M6 = f ( I, A,)
6. (W/L)M7,M8,M9,M10 = f ( I, A)
7. (W/L)M11,M12,M13,M14 = f ( I)
Where A = is Current gain for mirroring, and IB is driver
current.
VDD = 5.0 V VIN = TTL Clock,
Load = 100 , CL =5 pF
Table 2: Transistor dimensions of driver Circuit
Length (m) Width (m)
Transistor (W/L) ratio
(L) (W)
MU 112.1 3.2 358.7 Vin
ML 69.9 3.2 223.7
Vob
M1,M2 461.1 0.8 368.9
Voltage Level

M3, M4 528 0.8 422.4 Voa

M5,M6,M11 5.6 3.2 17.9
M7, M8,M9,M10 182 3.2 581.8
M12 3.5 3.2 11.2
M13,M14 5.6 3.2 17.9 Vdiff

Vert : 1V/Div
4. RESULTS AND DISCUSSION: Time (ns) Hor : 20nS/Div
Based on the targeted goals, geometries are computed for
all the transistors and circuit design and simulations are
Figt-4.2: LVDS Outputs Voltage @ 20 Mbps
carried out. Optimization is also carried out after studying the
sensitivities. Circuit is characterized with load RL = 100 and
CL = 5 pF and the results are shown in figures 4.1 to 4.4. With
the recommended load, the performance is satisfactory up to
650 Mbps data rate and with higher capacitive load of around
15 pF, it meets required specs up to 450 Mbps data rate.

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16

14
Power Supply Current Vs Frequency
Power Supply Current (mA)

12

10

0
1.E+03 1.E+05 1.E+06 1.E+07 3.E+07 5.E+07 1.E+08 2.E+08 4.E+08
Frequency (Hz)

Fig 4.3: Current Vs Device Operating Frequency

1.285
Sensitivity Of VOCM
1.28
Common mode O/P (VOCM )

1.275

1.27

1.265

1.26

1.255

1.25

1.245

1.24

1.235
-100 -50 0 50 100 150
Temp(oC)

Fig-4.4: O/P common mode voltage with temperature

5. ACKNOWLEDGEMENT

The authors acknowledge the constant encouragement and

guidance received from Shri DRM Samudraiah, Deputy
Director, SEDA, Shri AS Kiran Kumar Associate Director,
Space Applications Centre, and Dr. R.R. Navalgund, Director,
Space Applications Centre. The authors also wish to thank Mr.
Sanjeev Metha for fruitful discussions on design, analysis
aspects and Mr. Nilesh Desai for providing valued suggestions
on manuscript.

6. REFERENCES:

[1] A. Boni, A. Pierazzi, and D. Vecchi, LVDS 1/0 interface for

Gb/s-per-pin operation in 0.35-pm CMOS,IEEE J. of Solid-
State Circuits, vol. 36, no. 4, pp. 706-711, Apr - 2001.
[2] Mingdeng Chen, Jose Silva-Martinez, Michael Nix and Moises
E. Robinson, Low- Voltage Low-Power LVDS Drivers IEEE
J. Solid State Circuits, Vol. 40, no. 2 pp. 472-479, Feb - 2005.
[3] IEEE Standard for Low-Voltage Differential Signals
(LVDS) for Scalable Coherent Interface (SCI), 1596.3
SCI-LVDS Standard, IEEE Std. 1596.3-1996, 1994.
[4] P-W. Li, M.J. Chin, P. R. Gray, and R. Castello, Ratio-
Independent algorithmic analog-to-digital conversion
technique, IEEE J. SSC, Vol. SC-19, no. 6 pp. 828-
836, Dec - 1984.

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