VISVESVARAYA NATIONAL INSTITUTE

OF TECHNOLOGY
NAGPUR

VLSI DESIGN
MTECH 2017-19
CMOS Digital VLSI Design LAB

ASSIGNMENT 2
Submitted by:
I.C.S.Tejaswi
20605
Find the propogation dealy for the inverter circuit.

a. w=l
Code:
Finding tpd
Vin 1 0 pulse(0 5 0 20ns 20ns 50ns 140ns)
Vdd 3 0 dc 5
C1 2 0 1p
M1 2 1 0 0 m1
.model m1 NMOS level=49 version=3.3.0
M2 2 1 3 3 m2
.model m2 PMOS level=49 version=3.3.0
.tran 1ns 560ns
.control
run
meas tran tf1 WHEN v(2)=4.11 CROSS=3
meas tran tf2 WHEN v(2)=2.5 CROSS=5
meas tran tr1 WHEN v(2)=-0.01 CROSS=3
meas tran tr2 WHEN v(2)=2.5 CROSS=6
let tf=tf2-tf1
let tr=tr2-tr1
let tpd=0.5*(tf+tr)
 print line tf tr tpd >d.txt
plot v(1) v(2)
.endc
.end

Here tf1 is the highest peak value obtained in ON state (> Vdd/2 )

tr1 is the lowest peak value obtained in OFF state (< Vdd/2 )

tf2 is the Vdd/2 point while output is falling form On state to Off state.

tr2 is the Vdd/2 point while output is raising from Off state to On state.

The rise time would be tr= tr2-tr1

The fall time would be tf=tf2-tf1
The propogation dealy is tp=0.5* (tf+tr)
This data is stored in d.txt.
Plot of Vo vs Vin:

Data obtained:
tf = 1.533549e-07 tr = 1.902665e-07 tpd = 1.718107e-07
b. w=2l
Code:
Finding tpd
Vin 1 0 pulse(0 5 0 20ns 20ns 50ns 140ns)
Vdd 3 0 dc 5
C1 2 0 1p
M1 2 1 0 0 m1 w=10u
.model m1 NMOS level=49 version=3.3.0
M2 2 1 3 3 m2 w=10u
.model m2 PMOS level=49 version=3.3.0
.tran 1ns 560ns
.control
run
meas tran tf1 WHEN v(2)=5.05 CROSS=3
meas tran tf2 WHEN v(2)=2.5 CROSS=5
meas tran tr1 WHEN v(2)=-0.01 CROSS=3
meas tran tr2 WHEN v(2)=2.5 CROSS=6
let tf=tf2-tf1
let tr=tr2-tr1
let tpd=0.5*(tf+tr)
print line tf tr tpd >d1.txt
plot v(1) v(2)
.endc
.end

Plot of Vo vs Vin:
Data obtained:
tf = 1.565025e-07 tr = 1.725972e-07 tpd = 1.645499e-07

c. 2w=l
Code:
Finding tpd
Vin 1 0 pulse(0 5 0 20ns 20ns 50ns 140ns)
Vdd 3 0 dc 5
C1 2 0 1p
M1 2 1 0 0 m1 l=10u
.model m1 NMOS level=49 version=3.3.0
M2 2 1 3 3 m2 l=10u
.model m2 PMOS level=49 version=3.3.0
.tran 1ns 560ns
.control
run
meas tran tf1 WHEN v(2)=5.05 CROSS=3
meas tran tf2 WHEN v(2)=2.5 CROSS=5
meas tran tr1 WHEN v(2)=-0.01 CROSS=3
meas tran tr2 WHEN v(2)=2.5 CROSS=6
let tf=tf2-tf1
let tr=tr2-tr1
let tpd=0.5*(tf+tr)
print line tf tr tpd >d2.txt
plot v(1) v(2)
.endc
.end

Plot of Vo vs Vin:
Tpd cannot be found in this case for the same input which was given to previous examples.
Since Vdd/2 has never been reached so it is always in Off state.
The channel length been increased so the current would be less. Capacitor cannot charge fully.
Vout is not reaching Vdd/2.

If Off time of input is more than On time:

For the same 2W=L MOSFET,
Vin is Off for long time than in On state resulting n-MOS will be in cutoff and p-MOS is in Linear
region. Capacitor would charge more to reach Vdd - (Idsp * Rdsp).
d. 2w=2l
Code:
Finding tpd
Vin 1 0 pulse(0 5 0 20ns 20ns 50ns 140ns)
Vdd 3 0 dc 5
C1 2 0 1p
M1 2 1 0 0 m1 w=10u l=10u
.model m1 NMOS level=49 version=3.3.0
M2 2 1 3 3 m2 w=10u l=10u
.model m2 PMOS level=49 version=3.3.0
.tran 1ns 560ns
.control
run
meas tran tf1 WHEN v(2)=4.175 CROSS=3
meas tran tf2 WHEN v(2)=2.5 CROSS=5
meas tran tr1 WHEN v(2)=-0.24 CROSS=3
meas tran tr2 WHEN v(2)=2.5 CROSS=6
let tf=tf2-tf1
let tr=tr2-tr1
let tpd=0.5*(tf+tr)
print line tf tr tpd >d3.txt
plot v(1) v(2)
.endc
.end
Plot of Vo vs Vin:
Data obtained:

tf = 1.532392e-07 tr = 1.809861e-07 tpd = 1.671126e-07

If rise time and fall time of input are less:

Steep increase in input leads to overshoots due to Gibbs phenomenon.

Plot of Vout vs Vin for w=l Mosfet :

Plot of Vout vs Vin of w=l Mosfet with more input off time:

If off time is more in input , n-Mos is off and p-Mos in saturation for long time. So capacitor
would charge more.

THE END