Chapter 3 - Models For Cmos Components

Chapter 3 – Introduction (12/20/06) Page 3.
0-1
CHAPTER 3 – MODELS FOR CMOS COMPONENTS

INTRODUCTION
Chapter Outline
3.1 – Large Signal Transistor Models
3.2 – Process, Voltage, and Temperature Variations
3.3 – Small Signal Transistor Model
3.4 – Passive Component Models
3.5 – Matching of Components
3.6 – SPICE Models
3.7 – Model Extraction
3.8 – Summary
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 3 – Introduction (12/20/06) Page 3.0-2
Models Suitable for Understanding Analog Design

The model required for analog design with CMOS technology is one that leads to
understanding and insight as distinguished from accuracy.
Technology
Understanding
and Usage
Updating Model Thinking Model Updating Technology

Simple,
±10% to ±50% accuracy
Comparison of Design Decisions- Extraction of Simple

simulation with "What can I change to Model Parameters
expectations accomplish ....?" from Computer Models
Expectations
"Ballpark"
Computer Simulation
Refined and
optimized
design Fig.3.0-02
This chapter is devoted to the simple model suitable for design not using simulation.
Chapter 3 – Introduction (12/20/06) Page 3.0-3
Categorization of Electrical Models
Time Dependence
Time Independent Time Dependent
Linear Small-signal, midband Small-signal frequency

Rin, Av, Rout response-poles and zeros
Linearity (.TF) (.AC)
Nonlinear DC operating point Large-signal transient

iD = f(vD,vG,vS,vB) response - Slew rate
(.OP) (.TRAN)
Based on the simulation capabilities of SPICE.
Chapter 3 – Section 1 (12/20/06) Page 3.1-1
SECTION 3.1 – LARGE SIGNAL TRANSISTOR MOSFET MODELS

OPERATION OF THE MOSFET TRANSISTOR
Formation of the Channel for an Enhancement MOS Transistor
;;;
Subthreshold (VG<VT)
VB = 0 VS = 0 VG < VT VD = 0
;; ;;;
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region
Threshold (VG=VT)
;; ;;;
;;;;
VB = 0 VS = 0 VG =VT VD = 0
Polysilicon
p+
;; ;;;
n+ n+
;;;
p- substrate Inverted Region
Strong Threshold (VG>VT)
;;;
VB = 0 VS = 0 VG >VT VD = 0
;;;;;;
;;;
Polysilicon
p+ n+ n+
CMOS Analog Circuit Design Fig.3.1-02 © P.E. Allen - 2006

Transconductance Characteristics of an Enhancement NMOSFET when VDS = 0.1V
;;;
VGS≤VT:
VB = 0 VS = 0 vG =VT VD = 0.1V iD
;; ;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate Depletion Region 0 vGS
0 VT 2VT 3VT
VGS=2VT:
;;;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.1V iD
iD
Polysilicon
p+
;; ;;; n+ n+
;;;
0 vGS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 0.1V iD
;;;;;;
;;;
Polysilicon
p+ n+ n+

0 vGS
0 VT 2VT 3VT Fig.3.1-03
Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT
;;;
VDS=0:
VB = 0 VS = 0 vG =2VT VD = 0V iD
;;;;
;; ;;;
iD
Polysilicon VGS = 2VT
;; ;;;
p+ n+ n+
;;;
0 vDS
0 0.5VT VT
VDS=0.5VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 0.5VT iD
iD
Polysilicon VGS = 2VT
p+
;;
;;;;
;;;
n+ n+
;;;
p- substrate Channel current
0 vDS
0 0.5VT VT
VDS=VT:
;;;
VB = 0 VS = 0 VG = 2VT VD =VT iD
;;
;;;;
;;;
iD VGS = 2VT
Polysilicon
p+ n+ n+
A depletion region
p- substrate
forms between the drain and channel 0 vDS
0 0.5VT VT Fig.3.1-04

Output Characteristics of the Enhanced NMOS when vDS = 2VT
;;;;;
VGS=VT:
VB = 0 VS = 0 vG =VT VD = 2VT iD
;;;
iD
Polysilicon
;; ;;;
p+ n+ n+
;;;
p- substrate VGS =VT
0 vDS
0 VT 2VT 3VT
VGS=2VT:
;;
;;;;
;;;
VB = 0 VS = 0 VG = 2VT VD = 2VT iD
iD
Polysilicon
;;
;;;;
;;;
VGS =2VT
p+ n+ n+
;;;
p- substrate
0 vDS
0 VT 2VT 3VT
VGS=3VT:
;;;
VB = 0 VS = 0 VG = 3VT VD = 2VT iD
VGS =3VT
;;
;;;;
;;;
iD
Polysilicon
p+ n+ n+
Further increase in
p- substrate
VG will cause the FET to become active 0 vDS
0 VT 2VT 3VT
Fig.3.1-05
Output Characteristics of an Enhancement NMOS Transistor

2000
VGS = 3.0
1500
VGS = 2.5
iD(μA)
1000
VGS = 2.0
500
VGS = 1.5
VGS = 1.0
0
SPICE Input File: 0 1 2 3 4 5
vDS (Volts) Fig. 3.1-6
Output Characteristics for NMOS M5 6 5 0 0 MOS1 w=5u l=1.0u
M1 6 1 0 0 MOS1 w=5u l=1.0u VGS5 5 0 3.0
VGS1 1 0 1.0 VDS 6 0 5
M2 6 2 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VGS2 2 0 1.5 +gamma=0.4 +lambda=.04 phi=.7)
M3 6 3 0 0 MOS1 w=5u l=1.0u .dc vds 0 5 .2
VGS3 3 0 2.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 6 4 0 0 MOS1 w=5u l=1.0u ID(M5)
VGS4 4 0 2.5 .end
Transconductance Characteristics of an Enhancement NMOS Transistor

6000
VDS = 5V
5000
VDS = 4V
VDS = 3V
4000
iD(μA)
3000
VDS = 2V
2000
VDS = 1V
1000
0
SPICE Input File: 0 1 2 3 4 5
vGS (Volts) Fig. 3.1-7
Transconductance Characteristics for NMOS M5 5 6 0 0 MOS1 w=5u l=1.0u
M1 1 6 0 0 MOS1 w=5u l=1.0u VDS5 5 0 5.0
VDS1 1 0 1.0 VGS 6 0 5
M2 2 6 0 0 MOS1 w=5u l=1.0u .model mos1 nmos (vto=0.7 kp=110u
VDS2 2 0 2.0 +gamma=0.4 lambda=.04 phi=.7)
M3 3 6 0 0 MOS1 w=5u l=1.0u .dc vgs 0 5 .2
VDS3 3 0 3.0 .print dc ID(M1), ID(M2), ID(M3), ID(M4),
M4 4 6 0 0 MOS1 w=5u l=1.0u ID(M5)
VDS4 4 0 4.0 .probe
.end
;;;
SIMPLE LARGE SIGNAL MODEL (SAH MODEL)
;;;
Large Signal Model Derivation +
vGS +
1.) Let the charge per unit area in the channel -
iD - vDS
inversion layer be
n+ n+
QI(y) = -Cox[vGS-v(y)-VT] (coul./cm2) v(y)
Source dy Drain
p - y
2.) Define sheet conductivity of the inversion 0 L y y+dy
layer per square as Fig.110-03

cm2 coulombs amps 1
S = μoQI(y)
v·s
cm2 = volt = /sq.
3.) Ohm's Law for current in a sheet is
iD dv -iD -iDdy
JS = W = -SEy = -S dy dv = SW dy = μoQI(y)W iD dy = -WμoQI(y)dv
4.) Integrating along the channel for 0 to L gives
L vDS vDS

iDdy = - WμoQI(y)dv = WμoCox[vGS-v(y)-VT] dv

0 0 0
5.) Evaluating the limits gives
WμoCox v2(y)vDS WμoCox vDS2
iD = L (vGS-VT)v(y) -

2 0 iD = L (vGS-VT)vDS -

2

Saturation Voltage - VDS(sat) iD

vDS = vGS-VT
Interpretation of the large
signal model:
Active Region Saturation Region
Increasing
values of vGS
vDS
Fig. 110-04
The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of
the inverted parabolas. vDS
diD μoCoxW
dvDS = L [(vGS-VT) - vDS] = 0
Cutoff Saturation Active
T
V
vDS(sat) = vGS - VT
S-
vG
S=
Useful definitions:
vD
0 vGS
μoCoxW K’W 0 VT Fig. 3.2-4
L = L =
The Simple Large Signal MOSFET Model

Regions of Operation of the MOS Transistor:
1.) Cutoff Region:
vGS - VT < 0
iD = 0
(Ignores subthreshold currents)
2.) Active Region Output Characteristics of the MOSFET:
0 < vDS < vGS - VT iD/ID0
vDS = vGS-VT
μoCoxW 1.0
Active
vGS-VT
= 1.0
VGS0-VT
iD = 2L 2(vGS - VT) - vDS vDS

Region Saturation Region
vGS-VT
0.75 = 0.867
VGS0-VT
Channel modulation effects
3.) Saturation Region vGS-VT
= 0.707
0.5 VGS0-VT
0 < vGS - VT < vDS vGS-VT
= 0.5
VGS0-VT
μoCoxW 0.25 vGS-VT
=0
iD = 2 Cutoff Region
2L vGS - VT
VGS0-VT
vDS
0
0 0.5 1.0 1.5 2.0 2.5 VGS0-VT
Fig. 110-05

Illustration of the Need to Account for the Influence of vDS on the Simple Sah Model
Compare the Simple Sah model to SPICE level 2:
25μA
2
K' = 44.8μA/V
20μA 2
k = 0, v DS(sat) K' = 44.8μA/V
= 1.0V k=0.5, v DS(sat)
= 1.0V
15μA
iD
10μA SPICE Level 2
K' = 29.6μA/V 2
5μA k = 0, vDS(sat)
= 1.0V
0μA
0 0.2 0.4 0.6 0.8 1
vDS (volts)
VGS = 2.0V, W/L = 100μm/100μm, and no mobility effects.
Modification of the Previous Model to Include the Effects of vDS on VT

From the previous derivation:
L vDS vDS

Di dy = - WμoQI(y)dv = WμoCox[vGS - v(y) -VT]dv
0 0 0
Assume that the threshold voltage varies across the channel in the following way:
VT(y) = VT + kv(y)
where VT is the value of VT the at the source end of the channel and k is a constant.
Integrating the above gives,
WμoCox v2(y)vDS
iD = L (vGS-VT)v(y) - (1+k) 2
0
or
WμoCox v2DS
iD = L (vGS-VT)vDS - (1+k) 2

To find vDS(sat), set the diD/dvDS equal to zero and solve for vDS = vDS(sat),
vGS - VT
vDS(sat) = 1 + k
Therefore, in the saturation region, the drain current is
WμoCox
iD = 2(1+k)L (vGS - VT)2
For k = 0.5 and K’ = 44.8μA/V2, excellent correlation is achieved with SPICE 2.
Influence of VDS on the Output Characteristics
;;;
Channel modulation effect: VG > VT VD > VDS(sat)
As the value of vDS increases, the
;;;;;;;
B S
effective L decreases causing the
Depletion
current to increase. Polysilicon
;;;;;;;
Region
p+ n+ n+
Illustration:
Leff
Note that Leff = L - Xd p- substrate Xd

Fig110-06
Therefore the model in saturation
becomes,
K’W diD K’W dLeff iD dXd
iD = 2Leff (vGS-VT)2 dvDS = - 2L 2 (vGS - VT)2 dvDS = Leff dvDS iD
eff
Therefore, a good approximation to the influence of vDS on iD is
diD K’W
iD iD( = 0) + dvDS vDS = iD( = 0)(1 + vDS) = 2L (vGS-VT)2(1+vDS)
Channel Length Modulation Parameter,

Assume the MOS is transistor is saturated-
μCoxW
iD = 2L (vGS - VT)2(1 + vDS)
Define iD(0) = iD when vDS = 0V.
μCoxW
iD(0) = 2
2L (vGS- VT)
Now,
iD = iD(0)[1 + vDS] = iD(0) + iD(0) vDS
Matching with y = mx + b gives the value of
iD
iD3(0) VGS3
iD2(0)
iD1(0) VGS2
VGS1
vDS
-1

Influence of Channel Length on

Note that the value of varies with channel length, L. The data below is from a 0.25μm
CMOS technology.
Channel Length Modulation (V-1)

0.6
0.5
0.4
PMOS
0.3
0.2
NMOS
0.1
0
0 0.5 1 1.5 2 2.5
Channel Length (microns) Fig.130-6
Most analog designers stay away from minimum channel length to get better gains and
matching at the sacrifice of speed.
Influence of the Bulk Voltage on the Large Signal MOSFET Model

The components of the threshold voltage VSB0 = 0: VBS0 = 0V VGS
are: VD > 0
iD
VT = Gate-bulk work function (MS) Polysilicon
p+ n+ n+
+ voltage to change the surface
potential (-2F) p- substrate
+ voltage to offset the channel-bulk VSB1 > 0: VBS1 > 0V VGS

VD > 0
depletion charge (-Qb/Cox) iD
Polysilicon
+ voltage to compensate the p+ n+ n+
undesired interface charge
(-Qss/Cox) p- substrate
We know that VSB2 >VSB1: VSB2 >VSB1: VGS

VD > 0
Qb = |2F| + |vBS| Polysilicon
iD = 0
Therefore, as the bulk becomes more p+ n+ n+

reverse biased with respect to the p- substrate
source, the threshold voltage must
060613-02
increase to offset the increased channel-
bulk depletion charge.
Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued
Bulk-Source (vBS) influence on the transconductance characteristics-
iD
Decreasing values
of bulk-source voltage
VBS = 0
ID
vDS > vGS-VT
VGS
vGS
VT0 VT1 VT2 VT3
060612-02
In general, the simple model incorporates the bulk effect into VT by the previously
developed relationship:
VT(vBS) = VT0 + 2|f| + |vBS| - 2|f|
Summary of the Simple Large Signal MOSFET Model D

+
N-channel reference convention: iD
G B
Non-saturation- v
+ + DS

WμoCox vDS2
vGS vBS
iD = L
(v
GS - V T)v DS -
(1 + v
2 DS ) - -
S Fig. 110-10
Saturation-
WμoCox vDS(sat)2
WμoCox
iD =
(1+v 2
2L (vGS-VT) (1+vDS)
(v -V )v (sat) - ) =
L GS T DS 2 DS
where:
μo = zero field mobility (cm2/volt·sec)
Cox = gate oxide capacitance per unit area (F/cm2)
= channel-length modulation parameter (volts-1)
VT = VT0 + 2|f| + |vBS| - 2|f|
VT0 = zero bias threshold voltage
= bulk threshold parameter (volts-0.5)
2|f| = strong inversion surface potential (volts)
For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert
the current.
Silicon Constants
Constant Constant Description Value Units

Symbol
VG Silicon bandgap (27°C) 1.205 V
k Boltzmann’s constant 1.381x10-23 J/K
ni Intrinsic carrier 1.45x1010 cm-3
concentration (27°C)
o Permittivity of free space 8.854x10-14 F/cm
si Permittivity of silicon 11.7 o F/cm
ox
Permittivity of SiO2 3.9 o F/cm
MOSFET Parameters
Model Parameters for a Typical CMOS Bulk Process (0.25μm CMOS n-well):
Parameter Typical Parameter Value Units

Parameter Description
Symbol N-Channel P-Channel
VT0 Threshold Voltage 0.5± 0.15 -0.5 ± 0.15 V
(VBS = 0)
K' Transconductance Para- 120.0 ± 10% 25.0 ± 10% μA/V2
meter (in saturation)
Bulk threshold 0.4 0.6 (V)1/2
parameter
Channel length 0.32 (L=Lmin) 0.56 (L=Lmin) (V)-1
modulation parameter 0.06 (L 2Lmin) 0.08 (L 2Lmin)
2|F| Surface potential at 0.7 0.8 V
strong inversion

SUBTHRESHOLD MODEL
Large-Signal Model for Weak Inversion
The electrons in the substrate at the source side can be expressed as,

s
np(0) = npoexpVt
The electrons in the substrate at the drain side can be expressed as,
-v
s DS
np(L) = npoexp Vt
Therefore, the drain current due to diffusion is,

n (L)- n (0) v
p p W s DS
iD = qADn L =

L qXD n
n poexp 1 - exp-
Vt

Vt

where X is the thickness of the region in which iD flows.

In weak inversion, the changes in the surface potential, s are controlled by changes in
the gate-source voltage, vGS, through a voltage divider consisting of Cox and Cjs, the
depletion region capacitance.
Poly
ds Cox 1 vGS vGS-VT
dvGS = Cox+ Cjs = n s = n + k1 = n + k2 Oxide Cox vGS
Channel
where Dep. Cjs φs
VT
k2 = k1 + n Substrate
CMOS Analog Circuit Design 060405-04
© P.E. Allen - 2006
Large-Signal Model for Weak Inversion – Continued

Substituting the above relationships back into the expression for iD gives,
k v v
W
2
GS-VT
DS
iD = L qXDnnpo exp
Vt exp
nVt 1 - exp
- Vt
Define It as
k

2
It = qXDnnpo exp
Vt
to get,
v v
W
GS-VT
DS
iD = L It exp
nVt 1 - exp
- Vt
where n 1.5 – 3 iD
VGS=VT
If vDS > 0, then 1μA
v vDS
W
GS-VT
iD = It L exp nVt
1 + VA

VGS<VT
The boundary between nonsaturated
and saturated is found as,
Vov = VDS(sat) = VON = VGS -VT = 2nVt 0 vDS
0 1V
Fig. 140-03

SHORT CHANNEL, STRONG INVERSION MODEL

What is Velocity Saturation?
Electron Drift Velocity (m/s)

The most important short-channel 105
effect in MOSFETs is the velocity
saturation of carriers in the channel. 5x104
A plot of electron drift velocity
2x104
versus electric field is shown below.
104
5x103
An expression for the electron drift 105 106 107
velocity as a function of the electric Electric Field (V/m) Fig130-1
field is,
μn E
vd 1 + E/Ec
where
vd = electron drift velocity (m/s)
μn = low-field mobility ( 0.07m2/V·s)
Ec = critical electrical field at which velocity saturation occurs
Short-Channel Model Derivation

As before,
iD WQI(y)μnE
E
JD = JS = W = QI(y)vd(y) iD = WQI(y)vd(y) = 1 + E/Ec iD 1+ Ec

= WQI(y)μnE
Replacing E by dv/dy gives,

1 dv
dv
iD 1 + Ec dy
= WQI(y)μndy
Integrating along the channel gives,
L

1 dv
vDS

iD 1 + Ec dy
dy = WQI(y)μndv
0 0
The result of this integration is,
μnCox W μnCox W
2] =
iD = 1 vDS
L [2(v GS -V T )v DS -v DS 21 + vDS L [2(vGS-VT)vDS-vDS2]

21 + Ec L
where = 1/(EcL) with dimensions of V-1.

Saturation Voltage
Differentiating iD with respect to vDS and setting equal to zero gives,
(VGS-VT)
1
V’DS(sat) = 1 + 2(VGS-VT -1 (VGS-VT)1 -

2 + ···
if
(VGS-VT)
2 <1
Therefore,

(VGS-VT)

V’DS(sat) VDS(sat) 1 -
2 + ···
Note that the transistor will enter the saturation region for vDS < vGS - VT in the presence
of velocity saturation.
Large Signal Model for the Saturation Region

Assuming that
(VGS-VT)
2 <1
gives
V’DS(sat) (VGS-VT)
Therefore the large signal model in the saturation region becomes,
(VGS-VT)
K’ W
iD = 2[1 + (vGS-VT)] L [ vGS - VT]2, vDS (VGS-VT) 1 -

2 + ···

The Influence of Velocity Saturation on the Transconductance Characteristics

The following plot was made for K’ = 110μA/V2 and W/L = 1:
1000
θ=0
θ = 0.2
800
θ = 0.4
iD/W (μA/μm) 600
θ = 0.6
400
θ = 0.8
θ = 1.0
200
0
0.5 1 1.5 2 2.5 3
vGS (V) Fig130-2
Note as the velocity saturation effect becomes stronger, that the drain current-gate
voltage relationship becomes linear.
Circuit Model for Velocity Saturation

A simple circuit model to include the influence of velocity saturation D
is the following:
iD
We know that G
+ +
K’W vGS' -
iD = 2L (vGS’ -VT)2 and vGS = vGS’ + iD RSX
or vGS RSX
vGS’ = vGS - iDRXS
Substituting vGS’ into the current relationship gives, Fig130-3 - S
K’W
iD = 2L (vGS - iDRSX -VT)2
Solving for iD results in,
K’ W
iD = W L (vGS - VT)2

2 1 + K’ L RSX(vGS-VT)

Comparing with the previous result, we see that

W L 1
= K’ L RSX RSX = K’W = EcK’W
Therefore for K’ = 110μA/V2, W = 1μm and Ec = 1.5x106V/m, we get RSX = 6.06k.
CAPACITANCES OF THE MOSFET

Types of Capacitance
Physical Picture:
SiO2
Gate
Source Drain
C1 C2 C3
FOX FOX
C4
CBS CBD
Bulk
Fig120-06
MOSFET capacitors consist of:

• Depletion capacitances
• Charge storage or parallel plate capacitances
MOSFET Depletion Capacitors Polysilicon gate

Model:
1.) vBS FC·PB H G
C
CJ·AS CJSW·PS D
CBS = MJ + MJSW, Source Drain
vBS vBS
1 - 1 -
PB PB F
E
and B
A
2.) vBS> FC·PB SiO2
Bulk

CJ·AS V BS Drain bottom = ABCD
Fig. 120-07
CBS = 1+MJ
1 - (1+MJ)FC + MJ PB

Drain sidewall = ABFE + BCGF + DCGH + ADHE
(1- FC)
VBS
CJSW·PS CBS
+ 1+MJSW 1 - (1+MJSW)FC + MJSW PB

(1 - FC)
where vBS ≥ FC·PB
AS = area of the source vBS ≤ FC·PB
PB
PS = perimeter of the source vBS
CJSW = zero bias, bulk source sidewall capacitance FC·PB Fig. 120-08
MJSW = bulk-source sidewall grading coefficient
For the bulk-drain depletion capacitance replace "S" by "D" in the above.
Charge Storage (Parallel Plate) MOSFET Capacitances - C1, C2, C3 and C4
Mask L Oxide encroachment

Overlap capacitances:
Actual C1 = C3 = LD·Weff·Cox = CGSO or CGDO
Mask Actual
L (Leff)
W (Weff) (LD 0.015 μm for LDD structures)
LD W
Gate
Drain-gate overlap
Channel capacitances:
Source-gate overlap
capacitance CGS (C1) capacitance CGD (C3) C2 = gate-to-channel = CoxWeff·(L-2LD) =
Gate CoxWeff·Leff
FOX FOX
Source Drain C4 = voltage dependent channel-
Gate-Channel Channel-Bulk
Capacitance (C2)
Bulk
Capacitance (C4)
bulk/substrate capacitance
Fig. 120-09
Charge Storage (Parallel Plate) MOSFET Capacitances - C5

View looking down the channel from source to drain
Overlap Overlap
Gate
FOX C5 Source/Drain C5 FOX
Bulk
Fig120-10
C5 = CGBO
Capacitance values based on an oxide thickness of 140 Å or Cox=24.7 10-4 F/m2:
Type P-Channel N-Channel Units
CGSO 220 10-12 220 10-12 F/m
CGDO 220 10-12 220 10-12 F/m
CGBO 700 10-12 700 10-12 F/m
CJ 560 10-6 770 10-6 F/m2
CJSW 350 10-12 380 10-12 F/m
MJ 0.5 0.5
MJSW 0.35 0.38
;;;
Expressions for CGD, CGS and CGB
Cutoff
Cutoff Region: VB = 0 VS = 0 VG < VT VD > 0
CGS
CGB = C2+2C5 = Cox(Weff)(Leff) Polysilicon
CGD
+ 2CGBO(Leff) p+ n+ CGB n+
CGS = C1 Cox(LD)Weff = CGSO(Weff)
;;;
p- substrate
CGD = C3 Cox(LD)Weff = CGDO(Weff)
Saturated
Saturation Region: VB = 0 VS = 0 VG >VT VD >VG -VT
CGB = 2C5 = CGBO(Leff) CGS
Polysilicon
CGD
CGS = C1+(2/3)C2 =
p+ n+ n+
;;;
Cox(LD+0.67Leff)(Weff)
= CGSO(Weff) + 0.67Cox(Weff)(Leff)
CGD = C3 Cox(LD)Weff) = CGDO(Weff) Active
;;;
VB = 0 VS = 0 VG >VT VD <VG -VT
Nonsaturated Region: CGS
Polysilicon
CGD
CGB = 2 C 5 = 2CGBO(Leff)
p+ n+ n+
CGS = C1 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGSO + 0.5CoxLeff)Weff p- substrate Inverted Region
Fig120-11
CGD = C3 + 0.5C2 = Cox(LD+0.5Leff)(Weff)
= (CGDO + 0.5CoxLeff)Weff
Illustration of CGD, CGS and CGB

Comments on the variation of CBG in the cutoff region:
1 Capacitance
CBG = 1 1 + 2C5
+ C4 Large
C2 C4
C2 + 2C5
1.) For vGS 0, CGB C2 + 2C5 CGS
C1+ 0.67C2
(C4 is large because of the thin CGS, CGD
C1+ 0.5C2
inversion layer in weak inversion vDS = constant
CGS, CGD CGD vBS = 0
C1, C3
where VGS is slightly less than VT)) CGB C4 Small
2C5
0 vGS
2.) For 0 < vGS VT, CGB 2C5 Off Saturation Non-
Saturation
(C4 is small because of the thicker VT vDS +VT Fig120-12
inversion layer in strong inversion)

SECTION 3.2 – PROCESS, VOLTAGE, AND TEMPERATURE

(PVT)VARIATIONS OF CMOS TECHNOLOGY
PROCESS VARIATIONS
How Does Technology Vary?
1.) Thickness variations in layers (dielectrics and metal)
tox(min) tox(max)
060225-01
2.) Doping variations

n+ p+ p+
n-well Diffusion Differences

060225-02
3.) Process biases – differences between the drawn and actual dimensions due to process
(etching, lateral diffusion, etc.)
Drawn Dimension
Actual Dimension
060225-03
Large Signal Model Dependence on Process Variations

1.) Threshold voltage
VT = VT0 + |-2F + vSB| - |-2F|
where
Qb0 QSS 2qsiNA
VT0 = MS - 2F - Cox - Cox and = Cox
If VBS = 0, then VT is dependent on doping and oxide thickness because
kT NSUB 1
F = q ln ni and Cox tox
(Recall that the threshold is also determined by the threshold implant during processing)
2.) Transconductance parameter
1
K’ = μoCox tox
For short channel devices, the mobility is degraded as given by
μo 2x10-9m/V
μeff = 1 + (VGS - VT) and tox

Process Variation “Corners”

For strong inversion operation, the primary influence is the oxide thickness, tox. We see
that K’ will tend to increase with decreasing oxide thickness whereas VT tends to
decrease.
If the “speed” of a transistor is increased by increasing K’ and decreasing VT, then the
variation of technology can be expressed on a two-dimensional graph resulting in a
rectangular area of “acceptable” process limitation.
PMOS
Speed
Large Kʼ
Fast Small VT
PMOS Acceptable
Technology
Slow Parameters
PMOS Small Kʼ
Large VT
Slow Fast NMOS Speed
060118-10
NMOS NMOS
VOLTAGE VARIATION
What is Voltage Variation?
Voltage variation is the influence of power supply voltage on the component.
(There is also power supply influence on the circuit called power supply rejection ratio,
PSRR. We will deal with this much later.)
Power supply variation comes from:
1.) Influence of depletion region widths on components.
2.) Nonlinearity
3.) Breakdown voltage
Note: Because the large-signal model for the MOSFET includes all the influences of
voltage on the transistor, we will focus on passive components except for breakdown.

Models for Voltage Dependence of a Component

1.) ith-order Voltage Coefficients
In general a variable y = f(v) which is a function of voltage, v, can be expressed as a
Taylor series,
y(v = V0) y(V0) + a1(v- V0) + a2(v- V0)2+ a3(v- V0)3 + ···
where the coefficients, ai, are defined as,
df(v) | 1 d2f(v) |
a1 = dv v=V0 , a2 = 2 dv2 v=V0 , ….
The coefficients, ai, are called the first-order, second-order, …. voltage coefficients.
2.) Fractional Voltage Coefficient or Voltage Coefficient
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional voltage coefficient, VCF, which is defined as,
1 df(v) |
VCF(v=V0) = f(v=V0) dv v=V0 parts per million/V (ppm/V)
or more simply,
1 df(v)
VCF = f(v) dv parts per million/V (ppm/V)
Influence of Voltage on a Diffused Resistor – Depletion Region

Influence of the depletion region on the p+ resistor:
Thickness of
p+ p+ Resistor Thickness of
p+ Resistor
FOX FOX p+ p+
Depletion region
STI STI
n- well
n-well
p- substrate
060305-01 Older LOCOS Technology
As the voltage at the terminals of the resistor become smaller than the n-well potential,
the depletion region will widen causing the thickness of the resistor to decrease.
L
R = tW VR
where VR is the reverse bias voltage from the resistor to the well.
This effect is worse for well resistors because the doping concentration of the resistor is
smaller.
Voltage coefficient for diffused resistors 200-800 ppm/V
Voltage coefficient for well resistors 8000 ppm/V
Voltage Nonlinearity
Conductivity modulation:
As the current in a resistor increases, the conductivity becomes modulated and the
resistance increases. i
i= v
Example of a n-well resistor: R
0.1A
Conductivity
modulation
v
060311-01
As the reverse bias voltage across a pn junction

iR
becomes large, at some point, called the breakdown
voltage, the current will rapidly increase. Both
transistors, diodes and depletion capacitors experience
this breakdown.
Model for current multiplication factor: Breakdown
voltage
1 vR
M=
vR n

060311-02 BV
1 + BV

TEMPERATURE VARIATIONS
Models for Voltage Dependence of a Component
1.) ith-order Temperature Coefficients
As for voltage, the temperature dependence can be expressed as,
y(T = T0) y(T0) + a1(T- T0) + a2(T- AT0)2+ a3(T- T0)3 + ···
where the coefficients, ai, are defined as,
df(T) | 1 d2f(T) |
a1 = dT T=T0 , a2 = 2 dT2 T=T0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature coefficients.
2.) Fractional Temperature Coefficient or Temperature Coefficient
Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a term
called fractional temperature coefficient, TCF, which is defined as,
1 df(T) |
TCF(T=T0) = f(T=T0) dT T=T0 parts per million/°C (ppm/°C)
or more simply,
1 df(T)
TCF = f(T) dT parts per million/°C (ppm/°C)
Temperature Dependence of the MOSFET

Transconductance parameter:
-1.5
K’(T) = K’(T0) (T/T0) (Exponent becomes +1.5 below 77°K)
Threshold Voltage:
VT(T) = VT(T0) + (T-T0) + ···
Typically NMOS = -2mV/°C to –3mV/°C from 200°K to 400°K (PMOS has a + sign)
Example
Find the value of ID for a NMOS transistor at 27°C and 100°C if VGS = 2V and W/L =
5μm/1μm if K’(T0) = 110μA/V2 and VT(T0) = 0.7V and T0 = 27°C and NMOS = -2mV/°C.
Solution
At room temperature, the value of drain current is,
110μA/V2·5μm
ID(27°C) = 2·1μm (2-0.7)2 = 465μA
-1.5
At T = 100°C (373°K), K’(100°C)=K’(27°C) (373/300) =110μA/V2·0.72=79.3μA/V2
and VT(100°C) = 0.7 – (.002)(73°C) = 0.554V
79.3μA/V2·5μm
ID(100°C) = 2·1μm (2-0.554)2 = 415μA (Repeat with VGS = 1.5V)
Zero Temperature Coefficient (ZTC) Point for MOSFETs

For a given value of gate-source voltage, the drain current of the MOSFET will be
independent of temperature. Consider the following circuit:
Assume that the transistor is saturated and that: ID
T
μ = μoTo-1.5

and VT(T) = VT(To) + (T-To)
VGS
where = -0.0023V/°C and To = 27°C
Fig. 4.5-12
μoCoxW T -1.5
ID(T) = 2L To [VGS – VT0 - (T-To)]2
dID -1.5μoCox T -2.5 T
-1.5
= [V -V - (T-T )]2 + μ C [VGS-VT0-(T-To)] = 0
dT 2To
To
GS T0 o o oxTo
-4T
VGS – VT0 - (T-To) = 3 VGS(ZTC) = VT0 - To - 3
Let K’ = 10μA/V2, W/L = 5 and VT0 = 0.71V.
At T=27°C(300°K), VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(300°K)=1.63V
At T = 27°C (300°K), ID = (10μA/V2)(5/2)(1.63-0.71)2 = 21.2μA
At T=200°C(473°K),VGS(ZTC)=0.71-(-0.0023)(300°K)-(0.333)(-0.0023)(473°K)=1.76V
Experimental Verification of the ZTC Point

The data below is for a 5μm n-channel MOSFET with W/L=50μm/10μm, NA=1016 cm-3,
tox = 650Å, uoCox = 10μA/V2, and VT0 = 0.71V.
25°C
100 100°C
VDS = 6V 150°C
200°C
80 250°C
275°C
60 300°C
ID (A)
40
150°C
275°C 250°C 200°C
Zero TC Point
20 25°C
100°C
0
0 0.6 1.2 1.8 2.4 3
VGS (V) 0600613-01
A similar result holds for the p-channel MOSFET.

UDSM technology may not yield a well-defined ZTC point.
Bulk-Drain (Bulk-Source) Leakage Currents

Cross-section of a NMOS in a p-well:
;;;
VG > VT VD > VDS(sat)
VGS>VT:
;;;;;;;
B S
Depletion
Polysilicon
;;;;;;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-5
VGS<VT:
;;;
VG <VT VD > VDS(sat)
;;; ;;
B S
Depletion
Polysilicon
;;; ;;
Region
p+ n+ n+
p-well
n- substrate
Fig.3.6-6
Temperature Modeling of the PN Junction

PN Junctions (Reverse-biased only):
D p 2
p no Dnnpo qAD ni V
Go
iD Is = qA Lp + Ln L N = KT 3exp Vt
Differentiating with respect to temperature gives,
V
V
dIs 3KT 3 Go qKT 3VGo Go 3Is Is VGo

dT = T exp
Vt + KT 2 exp
Vt
=
T + T Vt
dIs 3 1 VGo
TCF = IsdT = T + T Vt
Example
Assume that the temperature is 300° (room temperature) and calculate the reverse diode
current change and the TCF for a 5° increase.
Solution
The TCF can be calculated from the above expression as TCF = 0.01 + 0.155 = 0.165.
Since the TCF is change per degree, the reverse current will increase by a factor of 1.165
for every degree (or °C) change in temperature. Multiplying by 1.165 five times gives
an increase of approximately 2. Thus, the reverse saturation current approximately
doubles for every 5°C temperature increase. Experimentally, the reverse current doubles
for every 8°C increase in temperature because the reverse current is in part leakage
current.
Experimental Verification of the PN Junction Temperature Dependence
10-5
200°C Data
10-6 Symbol Min. L
6 μm
250°C
10-7
Leakage Current (A)
5 μm
4 μm
10-8 IR 2 μm
50μm
Lmin 100°C
10-9 1V
Theory
10-10 matched
at 150°C Generation-
Diffusion Recombination
10-11
Leakage Leakage
Dominant Dominant
10-12
1.8 2 2.2 2.4 2.6 2.8
-1
1000/T (°K ) Fig. 3.6-7
Theory:
VG(T)

Is(T) T exp kT 3


Temperature Modeling of the PN Junction – Continued

PN Junctions (Forward biased – vD constant):
v

D
iD Is exp
Vt
Differentiating this expression with respect to temperature and assuming that the diode
voltage is a constant (vD = VD) gives
diD iD dIs 1 VD
dT = Is dT - T Vt iD
The fractional temperature coefficient for iD is
1 diD 1 dIs VD 3 VGo - VD
iD dT = Is dT - TVt = T + TVt
If VD is assumed to be 0.6 volts, then the fractional temperature coefficient is equal to
0.01+(0.155-0.077) = 0.0879. The forward diode current will approx. double for a 10°C.
PN Junctions (Forward biased – iD constant):
VD = Vt ln(ID/Is)
Differentiating with respect to temperature gives
dvD vD dI V

1 s vD 3Vt VGo Go - vD 3Vt
dT = T - V

t Is dT = -
T T - T = -
T - T
Assuming that vD = VD = 0.6 V the temperature dependence of the forward diode voltage
at room temperature is approximately -2.3 mV/°C.
Resistor Dependence on Temperature

Diffused Resistors:
The temperature dependence of resistors depends mostly on the doping level of diffused
and implanted resistors. As the doping level or sheet resistance increases from 100 /
to 400 /, the temperature coefficient varies from about +1000 ppm/°C to +4000
ppm/°C. Diffused and implanted resistors have good thermal conduction to the substrate
or well.
Polysilicon Resistors:
Typically has a sheet resistance of 20 / to 80 / and has poor thermal conduction
because it is electrically isolated by oxide layers.
Metal:
Metal is often used for resistors and has a positive temperature coefficient.
Temperature Coefficients of Resistors:
n-well = 4000 ppm/°C Diffusion = +1500 ppm/°C
Polysilicon = 500-2000 ppm/°C Ion implanted = +400 ppm/°C
Metal = +3800 ppm/°C (aluminum)

SECTION 3.3 – SMALL SIGNAL TRANSISTOR MOSFET MODELS

FREQUENCY INDEPENDENT
What is a Small Signal Model?
The small signal model is a linear approximation of a nonlinear model.
Mathematically:
Large Signal to Small Signal
iD = 2 (vGS - VT)2 id = gmvgs
Graphically:
iD
The large signal curve at point Q has been
iD = β(vGS-VT)2
approximated with a small signal model going
id through the point Q and having a slope of gm.
id = gmvgs
ID Q
vgs
vGS
VT VGS 060311-03
Why Small Signal Models?

The small signal model is a linear approximation to the large signal behavior.
1.) The transistor is biased at given DC operating point (Point Q above)
2.) Voltage changes are made about the operating point.
3.) Current changes result from the voltage changes.
If the designer is interested in only the current changes and not the DC value, then the
small signal model is a fast and simple way to find the current changes given the voltage
changes.
id
Large Signal
Model
id = gmvgs
ΔiD ΔiDʼ Q
vgs
ΔVGS 060311-04

How Good is the Small Signal Model?

It depends on how large are the changes and how nonlinear is the large signal model.
• The parameters of the small signal model will depend on the values of the large signal
model.
• The model is a tradeoff in complexity versus accuracy (we will choose simplicity and
give up accuracy).
• What does a simulator do? Exactly the same thing when it makes an ac analysis (i.e.
frequency response)
• Regardless of the approximate nature of the small signal model, it is the primary model
used to predict the signal performance of an analog circuit.
Small-Signal Model for the Saturation Region

The small-signal model is a linearization of the large signal model about a quiescent or
operating point.
Consider the large-signal MOSFET in the saturation region (vDS vGS – VT) :
WμoCox
2L (vGS - VT) 2 (1 + vDS)
iD =
The small-signal model is the linear dependence of id on vgs, vbs, and vds. Written as,
id gmvgs + gmbsvbs + gds vds
where
diD |
gm dvGS Q = (VGS-VT) = 2ID
diD | ID
gds dvDS Q = 1 + VDS ID
and
dD | diD dvGS | diD dVT | gm
gmbs dvBS Q = dvGS dvBS Q = - =
dVTdvBSQ 2 2|F| - VBS = gm

Small-Signal Model – Continued

Complete schematic D D
id
G B
model: + + +D
G B G B vgs vbs rds vds
gmvgs gmbsvbs
- - -
S S
where S S Fig. 120-01
diD | diD | iD

gm dvGS Q = (VGS-VT) = 2ID gds dvDS Q = 1 + vDS iD
and
D | iD vGS | iD vT | gm
gmbs = vBS Q = vGS vBS Q = - vTvBSQ= 2 2| | - V = gm
F BS
Simplified schematic model:
id
D D G
+ +D
An extremely important
G G vgs rds vds
assumption: gmvgs
- -
gm 10gmbs 100gds S S S S
Fig. 120-02
An Alternate Way of Deriving the Small Signal Model

Large-Signal Characteristics:
Ignore channel modulation-
K’W 2iD
i = iD = 2L (vGS - VT)2 = 2 (vGS - VT)2 and v = vGS = vDS = VT +
Small-Signal Characteristics:
The small signal model is a linearization of the large signal model at an operating point.

iD = 2 (vGS-VT)2(1+vDS) d + ID = 2 [vgs+(VGS-VT)]2[1+(vds+VDS)]

id+ID = 2 vgs2 + (VGS-VT)vgs + 2 (VGS-VT)2 + 2 vgs2vds + (VGS-VT)vgsvds

+ 2 (VGS-VT)2 vds + 2 vgs2VDS + (VGS-VT)vgsVDS + 2 (VGS-VT)2 VDS
Assume that vgs < VGS-VT, vds < VDS and <<1. Therefore we write:

id+ID (VGS-VT)vgs + 2 (VGS-VT)2vds + 2 (VGS-VT)2(1+VDS)

id = (VGS-VT)vgs+2 (VGS-VT)2vds = gmvgs+gdsvds and ID = 2 (VGS-VT)2(1+VDS)

Small-Signal Model for the Nonsaturated Region
iD | K’WVDS
K’W
gm = vGS Q = L (1+ V DS ) L VDS

iD | K’W VDS

gmbs = vBS Q = 2L 2 - V
F BS
iD | K’W ID K’W

gds = vDS Q = L ( VGS - VT - VDS)(1+VDS) + 1+VDS L (VGS - VT - VDS)
Note:
While the small-signal model analysis is independent of the region of operation, the
evaluation of the small-signal performance is not.
Small Signal Model for the Subthreshold Region

If vDS > 0, then
W
iD = Kx L evGS/nVt (1 + vDS)
Small-signal model:
diD | qID
gm = dvGS Q = nkT
diD | ID
gds = dvDS Q VA

FREQUENCY DEPENDENT SMALL SIGNAL MODEL

Small-Signal Frequency Dependent Model
The depletion capacitors are found by evaluating the large signal capacitors at the DC
operating point.
The charge storage capacitors are constant for a specific region of operation.
Cgd id
G D
+ +
Cgs
vgs rds vds
gmvgs gmbsvbs
- -
Cgb S - S Cbd
vbs Cbs
+
B Fig120-13
Gain-bandwidth of the MOSFET (fT)

The short-circuit current gain is measure of the frequency capability of the MOSFET.
iout
Small signal model: Cgd iout
+ C
iin gs
VDD vgs rds
iin − gmvgs Cbd
060311-05
Small signal analysis
gives,
iin
iout = gmvgs – sCgdvgs and vgs = s(Cgs + Cgd)
Therefore,
iout gm-sCgd gm
=
iin s(Cgs + Cgd) s(Cgs + Cgd)
Assume VSB = 0 and the MOSFET is in saturation,
1 gm 1 gm
fT = 2 Cgs + Cgd 2 Cgs
Recalling that
2 W 3 μo
Cgs 3 CoxWL and gm = μoCox L (VGS-VT) fT = 4 L2 (VGS-VT)
NOISE MODELS
MOS Device Noise at Low Frequencies
D D
D
eN2
G B G in2 G * B
Noise Noise
S B Free
Free S
MOSFET MOSFET S
where
8kTgm(1+) KF ID

in =
2
3 + fSCoxL2 f (amperes2)
f = bandwidth at a frequency, f
gmbs
= gm
k = Boltzmann’s constant
KF = Flicker noise coefficient
S = Slope factor of the 1/f noise
Reflecting the MOSFET Noise to the Gate

Dividing in2 by gm2 gives
in2 8kT(1+)
KF

en = gm2 = 3gm
2 + 2fCoxWL K’ f (volts2)
KF
It will be convenient to use B = 2CoxK’ for model simplification.
Frequency response of MOSFET noise:
Noise Spectral
Density
1/f noise
Thermal noise
fCorner log10 f
060311-06

MOSFET Noise Model at High Frequencies

At high frequencies, the source resistance can no longer be assumed to be small.
Therefore, a noise current generator at the input results.
MOSFET Noise Models:
Cgd
G D
vin Cgs vgs rds in2 io2

gmvgs
S S
Circuit 1: Frequency Dependent Noise Model
ei2 Cgd
G D
*
vin ii2 Cgs vgs rds io2
gmvgs
S S
Circuit 2: Input-referenced Noise Model
MOSFET Noise Model at High Frequencies – Continued

To find ei2 and ii2, we will perform the following calculations:
ei2:
Short-circuit the input and find io2 of both models and equate to get ei2 .
Ckt. 1: io2 = in2
2
in2
e = gm2 + (Cgd)2
i
Ckt. 2: io2 = gm2 ei2+ (Cgd)2ei2
ii2:
Open-circuit the input and find io2 of both models and equate to get ii2 .
Ckt. 1: io2 = in2

(1/Cgs) gm2ii2

2
Ckt. 2: io = (1/Cds) + (1/Cgs) ii + 2(Cgs+Cds)2
2

2
gm2 2Cgs2
2Cgs2 in2 if Cgd < Cgs ii2 = gm2 in2

SECTION 3.4 – PASSIVE COMPONENT MODELS

RESISTOR
Resistor Models v v
i + R (v) i + R (v)
− −
Cp Cp1 Cp2
Distributed Model Lumped Model

060315-01
i
1.) Large signal i = Rv
Conductivity
modulation
v
2.) Small signal 060311-01
v = Ri
3.) Noise
en2 = 4kTR or in2 = 4kTG
CAPACITOR
Capacitor Models Rp
One of the parasitic capacitors
i C(v) is the top plate and the other is
+ − associated with the bottom
Cp v plate.
Cp
060315-03
C
1.) Large signal Linear
Nonlinear
v
q = Cv i = C(dv/dt)
3.) Do capacitors have noise? See next page.

Switched Capacitor Circuits - kT/C Noise

Capacitors and switches generate an inherent thermal noise given by kT/C. This noise is
verified as follows.
Ron
An equivalent circuit for a switched
capacitor: vin v vin v
C out C out
060315-05
The noise voltage spectral density of switched capacitor above is given as

2kTRon
eR2on = 4kTRon Volts2/Hz = Volt2/Rad./sec.
The rms noise voltage is found by integrating this spectral density from 0 to to give

2kTRon 12d 2kTRon
1 kT
2 =
vRon
12+2 =
2 = C Volts(rms)2
0
where 1 = 1/(RonC). Note that the switch has an effective noise bandwidth of
1
fsw = 4RonC Hz
which is found by dividing the second relationship by the first.
INDUCTOR
Inductor Models v
L(i) R
R = losses of the inductor + −
Cp = parasitic capacitance to ground i
Cp Cp
Rp = losses due to eddy currents caused by
Rp Rp
magnetic flux
1.) Large Signal L 060316-03
Linear
Nonlinear
i
d di
= Li dt = v = L dt
i1 M i2 i1 L1-M L2-M i2
3.) Mutual inductance
di1 di2 + + + +
v1 L1 L2 v2 v1 M v2
v1 = L1 dt + M dt M
k= L L − − − −
di1 di2 1 2 060316-05
v2 = M dt + L2 dt

INTERCONNECTS
Types of “Wires”
1.) Metal
Many layers are available in today’s technologies:
- Lower level metals have more resistance (70 m/sq.)
- Upper level metal has the less resistance because it is thicker (50 m/sq.)
2.) Polysilicon
Better resistor than conductor (unpolysicided) (135/sq.)
Silicided polysilicon has a lower resistance (5/sq.)
3.) Diffusion
Reasonable for connections if silicided (5/sq.)
Unsilicided (55/sq.)
4.) Vias
Vias are vertical metal (tungsten plugs or aluminum)
- Connect metal layer to metal layer (3.5/via)
- Connect metal to silicon or polysilicon contact resistance (5/contact)
Ohmic Contact Resistance

The metal to silicon contact generates resistance because of the presence of a potential
barrier between the metal and the silicon.
Contact and Via Resistance:

Contact
Contact System Resistance Metal 3
(/μm2) Aluminum
Al-Cu-Si to 160/sq. base 750 Vias
Metal 2
Al-Cu-Si to 5/sq. emitter 40 Tungsten
Plugs
Al-Cu/Ti-W/PtSi to 1250 Metal 1
160/sq. base
Al-Cu/Al-Cu (Via) 5
Al-Cu/Ti-W/Al-Cu (Via) 5
Transistors
050319-02

Capacitance of Wires
Self, fringing and coupling capacitances:
Wide Spacing Minimum Spacing
CCoupling CCoupling
CFringe CFringe
Ground plane CSelf
050319-03
Capacitance Typical Value Units

Metal to diffusion, Self capacitance 33 aF/μm2
Metal to diffusion, Fringe capacitance, minimum spacing 7 aF/μm
Metal to diffusion, Fringe capacitance, wide spacing 40 aF/μm
Metal to metal, Coupling capacitance, minimum spacing 85 aF/μm
Metal to substrate, Self capacitance 28 aF/μm2
Metal to substrate, Fringe capacitance, minimum spacing 4 aF/μm
Metal to substrate, Fringe capacitance, wide spacing 39 aF/μm
Example of Coupling between the Input and Output of an Amplifier

For the NMOS in the layout below, find the location of the RHP zero caused by the
capacitive coupling due only to the metal-to-metal coupling capacitance between Vout and
Vin metal lines. Assume the transconductance is 775μS and Cgd = 3fF.
5V
n-substrate
M2
vout p-well
vin Poly
Metal
M1 Ground
p+
Each square is
1m x 1m
n+
050319-04
Assuming minimum spacing and 40μm of coupling gives Ccoupling = 3.4fF. The RHP
zero is given by,
gm 775μS
RHP zero = Ccoupling + Cgd = 6.4fF = 1.21x1011 radians/sec.(19.3 GHz)

Electromigration
Electromigration occurs if the current density is too large and the pressure of carrier
collisions on the metal atoms causes a slow displacement of the metal.
Black’s law:
1
MTF = AJ 2 e(Ea/kTj)
Metal 050304-04
Where
A = rate constant (cm4/A2/hr)
J = current density (A/cm2)
Ea = activation energy in electron volts (0.5eV for Al and 0.7eV for Cu doped Al)
k = Boltzmann’s constant (8.6x10-5 eV/K)
Electromigration leads to a maximum current density,Jmax. Jmax for copper doped
aluminum is 5x105 A/cm2 at 85°C.
If t = 10,000 Angstroms and Jmax = 5x105 A/cm2, then a 10μm wide lead can
conduct no more than 50mA at 85°C.
Where is AC Ground on the Chip?

AC grounds on the chip are any area tied to a fixed potential. This includes the substrate
and the wells. All parasitic capacitances are in reference to these points.
Protective Insulator Layer
VDD GRD
Top
Metal
GRD Metal Vias Metal Via Second
Inter- Level
mediate Tungsten Sidewall Tungsten Plugs Metal
Oxide Plugs Spacers Polycide
First
Layers Level
Tungsten Salicide Salicide Salicide Tungsten
Salicide Plugs Plug Metal
p+ n+ p+ p+ n+ n+ p+
Shallow Shallow Shallow
Trench Trench Trench
Isolation AC Ground Isolation DC and AC Ground Isolation
n-well p-well
DC Ground
Substrate
Gate Ox Oxide p+ p p- n- n n+ Poly Salicide Polycide Metal 060405-05

What is a Ground?
Ground is simply another power supply whose value is supposed to be zero and is used as
a reference for all other voltages.
• DC ground is a point in the circuit where the DC voltage is supposed to be zero.
• AC ground is a point in the circuit where the AC voltage is supposed to be zero.
C2
AC Ground
t=0
- VDD
Vout DC and AC
Vin C1 +
Ground
AC Ground VSS
050305-03
Grounds that are Not Grounds

Because of the resistance of “wires”, current flowing through a wire can cause a voltage
drop.
Bad:
An example of good and bad Circuit Circuit Circuit
practice: A B C
R R R
IA IA+IB IA+IB+IC
Better:
Circuit Circuit Circuit
A B C IC
R
2R IB
3R IA
Best:
Circuit Circuit Circuit
A B C
R IA R IB R IC
050305-04

Kelvin Connections
Avoid unnecessary ohmic drops.
A B A B
X Y
Ohmic Connection Kelvin Connection 041223-12
In the left-hand connection, an IR drop is experienced between X and Y causing the

potentials at A and B to be slightly different.
For example, let the current be 100μA and the metal be 30m/sq. Suppose that the
distance between X and Y is 100 squares. Therefore, the IR drop is
100μA x 30m/sq. x 100sq. = 0.3mV
MODELING OF SUBSTRATE NOISE

How Do Carriers Get Injected into the Substrate?
1.) Hot carriers (substrate current)
2.) Electrostatic coupling (across depletion regions and other dielectrics)
3.) Electromagnetic coupling (parallel conductors)
Why is this a Problem?

With decreasing channel lengths, more circuitry is being integrated on the same substrate.
The result is that noisy circuits (circuits with rapid transitions) are beginning to adversely
influence sensitive circuits (such as analog circuits).
Present Solution
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.

Hot Carrier Injection in CMOS Technology without an Epitaxial Region

Noisy Circuits Quiet Circuits
VDD
VDD(Analog)
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground
n+ channel vout Analog Ground
stop (1 Ω-cm)
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
p+ channel stop (1Ω-cm)
n- well "AC ground"
Hot Back-gating due to a
iD
Carrier momentary change in
Put substrate connections reverse bias
as close to the noise source
as possible ΔiD
ID
"AC ground" ΔiD
vGS
p- substrate (10 Ω-cm) VGS
Heavily Lightly Intrinsic Lightly Heavily Metal Fig. SI-01

Doped p Doped p Doping Doped n Doped n
Hot Carrier Injection in CMOS Technology with an Epitaxial Region

Noisy Circuits Quiet Circuits
VDD
VDD(Analog)
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground vout Analog Ground
;;;;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
n- well "AC ground" p-epitaxial Reduced back

Put substrate Hot layer (15 Ω-cm) gating due to
connections Carrier smaller resistance
as close to the
noise source
as possible
"AC ground"
p+ substrate (0.05 Ω-cm)


Computer Model for Substrate Interference Using SPICE Primitives

Noise Injection Model:
VDD
;;
VDD
vin vout
L1
Cs1
n- well
Digital Ground VDD(Digital)
;;;;;;
;;;;;
vin vout
Cs3 Cs2
vin vout Rs1 Substrate
;;;;;;
;;;;;
Rs2
Rs3
p+ n+ n+ p+ p+ n+
n- well Cs4
;;;;;
Hot Cs5
Carrier Coupling
Hot
L2 L3
Carrier Coupling
Coupling
Cs1 = Capacitance between n-well and substrate

Cs2,Cs3 and Cs4 = Capacitances between interconnect lines
(including bond pads) and substrate
Cs5 = All capacitance between the substrate and ac ground
p- substrate
Rs1,Rs2 and Rs3 = Bulk resistances in n-well and substrate
L1,L2 and L3 = Inductance of the bond wires and package leads
Heavily Lightly Intrinsic Lightly Heavily Metal
Fig. SI-06
Computer Model for Substrate Interference Using SPICE Primitives

Noise Detection Model:
VDD(Analog)
;
RL Substrate Noise
vin vout
VGS VDD
VDD(Analog)
vin RL RL
vout
vout
;;;
VGS Analog Ground L4 CL
;;;
L6
n+ n+ p+
VGS
Cs6 Rs4 Cs7
Substrate
Cs5
L5
Cs5,Cs6 and Cs7 = Capacitances between interconnect lines

(including bond pads) and substrate
p- substrate Rs4 = Bulk resistance in the substrate
L4,L5 and L6 = Inductance of the bond wires and package leads
Other Sources of Substrate Injection

(We do it to ourselves and can’t blame the digital circuits.)
Inductor
Substrate BJT
;;;;;;;;
Collector Base Emitter Collector
n+ p+ n+ n+
p- well
Fig. SI-04
Heavily Lightly Intrinsic Lightly Heavily Metal
Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
Summary of Substrate Interference

• Methods to reduce substrate noise
1.) Physical separation
2.) Guard rings placed close to the sensitive circuits with dedicated package pins.
3.) Reduce the inductance in power supply and ground leads (best method)
4.) Connect regions of constant potential (wells and substrate) to metal with as many
contacts as possible.
• Noise Insensitive Circuit Design Techniques
1.) Design for a high power supply rejection ratio (PSRR)
2.) Use multiple devices spatially distinct and average the signal and noise.
3.) Use “quiet” digital logic (power supply current remains constant)
4.) Use differential signal processing techniques.
• Some references
1.) D.K. Su, M.J. Loinaz, S. Masui and B.A. Wooley, “Experimental Results and Modeling Techniques
for Substrate Noise in Mixed-Signal IC’s,” J. of Solid-State Circuits, vol. 28, No. 4, April 1993, pp. 420-
430.
2.) K.M. Fukuda, T. Anbo, T. Tsukada, T. Matsuura and M. Hotta, “Voltage-Comparator-Based
Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal ICs,” J. of Solid-
State Circuits, vol. 31, No. 5, May 1996, pp. 726-731.
3.) X. Aragones, J. Gonzalez and A. Rubio, Analysis and Solutions for Switching Noise Coupling in
Mixed-Signal ICs, Kluwer Acadmic Publishers, Boston, MA, 1999.

SECTION 3.5 – MATCHING OF COMPONENTS

INTRODUCTION
What is Accuracy and Matching?
The accuracy of a quantity specifies the difference between the actual value of the
quantity and the ideal or true value of the quantity.
The mismatch between two quantities is the difference between the actual ratio of the
quantities and the desired ratio of the two quantities.
Example:
x1 = actual value of one quantity
x2 = actual value of a second quantity
X1 = desired value of the first quantity
X2 = desired value of the second quantity
The accuracy of a quantity can be expressed as,
x - X X
Accuracy = X = X
x2 X 2
The mismatch, , can be expressed as,
x 1 - X 1 X 1x 2
= X 2 = X 2x 1 - 1
X1
Relationship between Accuracy and Matching

Let:
X1 = |x1 - X1| x1 = X 1 ± X 1
and
X2 = |x2 – X2| x2 = X 2 ± X 2
Therefore, the mismatch can be expressed as,
X2
X1(X2 ± X2) 1 ± X2
X2 X1
= X2(X1 ± X1) – 1 = -
X1 – 1 1 ± X2 1 + X1 – 1
1 ± X1
X2 X1 X2 X1

1 ± X2 +- X1 – 1 = ± X2 +- X1
Thus, the mismatch is approximately equal to the difference in the accuracies of x1 and x2
assuming the deviations (X) are small with respect to X.

Characterization of the Mismatch

Mean of the mismatch for N samples-
1 N
m = N i
i=1
Standard deviation of the mismatch for N samples-
1 N 2
s = N-1 (i - m)
10
Number of Samples
i=1
9
8
7
6
5
4
3
2
1
0 X
0 1 2 3 4 5 6 7 8 9 1011121314
041005-01
253
m = 40 = 6.325 s = 2.115
Motivation for Matching of Components

The accuracy of analog signal processing is determined by the accuracy of gains and time
constants. These accuracies are dependent upon:
Gain Ratios of components or areas
Time constants Products of components or areas
Ratio Accuracy?
X1
X1± X1 X1 1± X1 X1 X1 X2 X1 X1 X2
Actual Ratio = X2± X2 = X2 X2 X21± X1 1-+ X2 X21± X1 -+ X2
1± X2
If X1 and X2 match (X1/X1 X2/X2), then the actual ratio becomes the ideal ratio.
Product Accuracy?
X1 X2 X1 X2
Product accuracy = (X1±X1)(X2±X2) = X1X21± X1 1± X2 X1X21± X1 ± X2

Unfortunately, the product cannot be accurately maintained in integrated circuits.

Switched Capacitor Circuits

Switched capacitor circuits offer a solution to the product accuracy problem.
A switched capacitor replacement of a resistor:
φ1
φ2
T
Tc R1= c
φ1 φ2 C1
+ + + +
v1 C1 v2 v1 v2
− − − −
060316-06
The product of a resistor, R1, and a capacitor, C2, now become,

Tc 1 C2
R1C2 = C1 C2 = fcC1C2 = fcC1

The accuracy of the time constant (product) now becomes,

C2 C2 C1 fc
- -
fcC11± C2 + C1 + fc
Assuming the clock frequency is accurate and larger than the signal bandwidth, then time
constants in analog signal processing can be accurately matched by ratios of elements.
Types of Mismatches
1.) Those controlled or influenced by electrical design
- Transistor operation
- Circuit techniques
- Correction/calibration techniques
2.) Those controlled or influenced by physical design
- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)
- Pattern shift (misalignment)
- Diffusion interactions
- Stress gradients and package shifts
- Temperature gradients and thermoelectrics
- Electrostatic interactions

ELECTRICAL MATCHING
Matching Principle
Assume that two transistors are matched (large signal model parameters are equal). Then
if all terminal voltages of one transistor are equal to the terminal voltages of the other
transistor, then the terminal currents will be matched.
iC1 iC2 iD1 iD2
iB1 iB2
Q1 Q2 M1 M2
iE1 iE2
041005-02
Note that the terminals may be physically connected together or at the same potential but
not physically connected together.
Examples of the Matching Principle

iD1 iD2 iD1 iD2
M3 M4 iD1 iD2
M3 M4
+ M1 VB M2 + M1 M2
Vio Vio
VB M1 M2 - -
M5 M5
041005-03
Cascode current mirror:
The key transistors are M1 and M2. The gates and sources are physically connected
and the drains are equal due to M3 and M4 gate-source drops. As a result, iD1 will be
very close to iD2.
Differential amplifier:
When iD1 and iD2 are equal, the fact that the drains of M1 and M2 are equal should
give the smallest value of the input offset voltage, Vio.
Note: Since the drain voltages of M3 and M4 in both circuits are not necessarily equal,
the gate-source voltages of M3 and M4 are not exactly equal which cause the drain
voltages of M1 and M2 to not be exactly equal.
Gate-Source Matching
Not as precise as the previous principle but useful for biasing applications.
A. If the gate-source voltages of two or more FETs are iD1 iD2
equal and the FETs are matched and operating in the M1 M2
W2
W1
saturation region, then the currents are related by the W/L L + + L2
1
ratios of the individual FETs. The gate-source voltages vGS1 vGS2
may be directly or indirectly connected. - -
Fig. 290-02
K’W1 2K’iD1
iD1 = 2L1 (vGS1-VT1)2 (vGS1-VT1)2 = (W1/L1)
K’W2 2K’iD2 iD1
iD2 = 2L2 (vGS2-VT2)2 (vGS2-VT2)2 = (W2/L2) W1
+ L1
vGS1
W2

W1

W1/L1
-
If vGS1 = vGS2, then L2 iD1 = L1 iD2

or iD1 = W2/L2 iD2

iD2
M2
W2
B. If the drain currents of two or more transistors are equal and the trans- + L2
vGS2
istors are matched and operating in the saturation region, then the gate- -
Fig. 290-03
source voltages are related by the W/L ratios (ignoring bulk effects).
W2/L2 W2 W1
If iD1=iD2, then vGS1 = VT1+ W1/L1 (vGS2-VT2) or vGS1=vGS2 if L2 = L1
Process Independent Biasing - MOSFET

The sensitivity of the bias points of all transistors depend on both the variation of the
technological parameters and the accuracy of the biasing circuits.
Gate-source voltage decomposition:
The gate-source voltage of the MOSFET can be divided into two parts:
1.) The part necessary to form or enhance the channel, VT
2.) The part necessary to cause current to iD
10W/L W/L 0.1W/L
flow, VGS – VT = VON , called the
overdrive. ID
Form Provide
This overdrive can be expressed, Channel Current
2ID
VON = VDS(sat) = K’(W/L) 0
0 VT
vGS
VGS 041007-09
The dependence of the bias point on the

technology, VT, can be reduced by making VON = VDS(sat) >> VT.
This implies that small values of W/L are preferable. Unfortunately, this causes the
transconductance to reduce if the current remains the same.
Doubly Correlated Sampling

Illustration of the use of chopper stabilization to remove the undesired signal, vu, from
the desired signal, vin. In this case, the undesired signal is the gate leakage current.
Vu(f) Clock
+1
Vin(f) t
-1
f
vu T =1
fc
f vA vB vC vout
vin A1 A2
VA(f)
f
0 fc 2fc 3fc
VB(f)
f
0 fc 2fc 3fc
VC(f)
f
0 fc 2fc 3fc Fig. 7.5-8
An Op Amp Using Doubly Correlated Sampling to Remove DC Offsets

VDD
clkb clkb
M3 M4 R2
Inn clk clkb Inp
Inp Cc Inn
clk clkb clk clk
clk clk
Inn M1 M2 Inp
VDD VDD
Inp M5 Inn
R1
clkb clkb
051207-01
• Chopping with 50% duty cycle

• All switches use thick oxide devices to reduce gate leakage
• Gain gm1(rds2||rds4)gm5R2
Will examine further in low noise op amps.

Self-Calibration Techniques
The objective of self-calibration is to increase the matching between two or more
components (generally passive).
The requirements for self-calibration:
1.) A time interval in which to perform the calibration
2.) A means of adjusting the value of one or more of the components.
Fixed Comparison Adjustable

Component of values Component
041007-05
Self-calibration can typically improve the matching by a factor of 2-3 bits (4-8).
Example of Capacitor Self-Calibration

C1 C2
Consider the charge amplifier below that should have a gain vIN vOUT
of unity. -
+
041007-06
Assume the amplifier has a DC input offset voltage of Vio. The following shows how to
calibrate one (or both) of the capacitors.
C1 C2
vOUT vx -
+ - - - + +
vOUT
VRef -Vio Vio
+
+ - C1
VRef Vio C2 VRef VRef -Vio
- +
Vio Vio
Autozero Phase Calibration Phase 041007-07
In the calibration phase, vx, is:

C2 C1 C -C
2 1
vx = (VREF-Vio) C1+C2 - (VREF-Vio) C1+C2 = (VREF-Vio) C1+C2
The correction circuitry varies C1 or C2 until vx = 0 as observed by vOUT.
Variable Components
The correction circuitry should be controlled by logic circuits so that the correction can
be placed into memory to maintain the calibration of the circuit during application.
Implementation for C1 and C2 of the previous example:
C1 C1 C1 C1 C2 C2 C2 C2
C1 1- 1 2K 2K+1 2K+2 2N C2 1- 1 2K 2K+1 2K+2 2N
2K 2K
S1 S2 S3 SN S1 S2 S3 SN
Capacitor C1 Capacitor C2
041007-08
K is selected to achieve the desired tolerance or variation

N is selected to achieve the desired resolution (N > K)
Additional circuitry:
Every self-calibration system will need additional logic circuits to sense when the value
of vx changes from positive to negative (or vice versa) and to store the switch settings in
memory to maintain the calibration.
Basics of Dynamic Element Matching†

Dynamic element matching chooses different, approximately equal-valued elements to
represent a more precise value of a component as a function of time.
Goal of dynamic element matching:
Convert the error due to element mismatch from a dc offset into an ac signal of
equivalent power which can be removed by the appropriate means (doubly-correlated
sampling, highpass filtering of a sigma-delta modulator, etc.)
i
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
e t1
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 Tim
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
VRef
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
Tim S0 S1 S2 S3 S4 S5 S6 S7 S8 S9
e t2
All resistor are approximately equal
valued to within some tolerance
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
041010-01
†
L. R. Carley, “A Noise-Shaping Coder Topology for 15+ Bit Converters, IEEE J. of Solid-State Circuits, vol. 24, no. 2, April 1989, pp. 267-273.
How Dynamic Element Matching Works

Assume that we have three approximately equal elements with the following currents:
Element 1 = 0.99mA Element 2 = 1.03mA Element 3 = 0.98mA
Ideal Current (mA)

3
2
Ideal current output level 1
0 t
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Elements → 1 1 1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2 1,2,3
+2
Error (%)
Normal
Error when dynamic +1
element matching is not 0 t
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
used -1
Elements → 1 3 2 3 1 2 1,2 2,3 1,3 1,2 1,3 2,3 1,2,3
+3
Matching Error (%)
+2
Dynamic Element
Error when dynamic +1
element matching is used 0 t

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-1
-2
060405-06
-3
Issues of Dynamic Element Matching

• The selection of the elements must be truly random for the maximum benefit to occur.
• If the number of elements is large this can be an overwhelming task to implement. An
approximation to random selection is the butterfly-type randomizer below:
S1 S5 S9
0 0
Three-stage, eight-line
S1 S6 S10
butterfly randomizer. 1 1
Each pair of switches S2 S5 S11
2 2
marked with the same S2 S6 S12
label is controlled to 3 3
either exchange the S3 S7 S9
4 4
two signal lines or S3 S8 S10
pass them directly 5 5
S4 S7 S11
to the next stage. 6 6
S5 S8 S12
041010-03 7 7
• When using the dynamic element technique, one needs to be careful that the averaging
activity of the dynamic element matching process does not interfere with other
averaging processes that might be occurring simultaneously (i.e. modulators).
• Other references:
1.) B.H. Leung and s. Sutarja, “Multibit - A/D Converter Incorporating A Novel Class of Dynamic Element Matching
Techniques,” IEEE Trans. on Circuits and Systems-II, vol. 39, no. 1, Jan. 1992, pp. 35-51.
2.) R. Baird and T. Fiez, “Linearity Enhancement of Multibit - A/D and D/A Converters Using Data Weighted Averaging,”
IEEE Trans. on Circuits and Systems-II, vol. 42, no. 12, Dec. 1995, pp. 753-762.
PHYSICAL MATCHING
Review of Physical Matching
We have examined these topics in the previous chapter. To summarize, the sources of
physical mismatch are:
- Random statistical fluctuations (microscopic fluctuations and irregularities)
- Process bias (geometric variations)
- Pattern shift (misalignment)
- Diffusion interactions
- Stress gradients and package shifts
- Temperature gradients and thermoelectrics
- Electrostatic interactions
Rules for Resistor Matching†

1.) Construct matched resistors from the same material.
2.) Make matched resistors the same width.
3.) Make matched resistors sufficiently wide.
4.) Where practical, use identical geometries for resistors (replication principle)
5.) Orient resistors in the same direction.
6.) Place matched resistors in close physical proximity.
7.) Interdigitate arrayed resistors.
8.) Place dummy resistors on either end of a resistor array.
9.) Avoid short resistor segments.
10.) Connect matched resistors in order to cancel thermoelectrics.
11.) If possible place matched resistors in a low stress area (minimize pieozoresistance).
12.) Place matched resistors well away from power devices.
13.) Place precisely matched resistors on the axes of symmetry of the die.
†
Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
Rules for Resistor Matching – Continued

14.) Consider the influence of tank modulation for HSR resistors (the voltage modulation
of the reverse-biased depletion region changes the sheet resistivity).
15.) Sectioned resistors are superior to serpentine resistors.
16.) Use poly resistors in preference to diffused resistors.
17.) Do not allow the buried layer shadow to intersect matched diffused resistors.
18.) Use electrostatic shielding where necessary.
19.) Do not route unconnected metal over matched resistors.
20.) Avoid excessive power dissipation in matched resistors.
Rules for Capacitor Matching†

1.) Use identical geometries for matched capacitors (replication principle).
2.) Use square or octogonal geometries for precisely matched capacitors.
3.) Make matched capacitors as large as possible.
4.) Place matched capacitors adjacent to one another.
5.) Place matched capacitors over field oxide.
6.) Connect the upper electrode of a matched capacitor to the higher-impedance node.
7.) Place dummy capacitors around the outer edge of the array.
8.) Electrostatically shield matched capacitors.
9.) Cross-couple arrayed matched capacitors.
10.) Account for the influence of the leads connecting to matched capacitors.
11.) Do not run leads over matched capacitors unless they are electrostatically shielded.
12.) Use thick-oxide dielectrics in preference to thin-oxide or composite dielectrics.
13.) If possible, place matched capacitors in areas of low stress gradients.
14.) Place matched capacitors well away from power devices.
15.) Place precisely matched capacitors on the axes of symmetry for the die.
†
Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
Mismatched Transistors
Assume two transistors have vDS1 = vDS2, K1’ K2’ and VT1 VT2. Therefore we have
iO K2’(vGS - VT2)2
iI = K ’(v - V )2
1 GS T1
How do you analyze the mismatch? Use plus and minus worst case approach. Define
K’ = K’2-K’1 and K’ = 0.5(K2’+K1’) K1’= K’-0.5K’ and K2’= K’+0.5K’
VT = VT2-VT1 and VT = 0.5(VT1+VT2) VT1 =VT -0.5VT and VT2=VT+0.5VT
Substituting these terms into the above equation gives,

K’ VT 2
iO (K’+0.5K’)(vGS - VT - 0.5VT )2 1 + 2K’ 1 - 2(vGS-VT)

iI = (K’-0.5K’)(v - V + 0.5V )2 = K’ VT 2

GS T T 1 - 1 +
2K’ 2(vGS-VT)
Assuming that the terms added to or subtracted from “1” are smaller than unity gives
iO K’ K’ VT 2 VT 2 K’ 2 VT

iI 1 +
2K’ 1 + 1 - 1 -
2K’ 2(vGS-VT) 2(vGS-VT) 1 + -
K’ (vGS-VT)
If K’/K’ = ±5% and VT/(vGS-VT) = ±10%, then iO/iI 1 ± 0.05 ±(-0.20) = 1±(0.25)
Geometric Effects
How does the size and shape of the transistor effect its matching?
Gate Area:
CVth CKp CW/W
Vth = W L Kp = K’ W L W/W = WeffLeff
eff eff eff eff
where CVth, CKp and CW/W are constants determined by measurement.
Values from a 0.35μm CMOS technology:
10.6mV·μm 8.25mV·μm
Vth,NMOS = W L Vth,PMOS = W L
eff eff eff eff
and
W W
0.0056·μm 0.0011·μm
W NMOS = W L W PMOS = W L
eff eff eff eff
The above results suggest that PMOS devices would be better matched than NMOS
devices in this technology.

Rules for Transistor Matching†

1.) Use identical finger geometries.
2.) Use large active areas.
3.) For voltage matching, keep VGS-VT, small ( i.e. 0.1V).
4.) For current matching, keep VGS-VT, large (i.e. 0.5V).
5.) Orient the transistors in the same direction.
6.) Place the transistors in close proximity to each other.
7.) Keep the layout of the matched transistors as compact as possible.
8.) Where practical use common centroid geometry layouts.
9.) Place dummy segments on the ends of arrayed transistors.
10.) Avoid using very short or narrow transistors.
11.) Place transistors in areas of low stress gradients.
12.) Do not place contacts on top of active gate area.
13.) Keep junctions of deep diffusions as far away from the active gate area as possible.
14.) Do not route metal across the active gate region.
15.) Place precisely matched transistors on the axes of symmetry of the die.
16.) Do not allow the buried layer shadow to intersect the active gate area.
17.) Connect gate fingers using metal connections.
† Alan Hastings, Art of Analog Layout, 2nd ed, 2006, Pearson Prentice Hall, New Jersey
SECTION 3.6 – COMPUTER MODELS

FET Model Generations
• First Generation – Physically based analytical model including all geometry
dependence.
• Second Generation – Model equations became subject to mathematical conditioning for
circuit simulation. Use of empirical relationships and parameter extraction.
• Third Generation – A return to simpler model structure with reduced number of
parameters which are physically based rather than empirical. Uses better methods of
mathematical conditioning for simulation including more specialized smoothing
functions.
Performance Comparison of Models (from Cheng and Hu, MOSFET Modeling & BSIM3
Users Guide)
ModelMinimum Minimum Model iD Accuracy in iD Accuracy in Small signal Scalability
L (μm) Tox (nm) Continuity Strong Inversion Subthreshold parameter
MOS1 5 50 Poor Poor Not Modeled Poor Poor
MOS2 2 25 Poor Poor Poor Poor Fair
MOS3 1 20 Poor Fair Poor Poor Poor
BSIM1 0.8 15 Fair Good Fair Poor Fair
BSIM2 0.35 7.5 Fair Good Good Fair Fair
BSIM3v2 0.25 5 Fair Good Good Good Good
BSIM3v3 0.15 4 Good Good Good Good Good
First Generation Models

Level 1 (MOS1)
• Basic square law model based on the gradual channel approximation and the square law
for saturated drain current.
• Good for hand analysis.
• Needs improvement for deep-submicron technology (must incorporate the square law to
linear shift)
Level 2 (MOS2)
• First attempt to include small geometry effects
• Inclusion of the channel-bulk depletion charge results in the familiar 3/2 power terms
• Introduced a simple subthreshold model which was not continuous with the strong
inversion model.
• Model became quite complicated and probably is best known as a “developing ground”
for better modeling techniques.
Level 3 (MOS3)
• Used to overcome the limitations of Level 2. Made use of a semi-empirical approach.
• Added DIBL and the reduction of mobility by the lateral field.
• Similar to Level 2 but considerably more efficient.
• Used binning but was poorly implemented.
Second Generation Models

BSIM (Berkeley Short-Channel IGFET Model)
• Emphasis is on mathematical conditioning for circuit simulation
• Short channel models are mostly empirical and shifts the modeling to the parameter
extraction capability
• Introduced a more detailed subthreshold current model with good continuity
• Poor modeling of channel conductance
HSPICE Level 28
• Based on BSIM but has been extensively modified.
• More suitable for analog circuit design
• Uses model binning
• Model parameter set is almost entirely empirical
• User is locked into HSPICE
• Model is proprietary
BSIM2
• Closely based on BSIM
• Employs several expressions developed from two dimensional analysis
• Makes extensive modifications to the BSIM model for mobility and the drain current
• Uses a new subthreshold model
• Output conductance model makes the model very suitable for analog circuit design
Third Generation Models

BSIM2 – Continued
• The drain current model is more accurate and provides better convergence
• Becomes more complex with a large number of parameters
• No provisions for variations in the operating temperature
BSIM3
• This model has achieved stability and is being widely used in industry for deep
submicron technology.
• Initial focus of simplicity was not realized.
MOS Model 9
• Developed at Philips Laboratory
• Has extensive heritage of industrial use
• Model equations are clean and simple – should be efficient
Other Candidates
• EKV (Enz-Krummenacher-Vittoz) – fresh approach well suited to the needs of analog
circuit design
BSIM2 Model
Generic composite expression for the model parameters:
LX WX
X = Xo + Leff + Weff
where
Xo = parameter for a given W and L
LX (WX) = first-order dependence of X on L (W)
Modeling features of BSIM2:
Mobility
• Mobility reduction by the vertical and the lateral field
Drain Current
• Velocity saturation
• Linear region drain current
• Saturation region drain current
• Subthreshold current
μoCoxWeff kT evGS-Vt-Voff

1 - eqVDS/kT

iDS = Leff ·
q
n ·
where NB
Voff = VOF + VOFB ·vBS + VOFD ·vDS and n = NO + PHI - v + ND ·vDS
BS
BSIM2 Output Conductance Model

Rout Saturation
(DIBL) Substrate
Linear current
Region induced
(Triode) body
Drain effect
Channel current (SCBE)
length
modulation
(CLM)
0 vDS
0 vDS(sat) 5V
050829-01
• Drain-Induced Barrier Lowering (DIBL) – Lowering of the potential barrier at the

source-bulk junction allowing carriers to traverse the channel at a lower gate bias than
would otherwise be expected.
• Substrate Current-Induced Body Effect (SCBE) – The high field near the drain
accelerates carriers to high energies resulting in impact ionization which generates a
hole-electron pair (hot carrier generation). The opposite carriers are swept into the
substrate and have the effect of slightly forward-biasing the source-substrate junction.
This reduces the threshold voltage and increases the drain current.
Charge Model
• Eliminates the partitioning choice (50%/50% is used)
• BSIM charge model better documented with more options
BSIM2 Basic Parameter Extraction

• A number of devices with different W/L are fabricated and measured
Weff
9 10 11 12
Weff,3
5 6 7 8
Weff,2
1 2 3 4
Weff,1
Leff
Leff,1 Leff,2 Leff,3 Leff,4
• A long, wide device is used as the base to add geometry effects as corrections.
• Procedure:
1.) Oxide thickness and the differences between the drawn and effective channel
dimensions are provided as process input.
2.) A long, wide device is used to determine some base parameters which are used as
the starting point for each individual device extraction in the second phase.
3.) In the second phase, a set of parameters is extracted independently for each device.
This phase represents the fitting of the data for each independent device to the intrinsic
equation structure of the model
4.) In the third phase, the compiled parameters from the second phase are used to
determine the geometry parameters. This represents the imposition of the extrinsic
structure onto the model.
BSIM2 Model used in Subthreshold

BSIM Model Parameters used in Subthreshold
VDS 1 0 DC 3.0
M1 1 1 0 0 CMOSN W=5UM L=2UM
.MODEL CMOSN NMOS LEVEL=4
+VFB=-7.92628E-01 LVFB= 1.22972E-02 WVFB=-1.00233E-01
+PHI= 7.59099E-01 LPHI= 0.00000E+00 WPHI= 0.00000E+00
+K1= 1.06705E+00 LK1= 5.08430E-02 WK1= 4.72787E-01
+K2=-4.23365E-03 LK2= 6.76974E-02 WK2= 6.27415E-02
+ETA=-4.30579E-03 LETA= 9.05179E-03 WETA= 7.33154E-03
+MUZ= 5.58459E+02 DL=6.86137E-001 DW=-1.04701E-001
+U0= 5.52698E-02 LU0= 6.09430E-02 WU0=-6.91423E-02
+U1= 5.38133E-03 LU1= 5.43387E-01 WU1=-8.63357E-02
+X2MZ= 1.45214E+01 LX2MZ=-3.08694E+01 WX2MZ= 4.75033E+01
+X2E=-1.67104E-04 LX2E=-4.75323E-03 WX2E=-2.74841E-03
+X3E= 5.33407E-04 LX3E=-4.69455E-04 WX3E=-5.26199E-03
+X2U0= 2.45645E-03 LX2U0=-1.46188E-02 WX2U0= 2.63555E-02
+X2U1=-3.80979E-04 LX2U1=-1.71488E-03 WX2U1= 2.23520E-02
+MUS= 5.48735E+02 LMUS= 3.28720E+02 WMUS= 1.35360E+02
+X2MS= 6.72261E+00 LX2MS=-3.48094E+01 WX2MS= 9.84809E+01
+X3MS=-2.79427E+00 LX3MS= 6.31555E+01 WX3MS=-1.99720E-01
+X3U1= 1.18671E-03 LX3U1= 6.13936E-02 WX3U1=-3.49351E-03
+TOX=4.03000E-002 TEMP= 2.70000E+01 VDD= 5.00000E+00
+CGDO=4.40942E-010 CGSO=4.40942E-010 CGBO=6.34142E-010
+XPART=-1.00000E+000
+N0=1.00000E+000 LN0=0.00000E+000 WN0=0.00000E+000
+NB=0.00000E+000 LNB=0.00000E+000 WNB=0.00000E+000
+ND=0.00000E+000 LND=0.00000E+000 WND=0.00000E+000
+RSH=0 CJ=4.141500e-04 CJSW=4.617400e-10 JS=0 PB=0.8
+PBSW=0.8 MJ=0.4726 MJSW=0.3597 WDF=0 DELL=0
.DC VDS 5.0 0 0.01
.PRINT DC ID(M1)
.PROBE
.END
Results of the BSIM2 Model Simulation in Subthreshold
100μA
10μA iD +
vGS
1μA -
ID(M1)
100nA
10nA
1nA
100pA
0V 0.4V 0.8V 1.2V 1.6V 2V
VGS

BSIM3 Model
The background for the BSIM3 model and the equations are given in detail in the text
MOSFET Modeling & BSIM3 User’s Guide, by Y. Cheng and C. Hu, Kluwer Academic
Publishers, 1999.
The short channel effects included in the BSIM3 model are:
• Normal and reverse short-channel and narrow-width effects on the threshold.
• Channel length modulation (CLM).
• Drain induced barrier lowering (DIBL).
• Velocity saturation.
• Mobility degradation due to the vertical electric field.
• Impact ionization.
• Band-to-band tunnelling.
• Velocity overshoot.
• Self-heating.
1.) Channel quantization.
2.) Polysilicon depletion.
BSIM3v3 Model Equations for Hand Calculations

In strong inversion, approximate hand equations are:
Weff 1
AbulkvDS
iDS = μeffCox Leff v -V
vDS GS th - 2 vDS , vDS < VDS(sat)
1+ EsatLeff

vDS - VDS(sat)
iDS = WeffvsatCox[vGS – Vth – AbulkVDS(sat)]1+ VA ,
vDS > VDS(sat)
where
EsatLeff(vGS-Vth)
VDS(sat) = AbulkEsatLeff + (vGS-Vth)
Leff = Ldrawn – 2dL
Weff = Wdrawn – 2dW
Esat = Electric field where the drift velocity (v) saturates
vsat = saturation velocity of carriers in the channel
μeff 2vsat
μ = 1+(Ey/Esat) μeff = Esat
Note: Assume Abulk 1 and extract Vth and VA.

MOSIS Parametric Test Results

http://www.mosis.org/
RUN: T02D VENDOR: TSMC
TECHNOLOGY: SCN025 FEATURE SIZE: 0.25 microns
INTRODUCTION: This report contains the lot average results obtained by MOSIS from measurements of
MOSIS test structures on each wafer of this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.
COMMENTS: TSMC 0251P5M.
TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS
MINIMUM 0.36/0.24
Vth 0.54 -0.50 volts
SHORT 20.0/0.24
Idss 557 -256 uA/um
Vpt 7.6 -7.2 volts
WIDE 20.0/0.24
Ids0 6.6 -1.5 pA/um
LARGE 50.0/50.0
Vjbkd 5.8 -7.0 volts
Ijlk -25.0 -1.1 pA
Gamma 0.44 0.61 V0.5
K’ (Uo*Cox/2) 112.0 -23.0 uA/V2
0.25μm BSIM3v3.1 NMOS Parameters

.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.4273342
+K1 = 0.3922983 K2 = 0.0185825 K3 = 1E-3
+K3B = 2.0947677 W0 = 2.171779E-7 NLX = 1.919758E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 7.137212E-3 DVT1 = 6.066487E-3 DVT2 = -0.3025397
+U0 = 403.1776038 UA = -3.60743E-12 UB = 1.323051E-18
+UC = 2.575123E-11 VSAT = 1.616298E5 A0 = 1.4626549
+AGS = 0.3136349 B0 = 3.080869E-8 B1 = -1E-7
+KETA = 5.462411E-3 A1 = 4.653219E-4 A2 = 0.6191129
+RDSW = 345.624986 PRWG = 0.3183394 PRWB = -0.1441065
+WR =1 WINT = 8.107812E-9 LINT = 3.375523E-9
+XL = 3E-8 XW = 0 DWG = 6.420502E-10
+DWB = 1.042094E-8 VOFF = -0.1083577 NFACTOR = 1.1884386
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 4.914545E-3 ETAB = 4.215338E-4
+DSUB = 0.0313287 PCLM = 1.2088426 PDIBLC1 = 0.7240447
+PDIBLC2 = 5.120303E-3 PDIBLCB = -0.0443076 DROUT = 0.7752992
+PSCBE1 = 4.451333E8 PSCBE2 = 5E-10 PVAG = 0.2068286
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL =0
+WLN = 1 WW = -1.22182E-16 WWN = 1.2127
+WWL = 0 LL =0 LLN = 1
+LW =0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 6.33E-10
+CGSO = 6.33E-10 CGBO = 1E-11 CJ = 1.766171E-3
+PB = 0.9577677 MJ = 0.4579102 CJSW = 3.931544E-10
+PBSW = 0.99 MJSW = 0.2722644 CF =0
+PVTH0 = -2.126483E-3 PRDSW = -24.2435379 PK2 = -4.788094E-4
+WKETA = 1.430792E-3 LKETA = -6.548592E-3 )
0.25μm BSIM3v3.1 PMOS Parameters

MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 5.7E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.6193382
+K1 = 0.5275326 K2 = 0.0281819 K3 =0
+K3B = 11.249555 W0 = 1E-6 NLX = 1E-9
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 3.1920483 DVT1 = 0.4901788 DVT2 = -0.0295257
+U0 = 185.1288894 UA = 3.40616E-9 UB = 3.640498E-20
+UC = -6.35238E-11 VSAT = 1.975064E5 A0 = 0.4156696
+AGS = 0.0702036 B0 = 3.111154E-6 B1 = 5E-6
+KETA = 0.0253118 A1 = 2.421043E-4 A2 = 0.6754231
+RDSW = 866.896668 PRWG = 0.0362726 PRWB = -0.293946
+WR =1 WINT = 6.519911E-9 LINT = 2.210804E-8
+XL = 3E-8 XW = 0 DWG = -2.423118E-8
+DWB = 3.052612E-8 VOFF = -0.1161062 NFACTOR = 1.2546896
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.7241245 ETAB = -0.3675267
+DSUB = 1.1734643 PCLM = 1.0837457 PDIBLC1 = 9.608442E-4
+PDIBLC2 = 0.0176785 PDIBLCB = -9.605935E-4 DROUT = 0.0735541
+PSCBE1 = 1.579442E10 PSCBE2 = 6.707105E-9 PVAG = 0.0409261
+DELTA = 0.01 MOBMOD = 1 PRT = 0
+UTE = -1.5 KT1 = -0.11 KT1L = 0
+KT2 = 0.022 UA1 = 4.31E-9 UB1 = -7.61E-18
+UC1 = -5.6E-11 AT = 3.3E4 WL =0
+WLN = 1 WW =0 WWN = 1
+WWL = 0 LL =0 LLN = 1
+LW =0 LWN = 1 LWL = 0
+CAPMOD = 2 XPART = 0.4 CGDO = 5.11E-10
+CGSO = 5.11E-10 CGBO = 1E-11 CJ = 1.882953E-3
+PB = 0.99 MJ = 0.4690946 CJSW = 3.018356E-10
+PBSW = 0.8137064 MJSW = 0.3299497 CF =0
+PVTH0 = 5.268963E-3 PRDSW = -2.2622317 PK2 = 3.952008E-3
+WKETA = -7.69819E-3 LKETA = -0.0119828 )
Summary of MOSFET Models for Simulation

• Models are much improved for efficient computer simulation
• Output conductance model is greatly improved
• Poor results for narrow channel transistors
• Can have discontinuities at bin boundaries
• Fairly complex model, difficult to understand in detail

SECTION 3.7 – EXTRACTION OF A LARGE SIGNAL MODEL FOR

HAND CALCULATIONS
Objective
Extract a simple model that is useful for design from the computer models such as
BSIM3.
Extraction for Short Channel Models
Procedure for extracting short channel models:
1.) Extract the square-law model parameters for a transistor with length at least 10
times Lmin.
2.) Using the values of K’, VT , , and extract the model parameters for the following
model:
K’ W
iD = 2[1 + (vGS-VT)] L [ vGS – VT]2(1+vDS)
Adjust the values of K’, VT , and as needed.
Illustration of the Extraction Procedure

Computer Model for ID
your technology
VGS
VBS
Choose L
Extract VT0, K', λ, γ and φ using the

simulator for the simple model
Initial guesses for VT0, K', λ, γ and φ
Use the appropriate optimization routine to find θ
and the new values for VT0, K', λ, γ and for the model
K' W
iD = (v - V 2
2[1 + θ(vGS - VT)] L GS T) (1 + λvDS)
04629-02

EXTRACTION OF THE SIMPLE, SQUARE-LAW MODEL

Characterization of the Simple Square-Law Model
Equations for the MOSFET in strong inversion:
Weff
iD = K’
(v - V ) 2(1 + v ) (1)
2Leff GS T DS
Weff v
2
iD = K’
(v - V )v - DS (1 + v ) (2)
Leff GS T DS 2 DS
where
VT = VT0 + [ 2|F| + vSB 2|F| ] (3)
Extraction of Model Parameters:

First assume that vDS is chosen such that the vDS term in Eq. (1) is much less than one
and vSB is zero, so that VT = VT0.
Therefore, Eq. (1) simplifies to
W
eff
iD = K’2Leff (vGS - VT0) 2 (4)
This equation can be manipulated algebraically to obtain the following
K' W K' W
1/2 eff1/2 eff1/2
iD = 2Leff vGS = 2Leff VT0 (5)
which has the form
y = mx + b (6)
This equation is easily recognized as the equation for a straight line with m as the slope
and b as the y-intercept. Comparing Eq. (5) to Eq. (6) gives
1/2
y = iD (7)
x = vGS (8)
K' W
eff1/2
m = 2Leff
and
K' W

eff1/2
b = - 2L

eff
VT0 (10)
Illustration of K’ and VT Extraction

1/2
(iD) Mobility degradation
region
vDS >VDSAT
Weak inversion
region 1/2
⎛ K ′ Weff ⎞
m= ⎜⎝ ⎟
2L eff ⎠
0 vGS
0 b′ =VT0 AppB-01
Comments:
• Stay away from the extreme regions of mobility degradation and weak inversion
• Use channel lengths greater than Lmin
Example 3.7-1 – Extraction of K’ and VT Using Linear Regression

Given the following transistor data shown in Table 3.7-1 and linear regression formulas
based on the form,
y = mx + b (11)
and
xi yi - ( xi yi)/n
m= 2 (12)
xi - (xi)2/n
1/2
determine VT0 and K’W/2L. The data in Table 3.7-1 also give ID as a function of VGS.
Table 3.7-1 Data for Example 3.7-1
VGS (V) ID (μA) ID (μA)1/2 VSB (V)

1.000 0.700 0.837 0.000
1.200 2.00 1.414 0.000
1.500 8.00 2.828 0.000
1.700 13.95 3.735 0.000
1.900 22.1 4.701 0.000

Example 3.7-1 – Continued

Solution
The data must be checked for linearity before linear regression is applied. Checking
slopes between data points is a simple numerical technique for determining linearity.
Using the formula that
y ID2 - ID1
Slope = m = =
x VGS2 - VGS1
Gives
1.414 - 0.837 2.828 - 1.414
m1 = 0.2 = 2.885 m2 = 0.3 = 4.713
3.735 - 2.828 4.701 - 3.735

m3 = 0.2 = 4.535 m4 = 0.2 = 4.830
These results indicate that the first (lowest value of VGS) data point is either bad, or at a
point where the transistor is in weak inversion. This data point will not be included in
subsequent analysis. Performing the linear regression yields the following results.
K'Weff
VT0 = 0.898 V 2
and 2Leff = 21.92 μA/V
Extraction of the Bulk-Threshold Parameter

Using the same techniques as before, the following equation
VT = VT0 + [ 2|F| + vSB 2|F| ]
is written in the linear form where
y = VT
x = 2|F| + vSB 2|F| (13)
m=
b = VT0
The term 2|F| is unknown but is normally in the range of 0.6 to 0.7 volts.
Procedure:
1.) Pick a value for 2|F|.
2.) Extract a value for .
2si q NSUB
3.) Calculate NSUB using the relationship, = Cox
kT NSUB
4.) Calculate F using the relationship, F = q ln ni
5.) Iterative procedures can be used to achieve the desired accuracy of and 2|F|.
Generally, an approximate value for 2|F| gives adequate results.

Illustration of the Procedure for Extracting

A plot of iD versus vGS for different values of vSB used to determine is shown below.
(iD)1/2
vGS
VT0 VT1 VT2 VT3
FigAppB-02
By plotting VT versus x of Eq. (13) one can measure the slope of the best fit line from
which the parameter can be extracted. In order to do this, VT must be determined at
various values of vSB using the technique previously described.
Illustration of the Procedure for Extracting - Continued

Each VT determined above must be plotted against the vSB term. The result is shown
below. The slope m, measured from the best fit line, is the parameter .
VSB =3V
VSB =2V
VT
VSB =1V m= γ
VSB =0V
0.5 0.5
(vSB +2 φF ) − (2 φF ) FigAppB-03

Example 3.7-2 – Extraction of the Bulk Threshold Parameter

Using the results from Ex. 3.7-1 and the following transistor data, determine the value of
using linear regression techniques. Assume that 2|F| is 0.6 volts.
Table 3.7-2 Data for Example 3.7-2.
VSB (V) VGS (V) ID (μA)
1.000 1.400 1.431
1.000 1.600 4.55
1.000 1.800 9.44
1.000 2.000 15.95
2.000 1.700 3.15
2.000 1.900 7.43
2.000 2.10 13.41
2.000 2.30 21.2
Solution
Table 3.7-2 shows data for VSB = 1 volt and VSB = 2 volts. A quick check of the data in
this table reveals that ID versus VGS is linear and thus may be used in the linear
regression analysis. Using the same procedure as in Ex. 3.7-1, the following thresholds
are determined: VT0 = 0.898 volts (from Ex. 3.7-1), VT = 1.143 volts (@VSB = 1 V), and VT
= 1.322 V (@VSB = 2 V). Table 3.7-3 gives the value of VT as a function of [(2|F| +
VSB)1/2 (2|F|)1/2 ] for the three values of VSB.
Example 3.7-2 - Continued

VSB (V) [ 2|F| + VSB - 2|F| ] (V1/2)

VT (V)
0.000 0.898 0.000
1.000 1.143 0.490
2.000 1.322 0.838
With these data, linear regression must be performed on the data of VT versus [(2|F| +
VSB)0.5 (2|F |)0.5]. The regression parameters of Eq. (12) are
xiyi = 1.668
xiyi = 4.466
2
xi = 0.9423
(xi)2 = 1.764
These values give m = 0.506 = .

Extraction of the Channel Length Modulation Parameter,

The channel length modulation parameter should be determined for all device lengths
that might be used. For the sake of simplicity, Eq. (1) is rewritten as
iD = i'D=' vDS + i'D
which is in the familiar linear form where
y = iD (Eq. (1))
x = vDS
m = i'D
b = i'D (Eq. (1) with = 0) iD
By plotting iD versus vDS, measuring the Saturation region

Nonsaturation
slope of the data in the saturation region, region
and dividing that value by the y-intercept, i'D m = λ i'D
can be determined. The procedure is
illustrated in the figure shown.
vDS
AppB-03
Example 3.7-3 – Extraction of the Channel Length Modulation Parameter

Given the data of ID versus VDS in Table 3.7-4, determine the parameter .
ID (μA) 39.2 68.2 86.8 94.2 95.7 97.2 98.8 100.3
VDS (V) 0.500 1.000 1.500 2.000 2.50 3.00 3.50 4.00
Solution
We note that the data of Table 3.7-4 covers both the saturation and nonsaturation regions
of operation. A quick check shows that saturation is reached near VDS = 2.0 V. To
calculate , we shall use the data for VDS greater than or equal to 2.5 V. The parameters of
the linear regression are
xiyi = 1277.85 xiyi = 5096.00
x2i = 43.5 (xi)2 = 169
These values result in m = I'D = 3.08 and b = I'D = 88, giving = 0.035 V-1.
The slope in the saturation region is typically very small, making it necessary to be
careful that two data points taken with low resolution are not subtracted (to obtain the
slope) resulting in a number that is of the same order of magnitude as the resolution of
the data point measured. If this occurs, then the value obtained will have significant and
unacceptable error.
EXTRACTION OF THE SIMPLE MODEL FOR SHORT CHANNEL MOSFETS

Extraction for Short Channel MOSFETS
The model proposed is the following one which is the square-law model modified by
the velocity saturation influence.
K’ W
iD = 2[1 + (vGS-VT)] L [ vGS - VT]2(1+vDS)
Using the values of K’, VT , , and extracted previously, use an appropriate extraction
procedure to find the value of adjusting the values of K’, VT , and as needed.
Comments:
• We will assume that the bulk will be connected to the source or the standard
relationship between VT and VBS can be used.
• The saturation voltage is still given by
VDS( sat) = VGS - VT
Example of a Genetic Algorithm†

1.) To use this algorithm or any other, use the simulator and an appropriate short-channel
model (BSIM3) to generate a set of data for the transconductance (iD vs. vGS) and
output characteristics (iD vs. vDS) of the transistor with the desired W and L values.
2.) The best fit to the data is found using a genetic algorithm. The constraints on the
parameters are obtained from experience with prior transistor parameters and are:
10E-6 < < 610E-6, 1 < < 5, 0 < VT < 1, and 0 < < 0.5
3,) The details of the genetic algorithm are:
Gene structure is A = [, , VT, fitness]. A mutation was done by varying all four
parameters. A weighted sum of the least square errors of the data curves was used as
the error function. The fitness of a gene was chosen as 1/error.
4.) The results for an extraction run of 8000 iterations for an NMOS transistor is shown
below.
(A/V2) VT(V) (V-1)
294.1x10-6 1.4564 0.4190 0.1437
5.) The results for a NMOS and PMOS transistor are shown on the following pages.
†
Anurag Kaplish, “Parameter Optimization of Deep Submicron MOSFETS Using a Genetic Algorithm,” May 4, 2000, Special Project Report,
School of ECE, Georgia Tech.
Extraction Results for an NMOS Transistor with W = 0.32μm and L = 0.18μm

Transconductance:
Extraction Results for an NMOS Transistor with W = 0.32μm and L = 0.18μm

Output:

Extraction Results for an PMOS Transistor with W = 0.32μm and L = 0.18μm

Transconductance:
Extraction Results for an PMOS Transistor with W = 0.32μm and L = 0.18μm

Output:

SECTION 3.8 - SUMMARY

• Model philosophy for analog IC design
Use simple models for design and sophisticated models for verification
• Models have several parts
Large signal static (dc variables)
Small signal static (midband gains, resistances)
Small signal dynamic (frequency response, noise)
Large signal dynamic (slew rate)
• In addition models may include:
Temperature
Noise
Process variations (Monte Carlo methods)
• Computer models
Must be numerically efficient
Quickly derived from new technology
• Analog Design “Tricks”
Stay away from minimum channel length if possible
- Larger rds larger gains
- Better agreement
Don’t use the computer models for design, rather verification of design

Chapter 3 - Models For Cmos Components

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Chapter 3 – Introduction (12/20/06) Page 3.

CHAPTER 3 – MODELS FOR CMOS COMPONENTS

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Introduction (12/20/06) Page 3.0-2

Models Suitable for Understanding Analog Design

Updating Model Thinking Model Updating Technology

Comparison of Design Decisions- Extraction of Simple

Categorization of Electrical Models

Linear Small-signal, midband Small-signal frequency

Nonlinear DC operating point Large-signal transient

Based on the simulation capabilities of SPICE.

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-1

SECTION 3.1 – LARGE SIGNAL TRANSISTOR MOSFET MODELS

Strong Threshold (VG>VT)

p- substrate Inverted Region

CMOS Analog Circuit Design Fig.3.1-02 © P.E. Allen - 2006

Transconductance Characteristics of an Enhancement NMOSFET when VDS = 0.1V

p- substrate Inverted Region

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-3

Output Characteristics of the Enhancement NMOS Transistor for VGS = 2VT

CMOS Analog Circuit Design © P.E. Allen - 2006

Output Characteristics of the Enhanced NMOS when vDS = 2VT

Chapter 3 – Section 1 (12/20/06) Page 3.1-5

Output Characteristics of an Enhancement NMOS Transistor

Transconductance Characteristics of an Enhancement NMOS Transistor

Chapter 3 – Section 1 (12/20/06) Page 3.1-7

CMOS Analog Circuit Design © P.E. Allen - 2006

Saturation Voltage - VDS(sat) iD

Chapter 3 – Section 1 (12/20/06) Page 3.1-9

The Simple Large Signal MOSFET Model

CMOS Analog Circuit Design © P.E. Allen - 2006

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-11

Modification of the Previous Model to Include the Effects of vDS on VT

Influence of VDS on the Output Characteristics

Note that Leff = L - Xd p- substrate Xd

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-13

Channel Length Modulation Parameter,

Influence of Channel Length on

Channel Length Modulation (V-1)

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-15

Influence of the Bulk Voltage on the Large Signal MOSFET Model

+ voltage to offset the channel-bulk VSB1 > 0: VBS1 > 0V VGS

We know that VSB2 >VSB1: VSB2 >VSB1: VGS

Therefore, as the bulk becomes more p+ n+ n+

VT(vBS) = VT0 + 2|f| + |vBS| - 2|f|

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-17

Summary of the Simple Large Signal MOSFET Model D

Constant Constant Description Value Units

CMOS Analog Circuit Design © P.E. Allen - 2006

Chapter 3 – Section 1 (12/20/06) Page 3.1-19

Parameter Typical Parameter Value Units

CMOS Analog Circuit Design © P.E. Allen - 2006

Therefore, the drain current due to diffusion is,

where X is the thickness of the region in which iD flows.

Chapter 3 – Section 1 (12/20/06) Page 3.1-21

Large-Signal Model for Weak Inversion – Continued

JD = JS = W = QI(y)vd(y) iD = WQI(y)vd(y) = 1 + E/Ec iD 1+ Ec

dIs 3KT 3 Go qKT 3VGo Go 3Is Is VGo