Welcome

to my second year course on Digital Electronics. You will nd that It is important for you to know at this stage what you are expected to learn (learning
the slides are supported by notes embedded with the Powerpoint outcome) from this module. Learning outcomes specify WHAT you should be able to do as a
result of taking this module. Let me go through the listed outcomes in some details:
presenta<ons. All my teaching materials are also available on the course
1. Understand synchronous digital systems if you are given a circuit with gates and
webpage: www.ee.ic.ac.uk/pcheung/teaching/ee2_digital/. I will be ip-ops, you should know how to predict how it behaves. For example, you should
upda<ng the notes, the laboratory instruc<ons and tutorial problem sheets be able to draw the <ming diagrams for output signals given the input s<muli, or write
each week aFer the lectures. down the sequence of states that the circuit must go through.
2. Design circuits to meet specica<on In real circuits, outputs response to changes in
inputs aFer some delay. In order for a digital circuit to work as intended, such delay
The course consists of about 16 hours lectures interleaved with 8 problem
must be taken into account, and you as a deign engineer must be sure that there are
solving classes. These will be held on Tuesday 4pm to 6pm and Wednesday no <ming viola<ons (i.e. circuit delays causing the circuit to fail).
10am to 11am. However, due to overseas commitment for the College, I will 3. A/D and D/A conversions the physical world is generally analogue in nature and is
not be giving classes on these days: 21-22 October 2014 and 28-29 October. not just 1s and 0s. However, electronic systems are increasingly manifest
There are NO classes from me during these two weeks. themselves as digital circuits. Analogue to Digital (A/D) and Digital to Analogue (D/A)
conversion provides the linkage between the analogue real work, and the digital
electronics world. You need to understand HOW analogue signals are converted to
This course follows on from the rst year Digital Electronics I course. Unlike digital, and how to interpret the datasheet of such components.
the rst year course where all gates and ip-ops are assumed to exhibit 4. Finite State Machines Designing digital circuits involve understanding of various
ideal behaviour, this course will teach you about real-life circuits. elds, and one of the eld of study is known as Finite State Machines (FSM). This is a
systema<c ways of thinking how a digital system goes through dierent states, and as
a result, control the opera<on of a digital sub-system.
Digital circuits are ubiquitous. For example, there are more electronic
5. Field Programmable Gate Arrays FPGAs is one of the primary technology for
modules in cars these days than mechanical systems. A mobile has more implemen<ng digital circuits nowadays. This has replaced most of the
transistors than human alive on earth, and most of these transistor are implementa<ons in discrete logic (such as 16-pin packaged TTL or CMOS gates). It
digital, i.e. working as on-o switches. Therefore this second year digital has also replaced many Applica<on Specic Integrated Circuits (ASICs) that the
electronics course is fundamental to any EEE or EIE educa<on. industry used to design. FPGAs prove to be much lower-risk and must easier to design
as compared to other approaches. Therefore this course will be based around the use
of FPGAs. (to con<nue ..)

1 2
6. Verilog HDL While you mostly use schema<c diagrams to describe your The prac<cal aspects of this course module is based around a FPGA board,
digital designs last year, you will ABANDON this in favour of a computer the DE0. There should be enough DE0 board, one for EACH PAIR of students
language to specify and design your digital circuits. You may nd this odd (in Laboratory Group) to use throughout the Autumn Term, or even
ini<ally because diagrams are generally more intui<ve than a computer throughout the YEAR! Bring your ID Card to Level 1 store, and you can check
language. However, using a Hardware Descrip<on Language (HDL as it is
out a board. But you must return it before you complete your Second Year,
called), and in our case, using Verilog, is the ONLY way that modern digital
systems are specied and designed. No maier whether you like
otherwise you will need to pay for a replacement. DO NOT TAKE MORE
programming or not, as a electronic engineer, you will have no choice but to THAN ONE per laboratory partnership. Share between the two of you.
learn such a language.
This course will be assessed through an examina<on paper in June 2016. There will This board has everything you need to do the experiment and MORE. It
also be an associated E2 Laboratory Experiment VERI. consists of a Cyclone III FPGA (which I will explain in more details in a later
The Laboratory Experiment is EXTREMELY IMPORTANT in helping you to learn this lecture). It has various input and output devices.
subject. It is designed to teach you how to design digital circuits using the Verilog
HDL targe<ng implementa<ons on FPGAs. The Lab sessions will run for FOUR weeks
star<ng on the 16th of November, and assessment for this experiment will take place
in the last week of term (star<ng 14th of December). You will also be provided with
an experimental board to use at home and at your leisure, one sharing between two
people in the same lab group..
There are three recommended textbook Fundamental of Digital Logic with Verilog
Design 3/e by Stephen Brown and Zvonko Vranesic. Unfortunately this book is in
short supply and is extremely expensive to buy new. You may be able to pick up a
second hand copy on the internet. Another possible book but less relevant is by
Dally and Har<ng. While it is NOT necessary to own a textbook for my course because I do
not follow a par<cular textbook in my lectures or in the lab, I would recommend you to get
hold of a second hand copy or an eBook in digital as a reference. The third book, also not
compulsory, is Verilog by Example: A concise introduc<on for FPGA Design by Blaine Readler.

3 4
This is the current lecture plan for the course. Details may change as we This lecture is just partly a revision lecture, and I also want to introduce you
progress through the term. There will be around 16 lectures (slightly higher to alterna<ve nota<ons used both in the notes and in some textbooks. This
than the nominal 15 lecture modules). I will cover a number of topics that follows the IEEE standard for digital schema<cs.
form the basic course in digital electronics. By the end of the course, you
should be able to independently design digital circuits using Altera FPGAs. Instead of using curves for gates, one could use rectangular blocks and a
symbol to denote the logic func<on. Inversion could be on the input or
output terminal. Instead of a circle, we could use a small triangle as shown
here.

IEEE publishes the standards, and there is an excellent tutorial on this digital
circuit nota<ons published by Texas Instrument (see the course webpage).

5 6
All digital circuits exhibit propaga<on delay. Here it shows the delay table for We use the IEEE standards for the symbol here. C mean clock input, the
a discrete logic CMOS NAND gate. The delay could be in the region of number 1 is a numerical label (as clock 1). D is for data input, and 1D means
nanoseconds. However, with the FPGA chips we use has an internal gate this input responsible to the control of input 1. Q is the ipop output.
propaga<on delay of approximately 100ps, which is much faster than
discrete logic. As can be seen later, the gate is also much more complex
than a simple NAND gate.

Also note that propaga<on delay depends on the cause (input rising or
falling) and the eect (output rising or falling). As can be seen in the
example here, the rising edge A to falling edge X delay is lower than that of A
falling to X rising.

Note that I use an arrow to indicate the cause (the blunt end) and the eect
(the pointed end) in a <ming diagram.

7 8
Timing and delay parameters for ipop is dierent from that with gates. You learned about various types of Flipops last year. Actually all you need is
Shown here is a D-ipop that responses to a rising edge on the clock signal. ONE type of ipop the D-ipop. Here is an example of a D-ipop used
A D-ipop is like a camera, taking a picture from the scene (input is D). in a ripple counter.
The clock input C1 is like the trigger on the camera when pressed it samples
the input and take a picture. The cause here is the rising edge of the CLOCK Q0 values is rst inverted (represented by the triangle) and then used a D
and the eect is the Q output sampling the D input, and keep the value un<l input on the next clock cycle. The ipop is triggered on the FALLING edge of
the next rising edge of the clock. CLOCK. Therefore the Q output TOGGLES on each ac<ve edge of the clock
(i.e. falling edge). Q0 is therefore changing a half the rate of CLOCK, hence
The delay here is from CLOCK rising edge to Q output changing. However, for this ipop acts as a divide-by-2 circuit. The circuit is eec<vely a binary
the D-ipop to work properly, there are two other <ming parameters which counter.
are important: the setup <me and the hold <me. I will be talking about
these in a later lecture. This is a simple nite state machine because it has 8 states which cycles
through in a sequence.

When then use the Q0 output as the clock input the next stage etc. Note
that because the 2nd stage only starts to work once the rst stage is
completed, the propaga<on of eects ripples through the circuit hence
the name ripple counter.

This counter is also known as an asynchronous sequen<al circuit. It is
asynchronous because the output signals are NOT synchronised to a single
clock signal (since there are many clock signals), and sequen<al because its
output depends on previous output values in a sequence.

9 10
The ripple counter is poten<ally very slow. The delay between the ac<ve Last year you learned about implemen<ng digital circuits using gates such as
edge of the clock and the counter output giving the correct value is the one shown here. You can s<ll buy this chip with FOUR NAND gates and
dependent on the number of ipops and therefore the size of the counter. this is known as discrete logic. We generally do not use these any more. It is
A far beier approach is to use the ipops TOGETHER as a group, and clock slow, expensive, consume lots of energy and very hard to use.
them using THE SAME CLOCK signal as shown here. The Logic Block is a
combinatorial circuit which computes the next D value D2:0 from the current Nevertheless, it is good to learn about NAND and NOR gates because, suing
Q value Q2:0. The rela<onship is simply: D2:0 = Q2:0 + 1. Since D2:0 and De Morgans theorem, you could in theory design and implement a Pen<um
Q2:0 change within a frac<on of a nanosecond of each other, this circuit is: microprocessor using use two input NAND or NOR gates alone. It is therefore
1) faster than the ripple counter; 2) the delay is constant instead of could be regarded as the building block of all digital circuits. Similarly, you
dependent on the size of the counter. could in theory build a car using only basic lego blocks. Unfortunately such a
car would not be very good.
This circuit is known as a synchronous sequen<al circuit because its func<on
is synchronous to a single clock signal. If you regard the Q2:0 output value as
a state value, it follows a nite number of states in a dened sequence.
Therefore it is also a form of Finite State Machine.

Note the nota<on with the arrows.

11 12
In early days of integrated circuits, designers started using rows of basic Of course you can also customise everything each transistor and each
gates (lows of dark stu here). These are either completely customised (full- wiring connect in a full-custom manner. Here is the layout of Intel i7
custom) or it is made with standard rows of gates but leaving the gates microprocessor (with 4 cores). Designing such a circuit is very expensive,
unconnected. For a specic design, the gates are connect through wires in highly risky, and once designed, it cannot be changed.
the wiring channels. Therefore the customisa<on is only in the wiring metal
layers and not the layers with transistors. This is known as semi-custom Most applica<ons in electronic industry cannot aord to embark on such a
applica<on-specic integrated circuits (ASICs). design. This drives the rise of the Field Programmable Gate Array.

13 14
So what is a FPGA? You came across the idea of Programmable Logic Device Let us look inside an FPGA. Consider the logic block shown in blue in the last
in the rst year, where the user can program what the logic gate does (be it a slide (Altera calls their logic block a Logic Element (LE)). Typically an LE
NAND or NOR or some form of SUM-of-PRODUCT implementa<on) or an consists of a 4-input Look-up Table (LUT) and a D-ipop. Let us for now NOT
adder, you as a user, can program the chip to perform that logic func<on. to worry about how the 4-LUT is implemented internally. Just treat this as a
Now we can add another layer of user programmability you can program 4-input combinatorial circuit which produces one output signal as shown
how these logic gates are connected together! In that way, we have a here. The IMPORTANT characteris<c is that the 4-LUT can be user dened
general programmable logic chip. Unlike the microprocessor where the (or programmable) to implement ANY 4-input Boolean func<on.
program is just the instruc<on to x digital hardware, here you can program
the hardware itself!

The rst FPGA was introduced by Xilinx in 1985. It has arrays of logic blocks
which are programmable. It is surrounded by PROGRAMMABLE ROUTING
RESOURCES, which allows the user to dene the interconnec<ons between
the logic blocks. It also has lots of very exible input and output circuits
(programmable for TTL, CMOS and other interface standards).

Nowadays, there are two major players in the FPGA domain: Xilinx and
Altera. These two domains 90% of the FPGA market with roughly equal
share.

15 16
The Logic Elements are surrounded by lost lots of rou<ng wires and Let us now look at the FPGA that you will use for this course. The Altera
interconnec<on switches. Typically a signal wire to the Logic Block or Logic Cyclone III FPGA has a logic element following the BASIC LE structure above.
Element can be connected to any of these wiring channels through a There are some complicated modica<on in order to mark the LE more
programmable connec<on (essen<ally a digital switch). Xilinx FPGAs also useable. The slight addi<ons are:
have dedicated switch blocks shown here. Horizontal and ver<cal wires can 1. The 4-input Look-up Table (4-LUT) also include special circuit to
be connected through such as switch block with programmable switches implement the carry-chain in a binary adder;
(dont worry for now how thats done). 2. Input 3 of the 4-LUT could be programmed to be a feedback signal from
the register output;
FPGAs have huge amount of these programmable resources and switches. 3. There is extra logic circuit to control the clock, reset and preset (i.e.
Typically a very small percentage of these are being connected (i.e. ON) for a preload) of the D-ipop;
given applica<on. 4. There is also a bypass circuit in order to provide chaining of registers from
the previous and next stage to make good shiF registers.
The main advantage and power of FPGA comes from the programmable
interconnect more so than the programmable logic. The Cyclone III contains over 15,000 Logic Elements. Puzng this in context,
you could put onto this one chip 481 32-bit binary adder circuits or 320bit
binary counters!

17 18
Logic Elements (LEs) are grouped together into blocks of 16 called Logic Programming a FPGA is called congura<on. In programming a computer or
Array Blocks (LABs) (i.e. 16 LE = 1 LAB). The LEs inside a LAB have short and microprocessor, we send to the computer instruc<on codes as 1s and 0s. These
<ghtly coupled Local Interconnect circuits. In that way, one could implement are interpreted by the computer which will follow the instruc<on to perform tasks.
16-bit adders or counters which are fast and ecient in rou<ng resources. The microprocessor needs to be fed these program codes con<nuously for it to
func<on.
The LABs are arranged in rows with horizontal and ver<cal interconnec<ons.
Therefore Cyclone III have three types of interconnect resources: local, In FPGAs, you only need to congure the chip ONCE on power-up. You download to
ver<cal and horizontal. the chip a BITSTREAM (also bits in 1s and 0s.) ThereaFer, the chip will behave as
you have designed it to.
Cyclone III also contains other type of logic resources such as blocks of
memory circuits, clock genera<ng circuits (known as Phase Locked Loops or What happens when you congure an FPGA? Let us consider 4-input LUTs circuit.
PLL) and mul<ply circuits. We will learn about this much later. This is typically implement using a tree of four layers of 2-input to 1-output
mul<plexers. The en<re circuit is a 16-to-1 mul<plexer using the 4-LUT inputs ABCD
as the control of the MUX tree. For example, if ABCD = 0000, then the top most
input of the MUX is routed to Y output.

In this way, ABCD forms the input columns of a truth table. For 4-inputs, the truth
table has 16 entries. The output Y for each of the truth table entry corresponds to
the input of the MUX. Congura<on involves xing the inputs to the 16-to-1 MUX by
storing 1 or 0 in the registers R. Changing the 16 values stored, you can change to
truth-table to anything you want.

19 20
To congure the programmable rou<ng, let us look at how the rou<ng circuit works. For this course, you will be designing circuits using the free version of the
Take Xilinx SWITCH BLOCK circuit (green blocks in slide 17). This block controls the design suite known as Quartus II from Altera. You can download your own
connec<ons between four horizontal channels and four ver<cal channels. The copy onto your notebook machine, or you can use the versions that are
diamond shaped block is a poten<al interconnect site. Inside the switch block installed in any PCs located anywhere in the department.
circuit, there are 6 transistor switches which are ini<ally all OFF (or open circuit).
Nothing is connected up). This very powerful design tool contains everything you need to design a
complex digital system ON YOUR OWN COMPUTER!
The gate input of EACH switch is controlled by the output of a 1-bit register (the
circuit is that of a simple 1-bit sta<c memory circuit). If the register stores a 1, the
rou<ng transistor will have its gate driven high. Since the transistor is a nMOS
transistor, it will become conduc<ng. In this way, conguring rou<ng simply means
that the correct 1s and 0s are stored in the registers that control these rou<ng
transistors.

As you would expect, typically a FPGA would have hundreds of thousands of these
rou<ng switches, most of these are OFF. Once programmed, the interconnec<ons
are made. The bold lines shows the programmed connec<ons.

Bitsteam informa<on used for congura<on purpose are usually stored on a ash memory
chip, which is download to the FPGA during power-up similar to boo<ng up a computer,
you congure the FPGA. Alterna<vely you can send the bitstream to the FPGA via a
computer connec<on to the chip. On DE0, it does both. Powerup DE0 will congure the
Cyclone III to a wai<ng mode, which makes the DE0 board talk to the computer via the
USB port. You then send the bitstream of your design using the USB port.

21 22
This slide shows you the func<onal blocks of the DE0 board. This has I also provide a purpose-built ADC/DAC board to support the lab experiment.
everything you need test basic designs involving switches, 7-segment displays This add-on board in only needed when you start the lab. So for now, you
and even a VGA output. can ignore it.

23 24